research-article

Detecting Software Cache Coherence Violations in MPSoC Using Traces Captured on Virtual Platforms

Authors:

Marcos Aurélio Pinto Cunha,

Omayma Matoussi,

Frédéric PétrotAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 16, Issue 2

Article No.: 30, Pages 1 - 21

https://doi.org/10.1145/2990193

Published: 02 January 2017 Publication History

Abstract

Software cache coherence schemes tend to be the solution of choice in dedicated multi/many core systems on chip, as they make the hardware much simpler and predictable. However, despite the developers’ effort, it is hard to make sure that all preventive measurements are taken to ensure coherence. In this work, we propose a method to identify the potential cache coherence violations using traces obtained from virtual platforms. These traces contain causality relations among events, which allow first to simplify the analysis, and second to avoid relying on timestamps. Our method identifies potential violations that may occur during a given execution for write-through and write-back cache policies. Therefore, it is independent of the software coherence protocol. We conducted experiments on parallel applications running on a lightweight SMP operating system, and we were able to detect coherence issues that we could then solve.

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Cited By

Zu Y(2020)Deep learning parallel computing and evaluation for embedded system clustering architecture processorDesign Automation for Embedded Systems10.1007/s10617-020-09235-5Online publication date: 7-Mar-2020
https://doi.org/10.1007/s10617-020-09235-5
Lyu YQin XChen MMishra P(2018)Directed Test Generation for Validation of Cache Coherence ProtocolsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.280123938:1(163-176)Online publication date: 18-Dec-2018
https://dl.acm.org/doi/10.1109/TCAD.2018.2801239

Index Terms

Detecting Software Cache Coherence Violations in MPSoC Using Traces Captured on Virtual Platforms
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multicore architectures
2. Computing methodologies
  1. Modeling and simulation
    1. Simulation support systems
      1. Simulation tools

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Information & Contributors

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 16, Issue 2

Special Issue on LCETES 2015, Special Issue on ACSD 2015 and Special Issue on Embedded Devise Forensics and Security

May 2017

705 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/3025020

Editor:
Sandeep K. Shukla
Indian Institute of Technology, India

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Copyright © 2017 ACM.

© 2017 Association for Computing Machinery. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of a national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 02 January 2017

Accepted: 01 August 2016

Revised: 01 May 2016

Received: 01 August 2015

Published in TECS Volume 16, Issue 2

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Ministry of Education of Brazil through the CAPES Foundation
French Ministry of Industry through the SoCTrace FUI project

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Cited By

Zu Y(2020)Deep learning parallel computing and evaluation for embedded system clustering architecture processorDesign Automation for Embedded Systems10.1007/s10617-020-09235-5Online publication date: 7-Mar-2020
https://doi.org/10.1007/s10617-020-09235-5
Lyu YQin XChen MMishra P(2018)Directed Test Generation for Validation of Cache Coherence ProtocolsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.280123938:1(163-176)Online publication date: 18-Dec-2018
https://dl.acm.org/doi/10.1109/TCAD.2018.2801239

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