MAX32561-LNJ+中文资料亚德诺数据手册PDF规格书

Benefits and Features

● Arm Cortex M3 Processor Core Allows for Easy

Integration into Applications

• 108MHz Core Operating Frequency Through PLL

• 1MB Dual-Bank Flash Memory with Cache

• 384KB System SRAM

• 8KB AES Self-Encrypted NVSRAM

● Security Features Facilitate System-Level Protection

• ISO 14443 type A/B EMV Compliant Contactless

Reader with Internal Transceiver

• Secure Boot Loader with Public Key Authentication

• AES, DES and SHA Hardware Accelerators

• Modulo Arithmetic Hardware Accelerator (MAA)

Supporting RSA, DSA, and ECDSA

• 9-Line Secure Keypad Controller

• Hardware True Random-Number Generator

• Die Shield with Dynamic Fault Detection

• 6 External Tamper Sensors with Independent

Random Dynamic Patterns

• 256-Bit Flip-Flop-Based Battery-Backup AES Key

Storage

• Temperature and Voltage Tamper Monitor

• Real-Time Clock

● Integrated Peripherals Reduce External Component Count

• Triple-Track Magnetic Stripe Head Interface

• One ISO 7816 Smart Card Interface with Integrated

Transceiver (1.8V, 3V, and 5V) and One Smart Card

Interface Only

• USB 2.0 Device with Internal Transceiver and

Dedicated PLL

• 2 SPI Ports, 2 UART Ports, and I2C Controller

• 6 Timers, 2 with PWM Capability

• Up to 39 General-Purpose I/O Pins

• 1-Channel, 10-Bit ADC

• 4-Channel DMA Controller

• 1 SPI Execute in Place (XiP) Master

● Power Management Optimizes Battery Life and

Reduces Active Power Consumption

• Single 3.3V Supply Operation*

• Integrated Battery-Backup Switch

• Clock Gating Function

• Low-Current Battery-Backup Operation

Applications

● PCI Mobile Payment Terminals (mPOS)

● ATM Keyboards

● EMV Card Reader

● Contact/Contactless Pin Pads