MC10162中文资料安森美半导体数据手册PDF规格书

Binary to 1-8 Decoder (High)

The MC10162 is designed to convert three lines of input data to a one–of–eight output. The selected output will be high while all other outputs are low. The enable inputs, when either or both are high, force all outputs low.

The MC10162 is a true parallel decoder. No series gating is used internally, eliminating unequal delay times found in other decoders. This device is ideally suited for demultiplexer applications. One of the two enable inputs is used as the data input, while the other is used as a data enable input.

A complete mux/demux operation on 16 bits for data distribution is illustrated in Figure 1 of the MC10161 data sheet.

• PD = 315 ns typ/pkg (No Load)

• tpd = 4.0 ns typ

• tr, tf = 2.0 ns typ (20–80)