ATSAM3N0AA-MU中文资料爱特梅尔数据手册PDF规格书

SAM3N Description

Atmels SAM3N series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 48 MHz and features up to 256 Kbytes of Flash and up to 24 Kbytes of SRAM. The peripheral set includes 2x USARTs, 2x UARTs, 2x TWIs, 3x SPI, as well as 1 PWM timer, 6x general purpose 16-bit timers, an RTC, a 10-bit ADC and a 10-bit DAC.

Features

• Core

– ARM® Cortex®-M3 revision 2.0 running at up to 48 MHz

– Thumb®-2 instruction

– 24-bit SysTick Counter

– Nested Vector Interrupt Controller

• Pin-to-pin compatible with SAM7S legacy products (48- and 64-pin versions) and SAM3S (48-, 64- and 100-pin versions)

• Memories

– From 16 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator, single plane

– From 4 to 24 Kbytes embedded SRAM

– 16 Kbytes ROM with embedded bootloader routines (UART) and IAP routines

• System

– Embedded voltage regulator for single supply operation

– Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation

– Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure Detection and optional low power 32.768 kHz for RTC or device clock

– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default frequency for device startup. In-application trimming access for frequency adjustment

– Slow Clock Internal RC oscillator as permanent low-power mode device clock

– One PLL up to 130 MHz for device clock

– Up to 10 peripheral DMA (PDC) channels

• Low Power Modes

– Sleep and Backup modes, down to 3 µA in Backup mode

– Ultra low power RTC

• Peripherals

– Up to 2 USARTs with RS-485 and SPI mode support. One USART (USART0) has ISO7816, IrDA® and PDC support in addition

– Two 2-wire UARTs

– 2 Two Wire Interface (I2C compatible), 1 SPI

– Up to 6 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and PWM mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor

– 4-channel 16-bit PWM

– 32-bit Real-time Timer and RTC with calendar and alarm features

– Up to 16 channels, 384 KSPS 10-bit ADC

– One 500 KSPS 10-bit DAC

• I/O

– Up to 79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die Series Resistor Termination

– Three 32-bit Parallel Input/Output Controllers

• Packages

– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm

– 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm

– 48-lead LQFP, 7 x 7 mm, pitch 0.5 mm/48-pad QFN 7x7 mm, pitch 0.5 mm