AD9575集成电路（IC）应用特定时钟/定时规格书PDF中文资料

GENERAL DESCRIPTION

The AD9575 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for network clocking. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize line card performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

FEATURES

Fully integrated VCO/PLL core

0.39 ps rms jitter from 12 kHz to 20 MHz at 156.25 MHz

0.15 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz

0.40 ps rms jitter from 12 kHz to 20 MHz at 106.25 MHz

0.15 ps rms jitter from 637 kHz to 10 MHz at 106.25 MHz

Input crystal frequency of 19.44 MHz, 25 MHz, or

25.78125 MHz

Pin selectable divide ratios for 33.33 MHz, 62.5 MHz,

100 MHz, 106.25 MHz, 125 MHz, 155.52 MHz, 156.25 MHz,

159.375 MHz, 161.13 MHz, and 312.5 MHz outputs

LVDS/LVPECL/LVCMOS output format

Integrated loop filter

Space saving 4.4 mm × 5.0 mm TSSOP

100 mA power supply current (LVDS output)

120 mA power supply current (LVPECL output)

3.3 V operation

APPLICATIONS

GbE/FC/SONET line cards, switches, and routers

CPU/PCI-E applications

Low jitter, low phase noise clock generation

AD9575属于集成电路（IC） > 应用特定时钟/定时。亚德诺半导体技术有限公司制造生产的AD9575应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。