1. General description

The HEF4027B is a dual positive-edge triggered JK flip-flop featuring independent set direct (nSD),

clear direct (nCD), clock inputs (nCP) and complementary outputs (nQ and nQ). Data is accepted

when nCP is LOW, and transferred to the output on the positive-going edge of the clock. The

asynchronous clear-direct (nCD) and set-direct (nSD) are independent and override the nJ, nK,

and nCP inputs. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower

clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting

resistors to interface inputs to voltages in excess of VDD.

2. Features and benefits

• Wide supply voltage range from 3.0 V to 15.0 V

• CMOS low power dissipation

• High noise immunity

• Fully static operation

• 5 V, 10 V, and 15 V parametric ratings

• Standardized symmetrical output characteristics

• Complies with JEDEC standard JESD 13-B

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-B exceeds 200 V

• Specified from -40 °C to +85 °C

3. Applications

• Registers

• Counters

• Control circuits

HEF4027B属于集成电路（IC） > 触发器。安世半导体(中国)有限公司制造生产的HEF4027B触发器触发器是能够存储单个逻辑状态或信息“位”的基本数字存储器件。这些器件至少有两个输入；一个或多个用于传递要存储的数据，另一个用于指示存储该数据的时间点。不同的触发器类型，例如 D（延迟）、SR（置位复位）和 JK，对提供给其输入的信号有不同的响应，可用于实现不同的逻辑功能。这些器件与锁存器的不同之处在于它们是边缘敏感器件，其保持的逻辑状态仅在接收到有效时钟信号时才会改变。