LRS1341中文资料夏普微数据手册PDF规格书

DESCRIPTION

The LRS1341/LRS1342 is a combination memory organized as 1,048,576 × 16-bit flash memory and 131,072 × 16-bit static RAM in one package.

FEATURES

• Flash Memory and SRAM

• Stacked Die Chip Scale Package

• 72-ball CSP (FBGA072-P-0811) plastic package

• Power supply: 2.7 V to 3.6 V

• Operating temperature: -25°C to +85°C

• Flash Memory

– Access time (MAX.): 100 ns

– Operating current (MAX.):

The current for F-VCC pin

– Read: 25 mA (tCYCLE = 200 ns)

– Word write: 17 mA

– Block erase: 17 mA

– Deep power down current (the current for

F-VCC pin): 10 µA (MAX. F-CE ≥ F-VCC - 0.2 V,

F-RP ≤-0.2 V, F-VPP ≤0.2 V)

– Optimized array blocking architecture

– Two 4K-word boot blocks

– Six 4K-word parameter blocks

– Thirty-one 32K-word main blocks

– Top/Bottom boot location versions

– Extended cycling capability

– 100,000 block erase cycles

– Enhanced automated suspend options

– Word write suspend to read

– Block erase suspend to word write

– Block erase suspend to read

• SRAM

– Access time (MAX.): 85 ns

– Operating current (MAX.):

– 45 mA

– 8 mA (tRC, tWC = 1 µs)

– Standby current: 45 µA (MAX.)

– Data retention current: 35 µA (MAX.)