MM74HC597 8-Bit Shift Registers with Input Latches
January 1988
Revised August 2000
MM74HC597
8-Bit Shift Registers with Input Latches
General Description
This high speed register utilizes advanced silicon-gate
CMOS technology. It has the high noise immunity and low
power consumption of standard CMOS integrated circuits,
as well as the ability to drive 10 LS-TTL loads.
The MM74HC597 comes in a 16-pin package and consists
of an 8-bit storage latch feeding a parallel-in, serial-out
8-bit shift register. Both the storage register and shift regis-
ter have positive-edge triggered clocks. the shift register
also has direct load (from storage) and clear inputs.
The 74HC logic family is speed, function, and pin-out com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to V
CC
and ground.
Features
s
8-bit parallel storage register inputs
s
Wide operating voltage range: 2V鈥?V
s
Shift register has direct overriding load and clear
s
Guaranteed shift frequency: DC to 30 MHz
s
Low quiescent current: 80
碌
A maximum
Ordering Code:
Order Number
MM74HC597M
MM74HC597SJ
MM74HC597N
Package Number
M16A
M16D
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Truth Table
RCK SCK SLOAD SCLR
Function
Data Loaded to input latches
Data loaded from inputs to
shift register
Data transferred from
X
L
H
input latches to shift
register
Invalid logic, state of
X
X
X
X
X
L
H
H
L
L
H
shift register indeterminate
when signals removed
Shift register cleared
Shift register clocked
Q
n
=
Q
n
鈭?/div>
1, Q
0
=
SER
鈫?/div>
鈫?/div>
No
clock
edge
X
X
X
L
X
H
鈫?/div>
Top View
漏 2000 Fairchild Semiconductor Corporation
DS005343
www.fairchildsemi.com