CD4077BE各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

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产品型号CD4077BE的概述

芯片CD4077BE的概述与详细参数 CD4077BE是一款广泛应用于数字电路设计中的CMOS四输入异或门（XOR gate），隶属于CD4000系列系列的增强型CMOS IC。这款芯片能够处理多种数字信号，适用于逻辑运算、数据处理以及各种数字系统的集成。详细参数 CD4077BE的主要电气特性和工作参数如下： 1. 电源电压（VDD）：3V至15V，通常在逻辑电路中使用的电压为5V或12V。 2. 输入电压（VI）：最大值为VDD。 3. 输出电压（VO）：接近接地（0V）和VDD之间。 4. 工作温度范围：从-55°C到125°C，适合于各种恶劣环境下使用的应用。 5. 逻辑高电平电压阈值（VTH）》：大约是VDD的70%。 6. 逻辑低电平电压阈值（VTL）」：大约是VDD的30%。 7. 输入电流（II）：极小，通常只有几个微安，使其在低功耗设计中表现卓越。 8. 输出电流（...

产品型号CD4077BE的Datasheet PDF文件预览

CD4070B,

CD4077B

Data sheet acquired from Harris Semiconductor

SCHS055

CMOS Quad Exclusive-OR

and Exclusive-NOR Gate

January 1998

Features

Description

• High-Voltage Types (20V Rating)

• CD4070B - Quad Exclusive-OR Gate

• CD4077B - Quad Exclusive-NOR Gate

• Medium Speed Operation

The Harris CD4070B contains four independent Exclusive-

OR gates. The Harris CD4077B contains four independent

Exclusive-NOR gates.

[ /Title

(CD40

70B,

CD407

7B)

/Sub-

ject

(CMO

SQuad

Exclu-

sive-

The CD4070B and CD4077B provide the system designer

with a means for direct implementation of the Exclusive-OR

and Exclusive-NOR functions, respectively.

- t

, t

PHL PLH

= 65ns (Typ) at V = 10V, C = 50pF

DD L

• 100% Tested for Quiescent Current at 20V

• Standardized Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

Ordering Information

TEMP.

PKG.

NO.

PART NUMBER RANGE ( C)

PACKAGE

-55 to 125 14 Ld PDIP

• Maximum Input Current of 1µA at 18V Over Full

Package Temperature Range

CD4070BE

CD4077BE

CD4070BF

CD4077BF

CD4070BM

CD4077BM

E14.3

- 100nA at 18V and 25 C

E14.3

• Noise Margin (Over Full Package Temperature Range)

and

- 1V at V

= 5V, 2V at V

= 10V, 2.5V at V

= 15V

-55 to 125 14 Ld CERDIP

-55 to 125 14 Ld SOIC

F14.3

• Meets All Requirements of JEDEC Standard No. 13B,

“Standard Speciﬁcations for Description of ‘B’ Series

CMOS Devices

F14.3

Exclu-

sive-

NOR

Gate)

/Autho

r ()

M14.15

Applications

• Logical Comparators

• Adders/Subtractors

/Key-

words

(Har-

ris

Semi-

con-

• Parity Generators and Checkers

Pinouts

CD4070B

(PDIP, CERDIP, SOIC)

TOP VIEW

CD4077B

(PDIP, CERDIP, SOIC)

TOP VIEW

ductor,

CD400

metal

gate,

CMOS

, pdip,

cerdip,

mil,

J = A

K = C

J = A

K = C

11 M = G

10 L = E

11 M = G

10 L = E

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 910.1

CD4070B, CD4077B

Functional Diagrams

CD4070B

CD4077B

J = A

K =

K = C

M = G

L = E

M = G

L = E

= 7

= 14

B †

2(5,9,12)

3(4,10,11)

A †

3(4,10,11)

A †

1(6,8,13)

† INPUTS PROTECTED

BY CMOS PROTECTION

NETWORK

BY CMOS PROTECTION

NETWORK

FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B

(1 OF 4 IDENTICAL GATES)

FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B

(1 OF 4 IDENTICAL GATES)

CD4070B TRUTH TABLE (1 OF 4 GATES)

CD4077B TRUTH TABLE (1 OF 4 GATES)

NOTE:

1 = High Level

0 = Low Level

1 = High Level

0 = Low Level

J = A

CD4070B, CD4077B

Absolute Maximum Ratings

Thermal Information

DC Supply Voltage Range (V ) . . . . . . . . . . . . . . . . . -0.5V to 20V Thermal Resistance (Typical, Note 1)

( C/W)

Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5V to V

DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 10mA

0.5V

PDIP Package . . . . . . . . . . . . . . . . . . .

CERDIP Package . . . . . . . . . . . . . . . .

SOIC Package. . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature (Hermetic Package or Die)175 C

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C

175

N/A

Operating Conditions

Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C

Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C

Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 3V to 18V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θ is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Speciﬁcations

LIMITS AT INDICATED TEMPERATURES ( C)

CONDITIONS

PARAMETER

(V)

0, 5

0, 10

0, 15

0, 20

0, 5

0, 10

0, 15

0, 5

0, 10

0, 15

0, 5

0, 10

0, 15

0, 5

0, 10

0, 15

(V)

-55

0.25

0.5

-40

0.25

0.5

7.5

125

7.5

MIN

TYP

0.01

0.02

MAX

UNITS

µA

Quiescent Device Current

0.25

Max

0.5

150

0.42

1.1

2.8

-0.42

-1.3

-1.1

-2.8

0.05

4.95

9.95

14.95

1.5

150

0.36

0.9

Output Low (Sink) Current

Min

0.4

0.64

1.6

4.2

-0.64

-2

0.61

1.5

0.51

1.3

3.4

-0.51

-1.6

-1.3

-3.4

0.5

2.6

6.8

-1

1.5

2.4

Output High (Source) Current

Min

4.6

-0.61

-1.8

-1.5

-4

-0.36

-1.15

-0.9

-2.4

0.05

4.95

9.95

14.95

1.5

2.5

-3.2

-2.6

-6.8

9.5

-1.6

-4.2

0.05

4.95

9.95

14.95

1.5

13.5

Output Voltage: Low Level,

Max

0.05

4.95

9.95

14.95

1.5

0.05

Output Voltage: High Level,

Min

4.95

9.95

14.95

Input Low Voltage,

Max

0.5, 4.5

1, 9

1.5

1.5, 13.5

0.5, 4.5

1, 9

Input High Voltage,

Min

3.5

1.5, 13.5

-5

±10

Input Current, I Max

0, 18

±0.1

±1

±0.1

µA

CD4070B, CD4077B

AC Electrical Speciﬁcations

T = 25 C, Input t , t = 20ns, C = 50pF, R = 200kΩ

TEST CONDITIONS

LIMITS ON ALL TYPES

PARAMETER

SYMBOL

(V)

TYP

140

MAX

280

130

100

200

100

UNITS

Propagation Delay Time

, t

PHL PLH

Transition Time

, t

THL TLH

100

Input Capacitance

Any Input

7.5

Typical Performance Curves

= 25 C

T = 25 C

GATE TO SOURCE VOLTAGE (V ) = 15V

12.5

GATE TO SOURCE VOLTAGE (V ) = 15V

10V

7.5

2.5

, DRAIN TO SOURCE VOLTAGE (V)

V , DRAIN TO SOURCE VOLTAGE (V)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

, DRAIN TO SOURCE VOLTAGE (V)

-15

-10

-5

-15

-10

-5

= 25 C

-5

GATE TO SOURCE VOLTAGE (V ) = -5V

-10

-15

-20

-25

-30

-5

-10V

-10

-15

-15V

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

CD4070B, CD4077B

Typical Performance Curves (Continued)

= 25 C

300

200

100

200

150

100

SUPPLY VOLTAGE (V ) = 5V

10V

15V

100

110

C , LOAD CAPACITANCE (pF)

FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF

LOAD CAPACITANCE

FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A

FUNCTION OF LOAD CAPACITANCE

= 25 C

LOAD CAPACITANCE C = 50pF

300

200

100

10V

= 50pF

10V

= 15pF

-1

, SUPPLY VOLTAGE (V)

f , INPUT FREQUENCY (kHz)

FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A

FUNCTION OF SUPPLY VOLTAGE

FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A

FUNCTION OF INPUT FREQUENCY

CD4070B, CD4077B

Dual-In-Line Plastic Packages (PDIP)

E14.3 (JEDEC MS-001-AA ISSUE D)

14 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INDEX

AREA

INCHES

MILLIMETERS

1 2

N/2

SYMBOL

MIN

MAX

0.210

MIN

MAX

5.33

NOTES

-B-

-A-

0.015

0.115

0.014

0.045

0.008

0.735

0.005

0.300

0.240

0.39

2.93

0.356

1.15

0.204

18.66

0.13

7.62

6.10

BASE

PLANE

0.195

0.022

0.070

0.014

0.775

4.95

0.558

1.77

0.355

19.68

-C-

SEATING

PLANE

e_A

e_C

e_B

0.010 (0.25)

0.325

0.280

8.25

7.11

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English

and Metric dimensions, the inch dimensions control.

0.100 BSC

0.300 BSC

2.54 BSC

7.62 BSC

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication No. 95.

0.430

0.150

10.92

3.81

0.115

2.93

4. Dimensions A, A1 and L are measured with the package seated in

JEDEC seating plane gauge GS-3.

Rev. 0 12/93

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and

dicular to datum

7. e and e are measured at the lead tips with the leads uncon-

are measured with the leads constrained to be perpen-

-C-

strained. e must be zero or greater.

8. B1maximumdimensionsdonotincludedambarprotrusions. Dambar

protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,

E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -

1.14mm).

CD4070B, CD4077B

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

c1 LEAD FINISH

F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)

14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

-D-

-A-

INCHES MILLIMETERS

MIN

BASE

(c)

METAL

SYMBOL

MAX

0.200

0.026

0.023

0.065

0.045

0.018

0.015

0.785

0.310

MIN

MAX

5.08

0.66

0.58

1.65

1.14

0.46

0.38

19.94

7.87

NOTES

0.014

0.045

0.023

0.008

0.36

1.14

0.58

0.20

-B-

(b)

SECTION A-A

bbb

C A - B

BASE

PLANE

-C-

SEATING

PLANE

A A

0.220

5.59

C A - B

eA/2

0.100 BSC

2.54 BSC

eA/2

0.300 BSC

0.150 BSC

7.62 BSC

3.81 BSC

ccc

aaa

C A - B

NOTES:

0.125

0.200

0.060

3.18

5.08

1.52

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded

area shown. The manufacturer’s identification shall not be used

as a pin one identification mark.

0.015

0.005

0.38

0.13

105

2. The maximum limits of lead dimensions b and c or M shall be

measured at the centroid of the finished lead surfaces, when

solder dip or tin plate lead finish is applied.

aaa

bbb

ccc

0.015

0.030

0.010

0.0015

0.38

0.76

0.25

0.038

3. Dimensions b1 and c1 apply to lead base metal only. Dimension

M applies to lead plating and finish thickness.

2, 3

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a

partial lead paddle. For this configuration dimension b3 replaces

dimension b2.

Rev. 0 4/94

5. This dimension allows for off-center lid, meniscus, and glass

overrun.

6. Dimension Q shall be measured from the seating plane to the

base plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

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CD4077BE产品参数

型号:	CD4077BE
生命周期：	Obsolete
包装说明：	DIP, DIP14
Reach Compliance Code：	unknown
风险等级：	5.76
系列：	4000/14000/40000
JESD-30 代码：	R-PDIP-T14
功能数量：	4
输入次数：	2
端子数量：	14
最高工作温度：	85 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP
封装等效代码：	DIP14
封装形状：	RECTANGULAR
封装形式：	IN LINE
施密特触发器：	NO
最大供电电压 (Vsup)：	18 V
最小供电电压 (Vsup)：	3 V
表面贴装：	NO
技术：	CMOS
温度等级：	INDUSTRIAL
端子形式：	THROUGH-HOLE
端子位置：	DUAL
Base Number Matches：	1

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产品型号CD4077BE的概述

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