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    产品型号CD74HCT157M96E4的Datasheet PDF文件预览

    The CD54HC158 and  
    CD74HC158 are obsolete and  
    no longer are supplied.  
    CD54/74HC157, CD54/74HCT157,  
    CD54/74HC158, CD54/74HCT158  
    Data sheet acquired from Harris Semiconductor  
    SCHS153C  
    High-Speed CMOS Logic  
    Quad 2-Input Multiplexers  
    September 1997 - Revised October 2003  
    Features  
    Description  
    • Common Select Inputs  
    • Separate Enable Inputs  
    • Buffered inputs and Outputs  
    • Fanout (Over Temperature Range)  
    The ’HC157, ’HCT157, ’HC158, and ’HCT158 are quad 2-  
    input multiplexers which select four bits of data from two  
    sources under the control of a common Select input (S). The  
    Enable input (E) is active Low. When (E) is High, all of the  
    outputs in the 158, the inverting type, (1Y-4Y) are forced  
    High and in the 157, the non-inverting type, all of the outputs  
    [ /Title  
    (CD74H  
    C157,  
    CD74H  
    CT157,  
    CD74H  
    C158,  
    CD74H  
    CT158)  
    /Subject  
    (High  
    - Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
    (1Y-4Y) are forced Low, regardless of all other input  
    - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads conditions.  
    o
    o
    • Wide Operating Temperature Range . . . -55 C to 125 C Moving data from two groups of registers to four common  
    output buses is a common use of these devices. The state of  
    the Select input determines the particular register from  
    which the data comes. They can also be used as function  
    generators.  
    • Balanced Propagation Delay and Transition Times  
    • Significant Power Reduction Compared to LSTTL  
    Logic ICs  
    • HC Types  
    Ordering Information  
    - 2V to 6V Operation  
    Speed  
    - High Noise Immunity: N = 30%, N = 30%of V at  
    CC  
    TEMP. RANGE  
    o
    IL  
    IH  
    PART NUMBER  
    CD54HC157F3A  
    CD54HCT157F3A  
    CD54HCT158F3A  
    CD74HC157E  
    ( C)  
    PACKAGE  
    16 Ld CERDIP  
    16 Ld CERDIP  
    16 Ld CERDIP  
    16 Ld PDIP  
    16 Ld SOIC  
    16 Ld SOIC  
    16 Ld SOIC  
    16 Ld PDIP  
    16 Ld SOIC  
    16 Ld SOIC  
    16 Ld SOIC  
    16 Ld PDIP  
    V
    = 5V  
    CC  
    • HCT Types  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    - 4.5V to 5.5V Operation  
    - Direct LSTTL Input Logic Compatibility,  
    V = 0.8V (Max), V = 2V (Min)  
    IL IH  
    - CMOS Input Compatibility, I ≤ 1µA at V , V  
    OL OH  
    l
    CD74HC157M  
    Pinout  
    CD74HC157MT  
    CD74HC157M96  
    CD74HCT157E  
    CD74HCT157M  
    CD74HCT157MT  
    CD74HCT157M96  
    CD74HCT158E  
    CD54HC157, CD54HCT157, CD54HC158, CD54HCT158  
    (CERDIP)  
    CD74HC157, CD74HCT157, CD74HC158  
    (PDIP, SOIC)  
    CD74HCT158  
    (PDIP)  
    TOP VIEW  
    S
    1
    2
    3
    4
    5
    6
    7
    8
    16 V  
    15 E  
    CC  
    1I  
    0
    1
    1I  
    14 4I  
    13 4I  
    0
    1
    NOTE: When ordering, use the entire part number. The suffix 96  
    denotes tape and reel. The suffix T denotes a small-quantity reel of  
    250.  
    1Y  
    2I  
    2I  
    12 4Y  
    0
    1
    11 3I  
    10 3I  
    0
    1
    2Y  
    9
    3Y  
    GND  
    CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
    Copyright © 2003, Texas Instruments Incorporated  
    1
    CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158  
    Functional Diagram  
    HC/HCT HC/HCT  
    157  
    158  
    2
    3
    1I  
    1I  
    4
    0
    1Y  
    1Y  
    1
    5
    6
    7
    2I  
    2I  
    0
    2Y  
    3Y  
    4Y  
    2Y  
    3Y  
    4Y  
    1
    11  
    10  
    3I  
    3I  
    9
    0
    1
    14  
    13  
    4I  
    4I  
    12  
    0
    1
    1
    15  
    S
    E
    TRUTH TABLE  
    DATA INPUTS  
    OUTPUT  
    SELECT  
    INPUT  
    ENABLE  
    157  
    158  
    Y
    E
    H
    L
    L
    L
    L
    S
    X
    L
    I0  
    X
    L
    I1  
    X
    X
    X
    L
    Y
    L
    H
    L
    H
    L
    H
    X
    X
    H
    L
    L
    H
    H
    H
    H
    H
    L
    H = High Voltage Level, L = Low Voltage Level, X = Don’t Care  
    2
    CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158  
    Absolute Maximum Ratings  
    Thermal Information  
    o
    DC Supply Voltage, V  
    . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
    Thermal Resistance (Typical, Note 1)  
    θ
    ( C/W)  
    CC  
    DC Input Diode Current, I  
    For V < -0.5V or V > V  
    JA  
    IK  
    E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .  
    M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .  
    67  
    73  
    + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
    OK  
    For V < -0.5V or V > V  
    I
    I
    CC  
    o
    DC Output Diode Current, I  
    Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C  
    Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
    Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
    o
    o
    + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
    O
    O
    CC  
    o
    DC Output Source or Sink Current per Output Pin, I  
    O
    For V > -0.5V or V < V  
    + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
    O
    O
    CC  
    (SOIC - Lead Tips Only)  
    DC V  
    or Ground Current, I  
    I
    . . . . . . . . . . . . . . . . . .±50mA  
    CC  
    CC or GND  
    Operating Conditions  
    o
    o
    Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
    A
    Supply Voltage Range, V  
    CC  
    HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
    HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
    DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
    I
    O
    CC  
    Input Rise and Fall Time  
    2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
    4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
    6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
    CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
    of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
    NOTE:  
    1. The package thermal impedance is calculated in accordance with JESD 51-7.  
    DC Electrical Specifications  
    TEST  
    CONDITIONS  
    o
    o
    o
    o
    o
    25 C  
    -40 C TO 85 C -55 C TO 125 C  
    V
    CC  
    PARAMETER  
    HC TYPES  
    SYMBOL  
    V (V)  
    I
    I
    (mA)  
    (V)  
    MIN  
    TYP  
    MAX  
    MIN  
    MAX  
    MIN  
    MAX  
    UNITS  
    O
    High Level Input  
    Voltage  
    V
    -
    -
    -
    2
    4.5  
    6
    1.5  
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    1.5  
    -
    1.5  
    -
    -
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    µA  
    IH  
    3.15  
    -
    -
    3.15  
    -
    -
    3.15  
    4.2  
    4.2  
    4.2  
    -
    Low Level Input  
    Voltage  
    V
    -
    2
    -
    0.5  
    1.35  
    1.8  
    -
    -
    0.5  
    1.35  
    1.8  
    -
    -
    0.5  
    1.35  
    1.8  
    -
    IL  
    4.5  
    6
    -
    -
    -
    -
    -
    -
    High Level Output  
    Voltage  
    CMOS Loads  
    V
    V
    or V  
    IH IL  
    -0.02  
    2
    1.9  
    1.9  
    1.9  
    OH  
    -0.02  
    -0.02  
    -
    4.5  
    6
    4.4  
    -
    4.4  
    -
    4.4  
    -
    5.9  
    -
    5.9  
    -
    5.9  
    -
    High Level Output  
    Voltage  
    TTL Loads  
    -
    -
    -
    -
    -
    -
    -
    -4  
    4.5  
    6
    3.98  
    -
    3.84  
    -
    3.7  
    -
    -5.2  
    0.02  
    0.02  
    0.02  
    -
    5.48  
    -
    5.34  
    -
    5.2  
    -
    Low Level Output  
    Voltage  
    CMOS Loads  
    V
    V
    or V  
    IH IL  
    2
    -
    -
    -
    -
    -
    -
    -
    0.1  
    0.1  
    0.1  
    -
    -
    -
    -
    -
    -
    -
    -
    0.1  
    0.1  
    0.1  
    -
    -
    -
    -
    -
    -
    -
    -
    0.1  
    0.1  
    0.1  
    -
    OL  
    4.5  
    6
    Low Level Output  
    Voltage  
    TTL Loads  
    -
    4
    4.5  
    6
    0.26  
    0.26  
    ±0.1  
    0.33  
    0.33  
    ±1  
    0.4  
    0.4  
    ±1  
    5.2  
    -
    Input Leakage  
    Current  
    I
    V
    or  
    6
    I
    CC  
    GND  
    Quiescent Device  
    Current  
    I
    V
    GND  
    or  
    0
    6
    -
    -
    8
    -
    80  
    -
    160  
    µA  
    CC  
    CC  
    3
    CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158  
    DC Electrical Specifications (Continued)  
    TEST  
    CONDITIONS  
    o
    o
    o
    o
    o
    25 C  
    -40 C TO 85 C -55 C TO 125 C  
    V
    CC  
    PARAMETER  
    HCT TYPES  
    SYMBOL  
    V (V)  
    I
    I
    (mA)  
    (V)  
    MIN  
    TYP  
    MAX  
    MIN  
    MAX  
    MIN  
    MAX  
    UNITS  
    O
    High Level Input  
    Voltage  
    V
    -
    -
    -
    -
    4.5 to  
    5.5  
    2
    -
    -
    -
    -
    -
    0.8  
    -
    2
    -
    -
    0.8  
    -
    2
    -
    -
    0.8  
    -
    V
    V
    V
    IH  
    Low Level Input  
    Voltage  
    V
    4.5 to  
    5.5  
    IL  
    High Level Output  
    Voltage  
    CMOS Loads  
    V
    V
    V
    or V  
    -0.02  
    4.5  
    4.5  
    4.5  
    4.5  
    4.4  
    4.4  
    4.4  
    OH  
    IH  
    IH  
    IL  
    High Level Output  
    Voltage  
    TTL Loads  
    -4  
    3.98  
    -
    -
    -
    -
    3.84  
    -
    3.7  
    -
    V
    V
    V
    Low Level Output  
    Voltage  
    CMOS Loads  
    V
    or V  
    0.02  
    4
    -
    -
    0.1  
    0.26  
    -
    -
    0.1  
    0.33  
    -
    -
    0.1  
    0.4  
    OL  
    IL  
    Low Level Output  
    Voltage  
    TTL Loads  
    Input Leakage  
    Current  
    I
    V
    and  
    0
    0
    -
    5.5  
    5.5  
    -
    -
    -
    ±0.1  
    8
    -
    -
    -
    ±1  
    80  
    -
    -
    -
    ±1  
    µA  
    µA  
    µA  
    I
    CC  
    GND  
    Quiescent Device  
    Current  
    I
    V
    or  
    -
    160  
    490  
    CC  
    CC  
    GND  
    Additional Quiescent  
    Device Current Per  
    Input Pin: 1 Unit Load  
    ∆I  
    CC  
    (Note 2)  
    V
    4.5 to  
    5.5  
    100  
    360  
    450  
    CC  
    -2.1  
    NOTE:  
    2. For dual-supply systems theoretical worst case (V = 2.4V, V  
    I
    = 5.5V) specification is 1.8mA.  
    CC  
    HCT Input Loading Table  
    UNIT LOADS  
    INPUT  
    HCT157  
    0.95  
    0.6  
    HCT158  
    0.4  
    I (All)  
    E
    0.6  
    S
    3
    2.8  
    NOTE: Unit Load is ∆I  
    360µA max at 25 C.  
    limit specified in DC Electrical Table, e.g.,  
    CC  
    o
    Switching Specifications Input t , t = 6ns  
    r
    f
    o
    o
    o
    o
    o
    25 C  
    -40 C TO 85 C -55 C TO 125 C  
    TEST  
    SYMBOL CONDITIONS  
    V
    CC  
    (V)  
    PARAMETER  
    MIN TYP MAX  
    MIN  
    MAX  
    MIN  
    MAX  
    UNITS  
    HC/HCT157 TYPES  
    Propagation Delay (Figure 1)  
    t
    t
    C = 50pF  
    2
    4.5  
    5
    -
    -
    -
    -
    -
    -
    -
    125  
    25  
    -
    -
    -
    -
    -
    -
    155  
    31  
    -
    -
    -
    -
    -
    -
    190  
    38  
    -
    ns  
    ns  
    ns  
    ns  
    ns  
    PLH, PHL  
    L
    Data to Output  
    HC157  
    C =15pF  
    10  
    12  
    -
    L
    HCT157  
    -
    -
    -
    C = 50pF  
    6
    21  
    26  
    32  
    L
    4
    CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158  
    Switching Specifications Input t , t = 6ns (Continued)  
    r
    f
    o
    o
    o
    o
    o
    25 C  
    -40 C TO 85 C -55 C TO 125 C  
    TEST  
    SYMBOL CONDITIONS  
    V
    CC  
    (V)  
    PARAMETER  
    MIN TYP MAX  
    MIN  
    MAX  
    170  
    34  
    -
    MIN  
    MAX  
    205  
    41  
    -
    UNITS  
    ns  
    Enable to Output  
    t
    t
    C = 50pF  
    2
    4.5  
    5
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    135  
    27  
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    PLH, PHL  
    L
    ns  
    HC157  
    C =15pF  
    11  
    12  
    -
    ns  
    L
    HCT157  
    -
    -
    -
    ns  
    C = 50pF  
    6
    2
    23  
    145  
    29  
    -
    29  
    180  
    36  
    -
    35  
    220  
    44  
    -
    ns  
    L
    Select to Output  
    t
    t
    C = 50pF  
    -
    ns  
    PLH, PHL  
    L
    4.5  
    5
    -
    ns  
    HC157  
    C =15pF  
    12  
    15  
    -
    ns  
    L
    HCT157  
    -
    -
    -
    ns  
    C = 50pF  
    L
    6
    5
    25  
    31  
    38  
    ns  
    Power Dissipation  
    C
    -
    PD  
    Capacitance (Notes 3, 4)  
    HC157  
    -
    -
    62  
    70  
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    pF  
    pF  
    HCT157  
    HC158  
    HC/HCT158 TYPES  
    Data to Output  
    t
    t
    t
    t
    C = 50pF  
    2
    4.5  
    5
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    140  
    28  
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    175  
    35  
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    210  
    42  
    -
    ns  
    PLH, PHL  
    L
    C =15pF  
    11  
    13  
    -
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    L
    HCT 158  
    -
    -
    -
    C = 50pF  
    6
    2
    24  
    160  
    32  
    -
    30  
    200  
    40  
    -
    36  
    240  
    48  
    -
    L
    Enable to Output  
    t
    C = 50pF  
    -
    PLH, PHL  
    L
    4.5  
    5
    -
    HC158  
    C =15pF  
    13  
    15  
    -
    L
    HCT 158  
    -
    -
    -
    C = 50pF  
    6
    2
    27  
    150  
    30  
    -
    34  
    190  
    38  
    -
    41  
    225  
    45  
    -
    L
    Select to Output  
    t
    C = 50pF  
    -
    PLH, PHL  
    L
    4.5  
    5
    -
    HC158  
    C =15pF  
    12  
    14  
    -
    L
    HCT 158  
    -
    -
    -
    C = 50pF  
    6
    2
    26  
    75  
    15  
    13  
    33  
    95  
    19  
    16  
    38  
    110  
    22  
    19  
    L
    Output Transition Time  
    t
    t
    C = 50pF  
    L
    -
    TLH, THL  
    4.5  
    6
    -
    -
    Power Dissipation  
    C
    -
    5
    PD  
    Capacitance (Notes 3, 4)  
    HC158  
    HCT 158  
    -
    -
    -
    35  
    35  
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    pF  
    pF  
    pF  
    Input Capacitance  
    NOTES:  
    C
    C = 50pF  
    -
    10  
    10  
    10  
    IN  
    L
    3. C  
    is used to determine the dynamic power consumption, per multiplexer.  
    2
    PD  
    4. P = V  
    f (C  
    PD  
    + C ) where f = input frequency, C = output load capacitance, V  
    = supply voltage.  
    CC  
    D
    CC  
    i
    L
    i
    L
    5
    CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158  
    Test Circuits and Waveforms  
    t = 6ns  
    t = 6ns  
    t = 6ns  
    t = 6ns  
    r
    f
    r
    f
    V
    3V  
    CC  
    90%  
    50%  
    10%  
    2.7V  
    1.3V  
    0.3V  
    INPUT  
    INPUT  
    GND  
    GND  
    t
    t
    t
    t
    THL  
    TLH  
    THL  
    TLH  
    90%  
    1.3V  
    90%  
    50%  
    10%  
    INVERTING  
    OUTPUT  
    INVERTING  
    OUTPUT  
    10%  
    t
    t
    PLH  
    PHL  
    t
    t
    PLH  
    PHL  
    FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-  
    TION DELAY TIMES, COMBINATION LOGIC  
    FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION  
    DELAY TIMES, COMBINATION LOGIC  
    6
    PACKAGE OPTION ADDENDUM  
    www.ti.com  
    9-Oct-2007  
    PACKAGING INFORMATION  
    Orderable Device  
    Status (1)  
    Package Package  
    Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
    Qty  
    Type  
    CDIP  
    CDIP  
    CDIP  
    CDIP  
    CDIP  
    CDIP  
    PDIP  
    Drawing  
    5962-9070201MEA  
    5962-9070301MEA  
    CD54HC157F  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    J
    J
    J
    J
    J
    J
    N
    16  
    16  
    16  
    16  
    16  
    16  
    16  
    1
    1
    TBD  
    TBD  
    TBD  
    TBD  
    TBD  
    TBD  
    A42 SNPB  
    A42 SNPB  
    A42 SNPB  
    A42 SNPB  
    A42 SNPB  
    A42 SNPB  
    N / A for Pkg Type  
    N / A for Pkg Type  
    N / A for Pkg Type  
    N / A for Pkg Type  
    N / A for Pkg Type  
    N / A for Pkg Type  
    1
    CD54HC157F3A  
    CD54HCT157F3A  
    CD54HCT158F3A  
    CD74HC157E  
    1
    1
    1
    25  
    Pb-Free  
    (RoHS)  
    CU NIPDAU N / A for Pkg Type  
    CD74HC157EE4  
    CD74HC157M  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    OBSOLETE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    PDIP  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    SSOP  
    PDIP  
    PDIP  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    N
    D
    D
    D
    D
    D
    D
    D
    D
    D
    DB  
    N
    N
    D
    D
    D
    D
    D
    D
    D
    16  
    16  
    16  
    16  
    16  
    16  
    16  
    16  
    16  
    16  
    16  
    16  
    16  
    16  
    16  
    16  
    16  
    16  
    16  
    16  
    25  
    Pb-Free  
    (RoHS)  
    CU NIPDAU N / A for Pkg Type  
    40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    CD74HC157M96  
    CD74HC157M96E4  
    CD74HC157M96G4  
    CD74HC157ME4  
    CD74HC157MG4  
    CD74HC157MT  
    2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    CD74HC157MTE4  
    CD74HC157MTG4  
    CD74HC157SM  
    250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    CD74HCT157E  
    25  
    25  
    Pb-Free  
    (RoHS)  
    CU NIPDAU N / A for Pkg Type  
    CD74HCT157EE4  
    CD74HCT157M  
    Pb-Free  
    (RoHS)  
    CU NIPDAU N / A for Pkg Type  
    40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    CD74HCT157M96  
    CD74HCT157M96E4  
    CD74HCT157M96G4  
    CD74HCT157ME4  
    CD74HCT157MG4  
    CD74HCT157MT  
    2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    Addendum-Page 1  
    PACKAGE OPTION ADDENDUM  
    www.ti.com  
    9-Oct-2007  
    Orderable Device  
    CD74HCT157MTE4  
    CD74HCT157MTG4  
    CD74HCT158E  
    Status (1)  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    Package Package  
    Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
    Qty  
    Type  
    Drawing  
    SOIC  
    D
    16  
    16  
    16  
    16  
    250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    SOIC  
    PDIP  
    PDIP  
    D
    N
    N
    250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    25  
    Pb-Free  
    (RoHS)  
    CU NIPDAU N / A for Pkg Type  
    CD74HCT158EE4  
    25  
    Pb-Free  
    (RoHS)  
    CU NIPDAU N / A for Pkg Type  
    (1) The marketing status values are defined as follows:  
    ACTIVE: Product device recommended for new designs.  
    LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
    NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
    a new design.  
    PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
    OBSOLETE: TI has discontinued the production of the device.  
    (2)  
    Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
    http://www.ti.com/productcontent for the latest availability information and additional product content details.  
    TBD: The Pb-Free/Green conversion plan has not been defined.  
    Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
    for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
    at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
    Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
    package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
    compatible) as defined above.  
    Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
    retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
    (3)  
    MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
    temperature.  
    Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
    provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
    accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
    reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
    incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
    information may not be available for release.  
    In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
    to Customer on an annual basis.  
    Addendum-Page 2  
    PACKAGE MATERIALS INFORMATION  
    www.ti.com  
    19-Mar-2008  
    TAPE AND REEL INFORMATION  
    *All dimensions are nominal  
    Device  
    Package Package Pins  
    Type Drawing  
    SPQ  
    Reel  
    Reel  
    A0 (mm)  
    B0 (mm)  
    K0 (mm)  
    P1  
    W
    Pin1  
    Diameter Width  
    (mm) W1 (mm)  
    (mm) (mm) Quadrant  
    CD74HC157M96  
    CD74HCT157M96  
    SOIC  
    SOIC  
    D
    D
    16  
    16  
    2500  
    2500  
    330.0  
    330.0  
    16.4  
    16.4  
    6.5  
    6.5  
    10.3  
    10.3  
    2.1  
    2.1  
    8.0  
    8.0  
    16.0  
    16.0  
    Q1  
    Q1  
    Pack Materials-Page 1  
    PACKAGE MATERIALS INFORMATION  
    www.ti.com  
    19-Mar-2008  
    *All dimensions are nominal  
    Device  
    Package Type Package Drawing Pins  
    SPQ  
    Length (mm) Width (mm) Height (mm)  
    CD74HC157M96  
    CD74HCT157M96  
    SOIC  
    SOIC  
    D
    D
    16  
    16  
    2500  
    2500  
    333.2  
    333.2  
    345.9  
    345.9  
    28.6  
    28.6  
    Pack Materials-Page 2  
    MECHANICAL DATA  
    MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001  
    DB (R-PDSO-G**)  
    PLASTIC SMALL-OUTLINE  
    28 PINS SHOWN  
    0,38  
    0,22  
    0,65  
    28  
    M
    0,15  
    15  
    0,25  
    0,09  
    5,60  
    5,00  
    8,20  
    7,40  
    Gage Plane  
    1
    14  
    0,25  
    A
    0°–ā8°  
    0,95  
    0,55  
    Seating Plane  
    0,10  
    2,00 MAX  
    0,05 MIN  
    PINS **  
    14  
    16  
    20  
    24  
    28  
    30  
    38  
    DIM  
    6,50  
    5,90  
    6,50  
    5,90  
    7,50  
    8,50  
    7,90  
    10,50  
    9,90  
    10,50 12,90  
    A MAX  
    A MIN  
    6,90  
    9,90  
    12,30  
    4040065 /E 12/01  
    NOTES: A. All linear dimensions are in millimeters.  
    B. This drawing is subject to change without notice.  
    C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
    D. Falls within JEDEC MO-150  
    POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
    IMPORTANT NOTICE  
    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,  
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    TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard  
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    TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
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    TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,  
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