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    • 北京元坤伟业科技有限公司

           该会员已使用本站17年以上

    • CD74HCT154ME4
    • 数量-
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    • QQ:857273081QQ：857273081 复制
      QQ:1594462451QQ：1594462451 复制
    • 010-62104931、62106431、62104891、62104791 QQ:857273081QQ:1594462451
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    • CD74HCT154ME4图

    • 上海振基实业有限公司

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    • CD74HCT154ME4
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    • QQ:330263063QQ：330263063 复制
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    产品型号CD74HCT154ME4的Datasheet PDF文件预览

    CD54HC154, CD74HC154,  
    CD54HCT154, CD74HCT154  
    Data sheet acquired from Harris Semiconductor  
    SCHS152D  
    High-Speed CMOS Logic  
    4- to 16-Line Decoder/Demultiplexer  
    September 1997 - Revised June 2004  
    A High on either enable input forces the output into the High  
    state. The demultiplexing function is performed by using the  
    four input lines, A0 to A3, to select the output lines Y0 to  
    Y15, and using one enable as the data input while holding  
    the other enable low.  
    Features  
    • Two Enable Inputs to Facilitate Demultiplexing and  
    Cascading Functions  
    [ /Title  
    (CD74  
    HC154  
    ,
    CD74  
    HCT15  
    4)  
    • Fanout (Over Temperature Range)  
    - Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
    - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
    Ordering Information  
    o
    o
    • Wide Operating Temperature Range . . . -55 C to 125 C  
    • Balanced Propagation Delay and Transition Times  
    TEMP. RANGE  
    o
    PART NUMBER  
    CD54HC154F3A  
    CD54HCT154F3A  
    CD74HC154E  
    ( C)  
    PACKAGE  
    24 Ld CERDIP  
    24 Ld CERDIP  
    24 Ld PDIP  
    24 Ld PDIP  
    24 Ld SOIC  
    24 Ld SOIC  
    24 Ld PDIP  
    24 Ld PDIP  
    24 Ld SOIC  
    24 Ld SOIC  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    -55 to 125  
    • Significant Power Reduction Compared to LSTTL  
    Logic ICs  
    /Sub-  
    ject  
    • HC Types  
    - 2V to 6V Operation  
    (High  
    Speed  
    CMOS  
    Logic  
    4-to-16  
    Line  
    CD74HC154EN  
    CD74HC154M  
    - High Noise Immunity: N = 30%, N = 30%of V  
    IL IH  
    at  
    CC  
    V
    = 5V  
    CC  
    • HCT Types  
    CD74HC154M96  
    CD74HCT154E  
    CD74HCT154EN  
    CD74HCT154M  
    CD74HCT154M96  
    - 4.5V to 5.5V Operation  
    - Direct LSTTL Input Logic Compatibility,  
    V = 0.8V (Max), V = 2V (Min)  
    IL IH  
    Decod  
    er/Dem  
    - CMOS Input Compatibility, I ≤ 1µA at V , V  
    OL OH  
    l
    Description  
    The ’HC154 and ’HCT154 are 4- to 16-line  
    decoders/demultiplexers with two enable inputs, E1 and E2.  
    NOTE: When ordering, use the entire part number. The suffix 96  
    denotes tape and reel.  
    Pinout  
    CD54HC154, CD54HCT154  
    (CERDIP)  
    CD74HC154, CD74HCT154  
    (PDIP, SOIC)  
    TOP VIEW  
    Y0  
    Y1  
    Y2  
    Y3  
    Y4  
    Y5  
    Y6  
    Y7  
    Y8  
    1
    2
    3
    4
    5
    6
    7
    8
    9
    24  
    V
    CC  
    23 A0  
    22 A1  
    21 A2  
    20 A3  
    19 E2  
    18 E1  
    17 Y15  
    16 Y14  
    15 Y13  
    14 Y12  
    13 Y11  
    Y9 10  
    Y10 11  
    GND 12  
    CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
    Copyright © 2004, Texas Instruments Incorporated  
    1
    CD54HC154, CD74HC154, CD54HCT154, CD74HCT154  
    Functional Diagram  
    1
    Y0  
    2
    Y1  
    3
    Y2  
    4
    Y3  
    5
    Y4  
    6
    Y5  
    7
    Y6  
    23  
    22  
    21  
    20  
    8
    A0  
    A1  
    A2  
    A3  
    Y7  
    9
    Y8  
    10  
    11  
    13  
    14  
    15  
    16  
    17  
    Y9  
    Y10  
    Y11  
    Y12  
    Y13  
    Y14  
    Y15  
    18  
    19  
    E1  
    E2  
    GND = 12  
    = 24  
    V
    CC  
    TRUTH TABLE  
    INPUTS  
    OUTPUTS  
    E1  
    L
    L
    L
    L
    L
    L
    L
    L
    L
    L
    L
    L
    L
    L
    L
    L
    L
    H
    H
    E2  
    L
    L
    L
    L
    L
    L
    L
    L
    L
    L
    L
    L
    L
    L
    L
    L
    H
    L
    H
    A3  
    L
    A2  
    L
    A1  
    L
    A0  
    L
    Y0  
    L
    Y1  
    Y2  
    H
    H
    L
    Y3  
    H
    H
    H
    L
    Y4  
    H
    H
    H
    H
    L
    Y5  
    H
    H
    H
    H
    H
    L
    Y6  
    H
    H
    H
    H
    H
    H
    L
    Y7  
    H
    H
    H
    H
    H
    H
    H
    L
    Y8  
    H
    H
    H
    H
    H
    H
    H
    H
    L
    Y9 Y10 Y11 Y12 Y13 Y14 Y15  
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    L
    L
    L
    L
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    L
    L
    H
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    L
    L
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    L
    H
    H
    H
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    L
    L
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    L
    H
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    L
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    X
    X
    X
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    L
    L
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    L
    H
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    L
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    H
    X
    X
    X
    H
    H
    H
    H
    H
    H
    H
    L
    H
    L
    H
    H
    H
    H
    H
    H
    H
    H
    X
    X
    X
    H
    H
    H
    H
    H
    H
    X
    X
    X
    H
    H
    H
    H
    H
    H
    H
    H = High Voltage Level, L = Low Voltage Level, X = Don’t Care  
    2
    CD54HC154, CD74HC154, CD54HCT154, CD74HCT154  
    Absolute Maximum Ratings  
    Thermal Information  
    o
    DC Supply Voltage, V  
    . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
    Thermal Resistance (Typical)  
    θ
    ( C/W)  
    CC  
    DC Input Diode Current, I  
    For V < -0.5V or V > V  
    JA  
    IK  
    E (PDIP) Package (.600) (Note 1) . . . . . . . . . . . . . .  
    EN (PDIP) Package (.300) (Note 1). . . . . . . . . . . . .  
    M (SOIC) Package (Note 2). . . . . . . . . . . . . . . . . . .  
    67  
    67  
    46  
    + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
    OK  
    For V < -0.5V or V > V  
    I
    I
    CC  
    DC Output Diode Current, I  
    o
    + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
    O
    O
    CC  
    Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C  
    Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
    Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
    o
    o
    DC Output Source or Sink Current per Output Pin, I  
    O
    o
    For V > -0.5V or V < V  
    + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
    O
    O
    CC  
    DC V  
    or Ground Current, I  
    I
    . . . . . . . . . . . . . . . . . .±50mA  
    CC  
    CC or GND  
    (SOIC - Lead Tips Only)  
    Operating Conditions  
    o
    o
    Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
    A
    Supply Voltage Range, V  
    CC  
    HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
    HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
    DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
    I
    O
    CC  
    Input Rise and Fall Time  
    2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
    4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
    6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
    CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
    of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
    NOTES:  
    1. The package thermal impedance is calculated in accordance with JESD 51-3.  
    2. The package thermal impedance is calculated in accordance with JESD 51-7.  
    DC Electrical Specifications  
    TEST  
    CONDITIONS  
    o
    o
    o
    o
    o
    25 C  
    -40 C TO 85 C -55 C TO 125 C  
    V
    CC  
    PARAMETER  
    HC TYPES  
    SYMBOL  
    V (V)  
    I
    I
    (mA)  
    (V)  
    MIN  
    TYP  
    MAX  
    MIN  
    MAX  
    MIN  
    MAX  
    UNITS  
    O
    High Level Input  
    Voltage  
    V
    -
    -
    -
    2
    4.5  
    6
    1.5  
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    1.5  
    -
    1.5  
    -
    -
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    V
    µA  
    IH  
    3.15  
    -
    -
    3.15  
    -
    -
    3.15  
    4.2  
    4.2  
    4.2  
    -
    Low Level Input  
    Voltage  
    V
    -
    2
    -
    0.5  
    1.35  
    1.8  
    -
    -
    0.5  
    1.35  
    1.8  
    -
    -
    0.5  
    1.35  
    1.8  
    -
    IL  
    4.5  
    6
    -
    -
    -
    -
    -
    -
    High Level Output  
    Voltage  
    CMOS Loads  
    V
    V
    or V  
    IH IL  
    -0.02  
    2
    1.9  
    1.9  
    1.9  
    OH  
    -0.02  
    -0.02  
    -
    4.5  
    6
    4.4  
    -
    4.4  
    -
    4.4  
    -
    5.9  
    -
    5.9  
    -
    5.9  
    -
    High Level Output  
    Voltage  
    TTL Loads  
    -
    -
    -
    -
    -
    -
    -
    -4  
    4.5  
    6
    3.98  
    -
    3.84  
    -
    3.7  
    -
    -5.2  
    0.02  
    0.02  
    0.02  
    -
    5.48  
    -
    5.34  
    -
    5.2  
    -
    Low Level Output  
    Voltage  
    CMOS Loads  
    V
    V
    or V  
    IH IL  
    2
    -
    -
    -
    -
    -
    -
    -
    0.1  
    0.1  
    0.1  
    -
    -
    -
    -
    -
    -
    -
    -
    0.1  
    0.1  
    0.1  
    -
    -
    -
    -
    -
    -
    -
    -
    0.1  
    0.1  
    0.1  
    -
    OL  
    4.5  
    6
    Low Level Output  
    Voltage  
    TTL Loads  
    -
    4
    4.5  
    6
    0.26  
    0.26  
    ±0.1  
    0.33  
    0.33  
    ±1  
    0.4  
    0.4  
    ±1  
    5.2  
    -
    Input Leakage  
    Current  
    I
    V
    or  
    6
    I
    CC  
    GND  
    Quiescent Device  
    Current  
    I
    V
    GND  
    or  
    0
    6
    -
    -
    8
    -
    80  
    -
    160  
    µA  
    CC  
    CC  
    3
    CD54HC154, CD74HC154, CD54HCT154, CD74HCT154  
    DC Electrical Specifications (Continued)  
    TEST  
    CONDITIONS  
    o
    o
    o
    o
    o
    25 C  
    -40 C TO 85 C -55 C TO 125 C  
    V
    CC  
    PARAMETER  
    HCT TYPES  
    SYMBOL  
    V (V)  
    I
    I
    (mA)  
    (V)  
    MIN  
    TYP  
    MAX  
    MIN  
    MAX  
    MIN  
    MAX  
    UNITS  
    O
    High Level Input  
    Voltage  
    V
    -
    -
    -
    -
    4.5 to  
    5.5  
    2
    -
    -
    -
    -
    -
    0.8  
    -
    2
    -
    -
    0.8  
    -
    2
    -
    -
    0.8  
    -
    V
    V
    V
    IH  
    Low Level Input  
    Voltage  
    V
    4.5 to  
    5.5  
    IL  
    High Level Output  
    Voltage  
    CMOS Loads  
    V
    V
    V
    or V  
    -0.02  
    4.5  
    4.5  
    4.5  
    4.5  
    4.4  
    4.4  
    4.4  
    OH  
    IH  
    IH  
    IL  
    High Level Output  
    Voltage  
    TTL Loads  
    -4  
    3.98  
    -
    -
    -
    -
    3.84  
    -
    3.7  
    -
    V
    V
    V
    Low Level Output  
    Voltage  
    CMOS Loads  
    V
    or V  
    0.02  
    4
    -
    -
    0.1  
    0.26  
    -
    -
    0.1  
    0.33  
    -
    -
    0.1  
    0.4  
    OL  
    IL  
    Low Level Output  
    Voltage  
    TTL Loads  
    Input Leakage  
    Current  
    I
    V
    and  
    0
    0
    -
    5.5  
    5.5  
    -
    -
    -
    ±0.1  
    8
    -
    -
    -
    ±1  
    80  
    -
    -
    -
    ±1  
    µA  
    µA  
    µA  
    I
    CC  
    GND  
    Quiescent Device  
    Current  
    I
    V
    or  
    -
    160  
    490  
    CC  
    CC  
    GND  
    Additional Quiescent  
    Device Current Per  
    Input Pin: 1 Unit Load  
    ∆I  
    CC  
    (Note 3)  
    V
    4.5 to  
    5.5  
    100  
    360  
    450  
    CC  
    -2.1  
    NOTE:  
    3. For dual-supply systems theoretical worst case (V = 2.4V, V  
    I
    = 5.5V) specification is 1.8mA.  
    CC  
    HCT Input Loading Table  
    INPUT  
    A0 - A3  
    UNIT LOADS  
    1.4  
    1.3  
    E1, E2  
    NOTE: Unit Load is ∆I  
    360µA max at 25 C.  
    limit specified in DC Electrical Table, e.g.,  
    CC  
    o
    Switching Specifications Input t , t = 6ns  
    r
    f
    o
    -40 C TO  
    85 C  
    o
    o
    o
    o
    25 C  
    -55 C TO 125 C  
    TEST  
    SYMBOL CONDITIONS  
    PARAMETER  
    HC TYPES  
    V
    (V) MIN  
    TYP MAX  
    MIN  
    MAX  
    MIN  
    MAX UNITS  
    CC  
    Propagation Delay (Figure 1)  
    Address to Output  
    t
    t
    C = 50pF  
    2
    -
    -
    -
    175  
    35  
    -
    -
    -
    -
    -
    220  
    44  
    -
    -
    -
    -
    -
    265  
    53  
    -
    ns  
    ns  
    ns  
    ns  
    PLH, PHL  
    L
    4.5  
    5
    -
    -
    -
    C =15pF  
    14  
    -
    L
    C = 50pF  
    6
    30  
    37  
    45  
    L
    4
    CD54HC154, CD74HC154, CD54HCT154, CD74HCT154  
    Switching Specifications Input t , t = 6ns (Continued)  
    r
    f
    o
    -40 C TO  
    85 C  
    o
    o
    o
    o
    25 C  
    -55 C TO 125 C  
    TEST  
    PARAMETER  
    E1 to Output  
    SYMBOL CONDITIONS  
    V
    (V) MIN  
    TYP MAX  
    MIN  
    MAX  
    MIN  
    MAX UNITS  
    CC  
    t
    t
    C = 50pF  
    2
    -
    -
    -
    175  
    35  
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    220  
    44  
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    265  
    53  
    -
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    pF  
    pF  
    PLH, PHL  
    L
    4.5  
    5
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    C =15pF  
    14  
    -
    L
    C = 50pF  
    6
    30  
    175  
    35  
    -
    37  
    220  
    44  
    -
    45  
    265  
    53  
    -
    L
    E2 to Output  
    t
    t
    C = 50pF  
    2
    -
    PLH, PHL  
    L
    4.5  
    5
    -
    C =15pF  
    14  
    -
    L
    C = 50pF  
    6
    30  
    75  
    15  
    13  
    10  
    -
    37  
    95  
    19  
    16  
    10  
    -
    45  
    110  
    22  
    19  
    10  
    -
    L
    Output Transition Time  
    (Figure 1)  
    t
    , t  
    TLH THL  
    C = 50pF  
    L
    2
    -
    4.5  
    6
    -
    -
    Input Capacitance  
    C
    -
    -
    -
    -
    IN  
    Power Dissipation Capacitance  
    (Notes 4, 5)  
    C
    5
    88  
    PD  
    HCT TYPES  
    Propagation Delay (Figure 2)  
    Address to Output  
    t
    , t  
    PLH PHL  
    C = 50pF  
    4.5  
    5
    -
    -
    -
    -
    -
    -
    -
    -
    -
    35  
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    44  
    -
    -
    -
    -
    -
    -
    -
    -
    -
    53  
    -
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    pF  
    pF  
    L
    C =15pF  
    14  
    -
    L
    E1 to Output  
    E2 to Output  
    t
    , t  
    PLH PHL  
    C = 50pF  
    4.5  
    5
    34  
    -
    43  
    -
    51  
    -
    L
    C =15pF  
    14  
    L
    t
    , t  
    PLH PHL  
    C = 50pF  
    4.5  
    5
    34  
    -
    43  
    -
    51  
    -
    L
    C =15pF  
    14  
    -
    L
    Output Transition Time  
    Input Capacitance  
    t
    , t  
    TLH THL  
    C = 50pF  
    L
    4.5  
    -
    15  
    10  
    -
    19  
    10  
    -
    22  
    10  
    -
    C
    -
    -
    -
    IN  
    Power Dissipation Capacitance  
    (Notes 4, 5)  
    C
    5
    84  
    PD  
    NOTES:  
    4. C  
    is used to determine the dynamic power consumption, per gate.  
    2
    PD  
    5. P = V  
    f (C  
    PD  
    + C ) where f = input frequency, C = output load capacitance, V  
    = supply voltage.  
    CC  
    D
    CC  
    i
    L
    i
    L
    5
    Test Circuits and Waveforms  
    t = 6ns  
    t = 6ns  
    t = 6ns  
    t = 6ns  
    r
    f
    r
    f
    V
    3V  
    CC  
    90%  
    50%  
    10%  
    2.7V  
    1.3V  
    0.3V  
    INPUT  
    INPUT  
    GND  
    GND  
    t
    t
    t
    t
    THL  
    TLH  
    THL  
    TLH  
    90%  
    1.3V  
    90%  
    50%  
    10%  
    INVERTING  
    OUTPUT  
    INVERTING  
    OUTPUT  
    10%  
    t
    t
    PLH  
    PHL  
    t
    t
    PLH  
    PHL  
    FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-  
    TION DELAY TIMES, COMBINATION LOGIC  
    FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION  
    DELAY TIMES, COMBINATION LOGIC  
    6
    PACKAGE OPTION ADDENDUM  
    www.ti.com  
    17-Oct-2005  
    PACKAGING INFORMATION  
    Orderable Device  
    Status (1)  
    Package Package  
    Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
    Qty  
    Type  
    CDIP  
    CDIP  
    CDIP  
    CDIP  
    PDIP  
    Drawing  
    5962-8670101JA  
    5962-8682201JA  
    CD54HC154F3A  
    CD54HCT154F3A  
    CD74HC154E  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    J
    J
    24  
    24  
    24  
    24  
    24  
    1
    1
    TBD  
    TBD  
    TBD  
    TBD  
    Call TI  
    Call TI  
    Call TI  
    Call TI  
    Level-NC-NC-NC  
    Level-NC-NC-NC  
    Level-NC-NC-NC  
    Level-NC-NC-NC  
    J
    1
    J
    1
    N
    15  
    Pb-Free  
    (RoHS)  
    CU NIPDAU Level-NC-NC-NC  
    CU NIPDAU Level-NC-NC-NC  
    CU NIPDAU Level-NC-NC-NC  
    CU NIPDAU Level-NC-NC-NC  
    CD74HC154EE4  
    CD74HC154EN  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    ACTIVE  
    PDIP  
    PDIP  
    PDIP  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    PDIP  
    PDIP  
    PDIP  
    PDIP  
    SOIC  
    SOIC  
    SOIC  
    SOIC  
    N
    24  
    24  
    24  
    24  
    24  
    24  
    24  
    24  
    24  
    24  
    24  
    24  
    24  
    24  
    24  
    15  
    15  
    15  
    Pb-Free  
    (RoHS)  
    NT  
    NT  
    DW  
    DW  
    DW  
    DW  
    N
    Pb-Free  
    (RoHS)  
    CD74HC154ENE4  
    CD74HC154M  
    Pb-Free  
    (RoHS)  
    25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    CD74HC154M96  
    CD74HC154M96E4  
    CD74HC154ME4  
    CD74HCT154E  
    2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    15  
    15  
    15  
    15  
    Pb-Free  
    (RoHS)  
    CU NIPDAU Level-NC-NC-NC  
    CU NIPDAU Level-NC-NC-NC  
    CU NIPDAU Level-NC-NC-NC  
    CU NIPDAU Level-NC-NC-NC  
    CD74HCT154EE4  
    CD74HCT154EN  
    CD74HCT154ENE4  
    CD74HCT154M  
    N
    Pb-Free  
    (RoHS)  
    NT  
    NT  
    DW  
    DW  
    DW  
    DW  
    Pb-Free  
    (RoHS)  
    Pb-Free  
    (RoHS)  
    25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    CD74HCT154M96  
    CD74HCT154M96E4  
    CD74HCT154ME4  
    2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
    no Sb/Br)  
    (1) The marketing status values are defined as follows:  
    ACTIVE: Product device recommended for new designs.  
    LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
    NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
    a new design.  
    PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
    OBSOLETE: TI has discontinued the production of the device.  
    (2)  
    Eco Plan  
    -
    The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
    &
    no Sb/Br)  
    -
    please check  
    http://www.ti.com/productcontent for the latest availability information and additional product content details.  
    TBD: The Pb-Free/Green conversion plan has not been defined.  
    Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
    for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
    at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
    Addendum-Page 1  
    PACKAGE OPTION ADDENDUM  
    www.ti.com  
    17-Oct-2005  
    Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
    retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
    (3)  
    MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
    temperature.  
    Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
    provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
    accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
    reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
    incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
    information may not be available for release.  
    In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
    to Customer on an annual basis.  
    Addendum-Page 2  
    MECHANICAL DATA  
    MCDI004A – JANUARY 1995 – REVISED NOVEMBER 1997  
    J (R-GDIP-T**)  
    CERAMIC DUAL-IN-LINE PACKAGE  
    24 PINS SHOWN  
    B
    13  
    24  
    C
    12  
    1
    0.065 (1,65)  
    0.045 (1,14)  
    Lens Protrusion (Lens Optional)  
    0.010 (0.25) MAX  
    0.090 (2,29)  
    0.060 (1,53)  
    0.175 (4,45)  
    0.140 (3,56)  
    A
    Seating Plane  
    0.018 (0,46) MIN  
    0.125 (3,18) MIN  
    0.022 (0,56)  
    0.014 (0,36)  
    0.100 (2,54)  
    0.012 (0,30)  
    0.008 (0,20)  
    24  
    28  
    32  
    40  
    PINS **  
    DIM  
    ”A”  
    NARR  
    WIDE  
    NARR  
    WIDE  
    NARR  
    WIDE  
    NARR  
    WIDE  
    0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)  
    0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)  
    1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)  
    1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)  
    0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)  
    0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)  
    MAX  
    MIN  
    MAX  
    MIN  
    ”B”  
    ”C”  
    MAX  
    MIN  
    4040084/C 10/97  
    NOTES: A. All linear dimensions are in inches (millimeters).  
    B. This drawing is subject to change without notice.  
    C. Window (lens) added to this group of packages (24-, 28-, 32-, 40-pin).  
    D. This package can be hermetically sealed with a ceramic lid using glass frit.  
    E. Index point is provided on cap for terminal identification.  
    POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
    MECHANICAL DATA  
    MPDI004 – OCTOBER 1994  
    NT (R-PDIP-T**)  
    PLASTIC DUAL-IN-LINE PACKAGE  
    24 PINS SHOWN  
    A
    PINS **  
    24  
    28  
    DIM  
    24  
    13  
    1.260  
    (32,04) (36,20)  
    1.425  
    A MAX  
    1.230  
    (31,24) (35,18)  
    1.385  
    A MIN  
    B MAX  
    B MIN  
    0.280 (7,11)  
    0.250 (6,35)  
    0.310  
    (7,87)  
    0.315  
    (8,00)  
    1
    12  
    0.290  
    (7,37)  
    0.295  
    (7,49)  
    0.070 (1,78) MAX  
    B
    0.020 (0,51) MIN  
    0.200 (5,08) MAX  
    Seating Plane  
    0.125 (3,18) MIN  
    0.100 (2,54)  
    0.010 (0,25)  
    0°–15°  
    0.021 (0,53)  
    0.015 (0,38)  
    M
    0.010 (0,25) NOM  
    4040050/B 04/95  
    NOTES: A. All linear dimensions are in inches (millimeters).  
    B. This drawing is subject to change without notice.  
    POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
    MECHANICAL DATA  
    MPDI006B – SEPTEMBER 2001 – REVISED APRIL 2002  
    N (R–PDIP–T24)  
    PLASTIC DUAL–IN–LINE  
    1.222 (31,04) MAX  
    24  
    13  
    0.360 (9,14) MAX  
    1
    12  
    0.070 (1,78) MAX  
    0.200 (5,08) MAX  
    0.020 (0,51) MIN  
    0.425 (10,80) MAX  
    Seating Plane  
    0.125 (3,18) MIN  
    0.100 (2,54)  
    0.010 (0,25)  
    0’–15’  
    0.021 (0,53)  
    0.015 (0,38)  
    0.010 (0,25) NOM  
    4040051–3/D 09/01  
    NOTES: A. All linear dimensions are in inches (millimeters).  
    B. This drawing is subject to change without notice.  
    C. Falls within JEDEC MS–010  
    POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
    MECHANICAL DATA  
    MPDI008 – OCTOBER 1994  
    N (R-PDIP-T**)  
    PLASTIC DUAL-IN-LINE PACKAGE  
    24 PIN SHOWN  
    A
    24  
    13  
    0.560 (14,22)  
    0.520 (13,21)  
    1
    12  
    0.060 (1,52) TYP  
    0.200 (5,08) MAX  
    0.020 (0,51) MIN  
    0.610 (15,49)  
    0.590 (14,99)  
    Seating Plane  
    0.100 (2,54)  
    0.125 (3,18) MIN  
    0.010 (0,25) NOM  
    0°–15°  
    0.021 (0,53)  
    0.015 (0,38)  
    0.010 (0,25)  
    PINS **  
    M
    24  
    28  
    32  
    40  
    48  
    52  
    DIM  
    1.270  
    1.450  
    1.650  
    2.090  
    2.450  
    2.650  
    A MAX  
    (32,26) (36,83) (41,91) (53,09) (62,23) (67,31)  
    1.230  
    1.410  
    1.610  
    2.040  
    2.390  
    2.590  
    A MIN  
    (31,24) (35,81) (40,89) (51,82) (60,71) (65,79)  
    4040053/B 04/95  
    NOTES: A. All linear dimensions are in inches (millimeters).  
    B. This drawing is subject to change without notice.  
    C. Falls within JEDEC MS-011  
    D. Falls within JEDEC MS-015 (32 pin only)  
    POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
    IMPORTANT NOTICE  
    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
    enhancements, improvements, and other changes to its products and services at any time and to discontinue  
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    TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
    accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
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    TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
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    Amplifiers  
    amplifier.ti.com  
    www.ti.com/audio  
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    dataconverter.ti.com  
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    www.ti.com/automotive  
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    dsp.ti.com  
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    www.ti.com/broadband  
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    interface.ti.com  
    logic.ti.com  
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    power.ti.com  
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    www.ti.com/opticalnetwork  
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    www.ti.com/wireless  
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    Texas Instruments  
    Post Office Box 655303 Dallas, Texas 75265  
    Copyright 2005, Texas Instruments Incorporated  
    配单直通车
    CD74HCT154ME4产品参数
    型号:CD74HCT154ME4
    是否无铅：不含铅
    是否Rohs认证：符合
    生命周期：Obsolete
    IHS 制造商：TEXAS INSTRUMENTS INC
    零件包装代码：SOIC
    包装说明：GREEN, PLASTIC, SOIC-24
    针数：24
    Reach Compliance Code：unknown
    ECCN代码：EAR99
    HTS代码：8542.39.00.01
    风险等级：5.16
    Is Samacsys：N
    其他特性：2 ENABLE INPUTS
    系列：HCT
    输入调节：STANDARD
    JESD-30 代码：R-PDSO-G24
    JESD-609代码：e4
    长度：15.4 mm
    负载电容（CL）：50 pF
    逻辑集成电路类型：OTHER DECODER/DRIVER
    最大I（ol）：0.004 A
    湿度敏感等级：1
    功能数量：1
    端子数量：24
    最高工作温度：125 °C
    最低工作温度：-55 °C
    输出极性：INVERTED
    封装主体材料：PLASTIC/EPOXY
    封装代码：SOP
    封装等效代码：SOP24,.4
    封装形状：RECTANGULAR
    封装形式：SMALL OUTLINE
    包装方法：TUBE
    峰值回流温度（摄氏度）：260
    电源：5 V
    Prop。Delay @ Nom-Sup：53 ns
    传播延迟（tpd）：53 ns
    认证状态：Not Qualified
    座面最大高度：2.65 mm
    子类别：Decoder/Drivers
    最大供电电压 (Vsup)：5.5 V
    最小供电电压 (Vsup)：4.5 V
    标称供电电压 (Vsup)：5 V
    表面贴装：YES
    技术：CMOS
    温度等级：MILITARY
    端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
    端子形式：GULL WING
    端子节距：1.27 mm
    端子位置：DUAL
    处于峰值回流温度下的最长时间：NOT SPECIFIED
    宽度：7.5 mm
    Base Number Matches：1
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