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产品型号CS7250B的Datasheet PDF文件预览

CS7250B  
Digital MEMS Microphone with  
High Performance and Low Power Modes  
Features  
Description  
• High acoustic overload point (AOP, 131 dB SPL)  
• High signal-to-noise ratio (SNR, 66 dB)  
• Low variation in sensitivity (±1 dB)  
• Low current consumption  
The CS7250B is a high-performance digital MEMS  
microphone, offering class-leading total harmonic distortion  
(THD) performance, excellent SNR, and low power  
consumption.  
The CS7250B supports two operational modes, selected  
according to the applied clock frequency. Low Power Mode  
is ideal for always-on voice activity detection; High  
— 650 A (High Performance Mode)  
— 160 A (Low Power Mode)  
— 5 A (Standby Mode)  
Performance Mode is optimized for high fidelity recording.  
The CS7250B incorporates a high-performance ADC,  
which outputs a single-bit data stream using pulse density  
modulation (PDM) encoding. The CS7250B supports  
selectable left/right channel assignment for a two-channel  
digital microphone interface, enabling efficient connection  
of multiple microphones in stereo/array configurations.  
• PDM digital audio output  
• Bottom-port LGA package  
• 1.8-V supply  
The CS7250B is available in a 3.50 x 2.65 x 0.98-mm  
bottom-port LGA package, with port diameter of 0.325 mm.  
It is ideal for portable applications such as smartphones,  
tablets, wearables and portable speech-recognition  
devices.  
VDD  
GND  
MEMS  
Transducer  
CMOS ASIC  
CLK  
Biasing  
DATA  
PDM  
High  
Performance  
Amp  
Digital  
Signal  
Processing  
Ultralow  
Power ADC  
LRSEL  
This document contains information for a new product.  
Cirrus Logic reserves the right to modify this product without notice.  
Preliminary Product Information  
DS1072PP1  
MAY '17  
Copyright Cirrus Logic, Inc. 2015–2017  
(All Rights Reserved)  
http://www.cirrus.com  
CS7250B  
Table of Contents  
1 Pin Descriptions ........................................................................................................................................................... 3  
1.1 LGA Pinout ............................................................................................................................................................ 3  
1.2 Pin Descriptions ..................................................................................................................................................... 3  
2 Typical Connection Diagram ....................................................................................................................................... 4  
3 Characteristics and Specifications ............................................................................................................................. 5  
Table 3-1. Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Table 3-2. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Table 3-3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Table 3-4. Acoustic and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Table 3-5. Audio Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
4 Typical Performance .................................................................................................................................................... 8  
4.1 Audio Frequency Response .................................................................................................................................. 8  
4.2 THD Performance .................................................................................................................................................. 8  
5 Applications Information ............................................................................................................................................. 9  
5.1 Important Assembly Guidelines ............................................................................................................................. 9  
5.2 PCB Land Pattern and Paste Stencil ..................................................................................................................... 9  
6 Package Dimension .................................................................................................................................................... 10  
7 Ordering Information .................................................................................................................................................. 10  
8 References .................................................................................................................................................................. 11  
9 Revision History ......................................................................................................................................................... 11  
2
DS1072PP1  
CS7250B  
1 Pin Descriptions  
1 Pin Descriptions  
1.1 LGA Pinout  
3
4
5
2
1
Figure 1-1. Top-Down (Through-Package) View  
1.2 Pin Descriptions  
A description of each pin on the CS7250B is provided in Table 1-1.  
Table 1-1. Pin Descriptions  
Name  
DATA  
Pin #  
I/O  
O
I
Description  
1
2
PDM data output  
Channel select  
LRSEL  
0 = Data output following falling CLK edge  
1 = Data output following rising CLK edge  
This pin must be tied to VDD or GND—there is no internal pull-up/-down provided.  
GND  
CLK  
VDD  
3
4
5
Ground  
I
Clock input  
Power supply  
3
DS1072PP1  
CS7250B  
2 Typical Connection Diagram  
2 Typical Connection Diagram  
0.1µF  
0.1µF  
1.8V  
1.8V  
AVDVD  
D
D
GND  
VDD  
GND  
CS7250B  
CS7250B  
AP/CODEC  
CLK  
DATA  
LRSEL CLK DATA  
LRSEL CLK DATA  
Figure 2-1. Typical Connection Diagram  
Stereo connection of two CS7250B digital microphones is shown in Fig. 2-1.  
It is recommended to connect a 0.1-F decoupling capacitor between the VDD and GND pins of the CS7250B. A ceramic  
0.1-F capacitor with X7R dielectric or better is suitable. The capacitor should be placed as close to the CS7250B as  
possible.  
4
DS1072PP1  
CS7250B  
3 Characteristics and Specifications  
3 Characteristics and Specifications  
Table 3-1. Parameter Definitions  
Parameter  
Definition  
Sensitivity  
A measure of the microphone output response to the acoustic pressure of a 1-kHz, 94 dB SPL (1 Pa RMS)  
sine wave. This is referenced to the output Full Scale Range (FSR) of the microphone.  
Full Scale Range (FSR)  
Sensitivity, electrical noise floor and power supply rejection are measured with reference to the output full  
scale range (FSR) of the microphone. FSR is defined as the amplitude of a 1-kHz sine-wave output whose  
positive peak value reaches 100% density of logic 1s and whose negative peak value reaches 0% density  
of logic 1s. This is the largest 1-kHz sine wave that fits in the digital output range without clipping. Note that,  
because the definition of FSR is based on a sine wave, it is possible to support a square wave test signal  
output whose level is +3 dBFS.  
Total harmonic distortion (THD) The ratio of the RMS sum of the harmonic distortion products in the specified bandwidth (see note) relative  
to the RMS amplitude of the fundamental (i.e., test frequency) output.  
Signal-to-noise ratio (SNR)  
A measure of the difference in level between the output response of a 1-kHz, 94 dB SPL sine wave and the  
idle noise output.  
Dynamic Range (DR)  
The ratio of the 10% THD microphone output level (in response to a sine wave input) and the idle noise  
output.  
Note: Unless otherwise specified, all performance measurements are specified with a low-pass brick-wall filter and, where noted, an  
A-weighted filter. The low-pass filter removes out-of-band noise.  
Table 3-2. Recommended Operating Conditions  
Parameter  
Symbol  
VDD  
GND  
Min  
1.62  
Typ  
1.8  
0
Max  
1.98  
Units  
V
V
Supply voltage  
Ground  
Clock frequency  
Operating temperature range  
F
T
0.3  
–40  
3.2  
+85  
MHz  
ºC  
CLK  
A
Table 3-3. Absolute Maximum Ratings  
Absolute maximum ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits.  
Device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified.  
Parameter  
Symbol  
VDD  
Min  
–0.3  
–0.3  
–10  
–40  
Max  
2.4  
Units  
V
V
mA  
ºC  
ºC  
%
1
Supply voltage  
1
[2]  
Input voltage  
V
2.3  
IN  
IN  
3
Input current  
I
+10  
+105  
30  
60  
+105  
Operating temperature range  
T
A
Storage temperature prior to soldering  
Storage relative humidity prior to soldering  
Storage temperature after soldering  
T
Stgp  
RH  
–40  
Stgp  
T
Stg  
ºC  
ESD-sensitive device. The CS7250B is manufactured on a CMOS process. It is therefore generically susceptible to damage from  
excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. This device is  
qualified to current JEDEC ESD standards  
1.All voltages are measured with respect to GND.  
2.If VDD is above the minimum recommended operating level (see Table 3-2), the maximum input voltage is VDD + 0.3 V.  
3.Input current is positive when flowing into the device.  
5
DS1072PP1  
CS7250B  
3 Characteristics and Specifications  
Table 3-4. Acoustic and Electrical Characteristics  
Test conditions (unless specified otherwise):  
VDD = 1.8 V, GND = 0 V, CLK = 3.072 MHz, TA = +25ºC, 55 ±15% RH, 1-kHz, 94 dB SPL test signal, no load on DATA pin.  
1
Parameter  
Min  
Typ  
Max  
Units  
General characteristics  
Directivity  
Polarity  
Omnidirectional  
Positive sound pressure  
THD < 10%  
Increasing density of 1s  
dBFS  
dB SPL  
2
Sensitivity  
–37  
–36  
131  
–35  
High Performance Mode Acoustic overload  
(CLK = 3.072 MHz)  
THD  
94 dB SPL  
125 dB SPL  
0.2  
1
%
%
SNR  
DR  
A-weighted  
A-weighted  
A-weighted  
A-weighted  
66  
103  
28  
–102  
–90  
dB  
dB  
dB SPL  
dBFS  
dBFS  
Acoustic noise floor  
Electrical noise floor  
PSR (with respect to VDD)  
100 mV p-p, swept sine wave,  
20 Hz–20 kHz, A-weighted  
Low Power Mode  
(CLK = 768 kHz)  
Acoustic overload  
THD  
SNR  
THD < 10%  
117 dB SPL  
20 Hz–8 kHz, A-weighted  
20 Hz–8 kHz, A-weighted  
20 Hz–8 kHz, A-weighted  
20 Hz–8 kHz, A-weighted  
120  
1
62  
88  
32  
dB SPL  
%
dB  
DR  
dB  
Acoustic noise floor  
Electrical noise floor  
PSR (with respect to VDD)  
dB SPL  
dBFS  
dBFS  
–98  
–90  
100 mV p-p, swept sine wave,  
20 Hz–8 kHz, A-weighted  
Frequency response  
Frequency response  
–3 dB low frequency  
+3 dB high frequency  
35  
13  
Hz  
kHz  
Frequency response flatness  
Input HIGH Level  
Input LOW Level  
Output HIGH Level  
Output LOW Level  
Input capacitance  
Input leakage  
200 Hz–8 kHz  
–1  
0.65 VDD  
3
+1  
dB  
V
V
V
V
pF  
A  
pF  
3
Digital I/O  
0.35 VDD  
I
= 1 mA 0.9 VDD  
OH  
I
OL  
= –1 mA  
–1  
0.1 VDD  
5
1
200  
Load capacitance (DATA)  
4
Miscellaneous  
characteristics  
Current consumption  
High Performance Mode, CLK = 3.072 MHz  
Low Power Mode, CLK = 768 kHz  
Standby Mode, CLK = 0 Hz  
650  
160  
5
10  
A  
A  
A  
Startup time  
From power applied to output within 0.5 dB  
of sensitivity specification  
15  
ms  
Mode-transition time  
CLK frequency range  
From Low Power Mode to High  
Performance Mode  
10  
ms  
5,6  
High Performance Mode  
Low Power Mode  
Standby Mode  
1.4  
300  
0
3.2  
800  
MHz  
kHz  
Hz  
1.Performance measurements are specified with a low-pass brick-wall filter and, where noted, an A-weighted filter. The low-pass filter removes  
out-of-band noise. The Low Power Mode is measured with a cut-off frequency of 8 kHz; all other measurements are with a 20 kHz cut-off frequency.  
2.Sensitivity is measured at production test 0.9 s after power up.  
3.Note that digital input pins should not be left unconnected or floating.  
4.Measured without a load on the DATA pin.  
5.High Performance and Low Power Modes are selected according to the CLK frequency.  
6.Standby Mode is selected when the CLK input is stopped; this is a power-saving mode. Normal operation resumes automatically when the CLK input  
frequency is within the specified operational limits. Note that the VDD supply is still required in Standby Mode.  
6
DS1072PP1  
CS7250B  
3 Characteristics and Specifications  
Table 3-5. Audio Interface Timing  
The following timing information is valid across the full range of recommended operating conditions.  
1
Parameter  
Symbol  
Min  
313  
60:40  
Typ  
Max  
3333  
40:60  
6
Units  
ns  
CLK cycle time  
CLK duty cycle  
CLK rise/fall time  
DATA enable time  
t
CY  
ns  
From rising CLK edge, LRSEL = 0  
From falling CLK edge, LRSEL = 1  
From rising CLK edge, LRSEL = 0  
From falling CLK edge, LRSEL = 1  
From falling CLK edge, LRSEL = 0  
From rising CLK edge, LRSEL = 1  
t
t
14  
14  
20  
20  
90  
90  
10  
10  
ns  
ns  
ns  
ns  
ns  
ns  
R_EN  
t
L_EN  
DATA valid time  
DATA disable time  
Notes:  
R_DV  
t
L_DV  
t
R_DIS  
t
L_DIS  
• The DATA output is high-impedance when not outputting data; this enables the outputs of two microphones to be connected together with  
the data from one microphone interleaved with the data from the other. (The microphones must be configured to transmit on opposite  
channels in this case.)  
• In a typical configuration, the left channel is transmitted following the rising CLK edge (LRSEL = 1). In this case, the left channel should be  
sampled by the receiving device on the falling CLK edge.  
• Similarly, the right channel is typically transmitted following the falling CLK edge (LRSEL = 0). In this case, the right channel should be  
sampled by the receiving device on the rising CLK edge.  
• The CS7250B operating mode is selected according to the CLK frequency; see Table 3-4 for further details.  
1.Digital microphone interface timing.  
tCY  
CLK  
(input)  
tL_DV  
DATA  
(LRSEL = 1)  
tL_DIS  
tL_EN  
tR_DV  
DATA  
(LRSEL = 0)  
tR_DIS  
tR_EN  
DATA is high-impedance (Hi-Z) when not outputting data  
7
DS1072PP1  
CS7250B  
4 Typical Performance  
4 Typical Performance  
4.1 Audio Frequency Response  
Test conditions: VDD = 1.8 V, GND = 0 V, CLK = 3.072 MHz, no load on DATA pin.  
10.0  
9.0  
8.0  
7.0  
6.0  
5.0  
4.0  
3.0  
2.0  
1.0  
0.0  
-1.0  
-2.0  
-3.0  
-4.0  
-5.0  
-6.0  
-7.0  
-8.0  
-9.0  
-10.0  
10  
100  
1000  
10000  
100000  
Frequency (Hz)  
Figure 4-1. Sensitivity vs. Audio Frequency (20 Hz–20 kHz)  
4.2 THD Performance  
Test conditions: VDD = 1.8 V, GND = 0 V, CLK = 3.072 MHz, no load on DATA pin.  
10.0  
9.0  
8.0  
7.0  
6.0  
5.0  
4.0  
3.0  
2.0  
1.0  
0.0  
90.0  
95.0  
100.0  
105.0  
110.0  
115.0  
120.0  
125.0  
130.0  
135.0  
Input Sound Pressure Level (dB SPL)  
Figure 4-2. THD (%) vs. Input Sound Pressure Level (dB SPL)  
8
DS1072PP1  
CS7250B  
5 Applications Information  
5 Applications Information  
Cirrus Logic provides a range of audio codecs incorporating a digital microphone input interface; these support direct  
connection to digital microphones such as the CS7250B.  
Further information on Cirrus Logic audio codecs is provided in the respective product data sheet, which is available from  
the Cirrus Logic website  
5.1 Important Assembly Guidelines  
Do not put a vacuum over the port hole of the microphone. Placing a vacuum over the port hole can damage the  
device.  
Do not board wash the microphone after a reflow process. Board washing and the associated cleaning agents can  
damage the device.  
Do not expose to ultrasonic cleaning methods.  
Do not use a vapor phase reflow process. The vapor can damage the device.  
Please refer to application note WAN0273 MEMS Mic Assembly and Handling Guidelines for further assembly and  
handling guidelines.  
5.2 PCB Land Pattern and Paste Stencil  
The recommended PCB land pattern and paste stencil pattern for the CS7250B microphone are shown in Fig. 5-1 and  
Fig. 5-2 respectively.  
See also application note WAN0284 General Design Considerations for MEMS Microphones for further details of PCB  
footprint design. Full definition of the package dimensions is provided in Section 6.  
The recommended PCB land pattern is shown in Fig. 5-1.  
Figure 5-1. PCB Land Pattern, Top View  
DS1072PP1  
9
CS7250B  
6 Package Dimension  
The recommended PCB paste stencil pattern is shown in Fig. 5-2.  
Figure 5-2. PCB Paste Stencil, Top View  
6 Package Dimension  
A
B
(
(
1.625)  
1.025)  
C
0.325 0.050  
1.325  
0.150  
C A B  
(R0.280)  
1.040  
Pick Area  
3
2X (1.252)  
2X (0.822)  
3.500 (3.140) (2.240)  
2
1
4
5
4X (0.522)  
(0.290)  
0.980  
(1.390)  
2X (1.675)  
0.488  
4X  
0.100  
C
(2.290)  
2.650  
4X (0.725)  
Top View  
Bottom View  
Side View  
Unless otherwise specified, dimensions are in millimeters and tolerance is 0.100  
7 Ordering Information  
Table 7-1. Ordering Information  
Halogen  
Free  
Pb  
Free  
Temperature  
Range  
Product  
Description  
Package  
Grade  
Container  
Order #  
CS7250B–CAZR  
CS7250B Digital MEMS  
Microphone with High  
LGA  
Yes  
Yes  
Commercial –40 to +85°C  
Tape and  
1
Reel  
Performance and Low  
Power Modes  
1.Reel quantity = 5000  
10  
DS1072PP1  
CS7250B  
8 References  
8 References  
WAN0273 MEMS Mic Assembly and Handling Guidelines  
WAN0284 General Design Considerations for MEMS Microphones  
9 Revision History  
Table 9-1. Revision History  
Changes  
Revision  
• Clarification of sensitivity specification added (Table 3-4).  
PP1  
• THD and frequency-response specifications updated (Table 3-4).  
• Frequency response plot updated (Section 4.2).  
• Order quantity updated (Section 7).  
MAY ‘17  
Contacting Cirrus Logic Support  
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.  
To find the one nearest you, go to www.cirrus.com.  
IMPORTANT NOTICE  
“Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. For the purposes of our  
terms and conditions of sale, “Preliminary” or “Advanced” data sheets are nonfinal data sheets that include, but are not limited to, data sheets marked as “Target”,  
“Advance”, “Product Preview”, “Preliminary Technical Data”, and/or “Preproduction”. Products provided with any such data sheet are therefore subject to relevant  
terms and conditions associated with “Preliminary” or “Advanced” designations. The products and services of Cirrus Logic International (UK) Limited; Cirrus Logic,  
Inc.; and other companies in the Cirrus Logic group (collectively either “Cirrus Logic” or “Cirrus”) are sold subject to Cirrus Logic’s terms and conditions of sale  
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. Software is provided pursuant to  
applicable license terms. Cirrus Logic reserves the right to make changes to its products and specifications or to discontinue any product or service without notice.  
Customers should therefore obtain the latest version of relevant information from Cirrus Logic to verify that the information is current and complete. Testing and  
other quality control techniques are utilized to the extent Cirrus Logic deems necessary. Specific testing of all parameters of each device is not necessarily  
performed. In order to minimize risks associated with customer applications, the customer must use adequate design and operating safeguards to minimize  
inherent or procedural hazards. Cirrus Logic is not liable for applications assistance or customer product design. The customer is solely responsible for its selection  
and use of Cirrus Logic products. Use of Cirrus Logic products may entail a choice between many different modes of operation, some or all of which may require  
action by the user, and some or all of which may be optional. Nothing in these materials should be interpreted as instructions or suggestions to choose one mode  
over another. Likewise, description of a single mode should not be interpreted as a suggestion that other modes should not be used or that they would not be  
suitable for operation. Features and operations described herein are for illustrative purposes only.  
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR  
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS LOGIC PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN  
PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, NUCLEAR SYSTEMS, LIFE SUPPORT PRODUCTS OR  
OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS LOGIC PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S  
RISK AND CIRRUS LOGIC DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF  
MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS LOGIC PRODUCT THAT IS USED IN SUCH A MANNER. IF THE  
CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS LOGIC PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY  
SUCH USE, TO FULLY INDEMNIFY CIRRUS LOGIC, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL  
LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.  
This document is the property of Cirrus Logic and by furnishing this information, Cirrus Logic grants no license, express or implied, under any patents, mask work  
rights, copyrights, trademarks, trade secrets or other intellectual property rights. Any provision or publication of any third party’s products or services does not  
constitute Cirrus Logic’s approval, license, warranty or endorsement thereof. Cirrus Logic gives consent for copies to be made of the information contained herein  
only for use within your organization with respect to Cirrus Logic integrated circuits or other products of Cirrus Logic, and only if the reproduction is without  
alteration and is accompanied by all associated copyright, proprietary and other notices and conditions (including this notice). This consent does not extend to  
other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. This document and its information  
is provided “AS IS” without warranty of any kind (express or implied). All statutory warranties and conditions are excluded to the fullest extent possible. No  
responsibility is assumed by Cirrus Logic for the use of information herein, including use of this information as the basis for manufacture or sale of any items, or  
for infringement of patents or other rights of third parties. Cirrus Logic, Cirrus, the Cirrus Logic logo design, and SoundClear are among the trademarks of Cirrus  
Logic. Other brand and product names may be trademarks or service marks of their respective owners.  
Copyright © 2015–2017 Cirrus Logic, Inc. All rights reserved.  
DS1072PP1  
11  
配单直通车
CS7311-4产品参数
型号:CS7311-4
生命周期:Contact Manufacturer
IHS 制造商:SHOKAI FAR EAST LTD
Reach Compliance Code:unknown
风险等级:5.59
Is Samacsys:N
Base Number Matches:1
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