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  • 北京元坤伟业科技有限公司

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产品型号CSD17527Q5A的概述

CSD17527Q5A芯片的概述 CSD17527Q5A是一款由德州仪器(Texas Instruments,TI)生产的N沟道MOSFET( Metal-Oxide-Semiconductor Field-Effect Transistor),广泛应用于各种电子电路中。作为高效率的功率管理器件,其特性使其在电源转换和开关应用中表现出色。此芯片在尺寸、功率密度以及热管理方面种种优点,使得它成为现代电子设计中的常用元件之一。 在考虑MOSFET的应用时,CSD17527Q5A也因其低导通电阻和高电流承载能力受到市场欢迎。它适合应用于便携设备、电源模块、DC-DC转换器及电池管理系统等领域。CSD17527Q5A的设计不仅能够提高系统的效率,还能降低其整体发热量,这对于现代电子设备的稳定性和性能至关重要。 CSD17527Q5A芯片的详细参数 CSD17527Q5A的关键参数如下: - 阈...

产品型号CSD17527Q5A的Datasheet PDF文件预览

CSD17327Q5A  
www.ti.com  
SLPS332 JUNE 2011  
30V, N-Channel NexFETPower MOSFETs  
Check for Samples: CSD17327Q5A  
PRODUCT SUMMARY  
Drain to Source Voltage  
1
FEATURES  
VDS  
Qg  
30  
2.8  
0.8  
V
2
Ultralow Qg and Qgd  
Low Thermal Resistance  
Avalanche Rated  
Pb Free Terminal Plating  
RoHS Compliant  
Gate Charge Total (4.5V)  
Gate Charge Gate to Drain  
nC  
nC  
mΩ  
mΩ  
V
Qgd  
VGS = 4.5V  
VGS = 8V  
12.5  
9.9  
RDS(on) Drain to Source On Resistance  
VGS(th) Threshold Voltage  
1.6  
Halogen Free  
SON 5-mm × 6-mm Plastic Package  
Text Added For Spacing  
ORDERING INFORMATION  
Device  
CSD17327Q5A  
Package  
Media  
Qty  
Ship  
APPLICATIONS  
SON 5-mm × 6-mm  
Plastic Package  
13-Inch  
Reel  
Tape and  
Reel  
Point-of-Load Synchronous Buck in  
2500  
Networking, Telecom and Computing Systems  
Optimized for Control FET Applications  
Text Added For Spacing  
ABSOLUTE MAXIMUM RATINGS  
DESCRIPTION  
TA = 25°C unless otherwise stated  
VALUE  
UNIT  
V
The NexFETpower MOSFET has been designed  
to minimize losses in power conversion applications.  
VDS  
VGS  
Drain to Source Voltage  
30  
Gate to Source Voltage  
+10 / -10  
V
Continuous Drain Current, TC = 25°C  
Continuous Drain Current(1)  
Pulsed Drain Current, TA = 25°C(2)  
Power Dissipation(1)  
65  
13  
85  
3
A
Top View  
ID  
A
S
S
S
G
1
2
3
4
8
7
6
5
D
D
D
IDM  
PD  
TJ,  
A
W
Operating Junction and Storage  
TSTG Temperature Range  
55 to 150  
°C  
Avalanche Energy, single pulse  
ID = 30A, L = 0.1mH, RG = 25Ω  
EAS  
45  
mJ  
D
=
44°C/W on 1-inch2 (6.45-cm2), 2-oz.  
D
(1) Typical RθJA  
(0.071-mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4  
PCB.  
P0093-01  
(2) Pulse duration 300μs, duty cycle 2%  
Text 4 Spacing  
RDS(on) vs VGS  
Text 4 Spacing  
GATE CHARGE  
35  
30  
25  
20  
15  
10  
5
10  
ID = 11A  
ID = 11A  
VDD = 15V  
9
8
7
6
5
4
3
2
1
0
TC = 25°C  
TC = 125ºC  
0
0
1
2
3
4
5
6
7
8
9
10  
0
1
2
3
4
5
6
Qg - Gate Charge - (nC)  
VGS - Gate-to- Source Voltage - V  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NexFET is a trademark of Texas Instruments.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2011, Texas Instruments Incorporated  
 
 
CSD17327Q5A  
SLPS332 JUNE 2011  
www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
ELECTRICAL CHARACTERISTICS  
(TA = 25°C unless otherwise stated)  
PARAMETER  
Static Characteristics  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
BVDSS  
IDSS  
Drain to Source Voltage  
VGS = 0V, IDS = 250μA  
30  
V
μA  
nA  
V
Drain to Source Leakage Current  
Gate to Source Leakage Current  
Gate to Source Threshold Voltage  
VGS = 0V, VDS = 24V  
VDS = 0V, VGS = +10/-10V  
VDS = VGS, IDS = 250μA  
VGS = 4.5V, IDS = 11A  
VGS = 8V, IDS = 11A  
1
100  
2.0  
IGSS  
VGS(th)  
1.1  
1.6  
12.5  
9.9  
15.5  
12.2  
mΩ  
mΩ  
S
RDS(on)  
Drain to Source On Resistance  
gfs  
Transconductance  
VDS = 15V, IDS = 11A  
44  
Dynamic Characteristics  
Ciss  
Coss  
Crss  
RG  
Input Capacitance  
422  
286  
26  
506  
343  
33  
pF  
pF  
pF  
VGS = 0V, VDS = 15V,  
f = 1MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Series Gate Resistance  
Gate Charge Total (4.5V)  
Gate Charge Gate to Drain  
Gate Charge Gate to Source  
Gate Charge at Vth  
Output Charge  
4.7  
2.8  
0.8  
1.2  
0.6  
6.8  
5.6  
8.2  
9.8  
3.2  
Qg  
3.4  
nC  
nC  
nC  
nC  
nC  
ns  
ns  
ns  
ns  
Qgd  
Qgs  
Qg(th)  
Qoss  
td(on)  
tr  
VDS = 15V, IDS = 11A  
VDS = 13V, VGS = 0V  
Turn On Delay Time  
Rise Time  
VDS = 15V, VGS = 4.5V,  
IDS = 11A,RG = 2Ω  
td(off)  
tf  
Turn Off Delay Time  
Fall Time  
Diode Characteristics  
VSD  
Qrr  
trr  
Diode Forward Voltage  
ISD = 11A, VGS = 0V  
0.85  
10.5  
14.6  
1
V
Reverse Recovery Charge  
Reverse Recovery Time  
nC  
ns  
VDS= 13V, IF = 11A, di/dt = 300A/μs  
THERMAL CHARACTERISTICS  
(TA = 25°C unless otherwise stated)  
PARAMETER  
Thermal Resistance Junction to Case(1)  
Thermal Resistance Junction to Ambient(1)(2)  
MIN  
TYP  
MAX  
UNIT  
°C/W  
°C/W  
RθJC  
RθJA  
1.9  
51  
(1)  
R
θJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×  
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the users board design.  
(2) Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.  
2
Copyright © 2011, Texas Instruments Incorporated  
CSD17327Q5A  
www.ti.com  
SLPS332 JUNE 2011  
GATE  
Source  
GATE  
Source  
Max RθJA = 51°C/W  
when mounted on  
1 inch2 (6.45 cm2) of  
2-oz. (0.071-mm thick)  
Cu.  
Max RθJA = 131°C/W  
when mounted on a  
minimum pad area of  
2-oz. (0.071-mm thick)  
Cu.  
DRAIN  
DRAIN  
M0137-02  
M0137-01  
TYPICAL MOSFET CHARACTERISTICS  
(TA = 25°C unless otherwise stated)  
10  
1
0.5  
0.3  
0.1  
0.1  
0.05  
Duty Cycle = t1/t2  
0.02  
0.01  
0.01  
0.001  
0.0001  
P
Single Pulse  
t1  
t2  
Typical RqJA = 105°C/W (min Cu)  
TJ = P ´ ZqJA ´ RqJA  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
1k  
tp - Pulse Duration - s  
G012  
Figure 1. Transient Thermal Impedance  
Copyright © 2011, Texas Instruments Incorporated  
3
CSD17327Q5A  
SLPS332 JUNE 2011  
www.ti.com  
TYPICAL MOSFET CHARACTERISTICS (continued)  
(TA = 25°C unless otherwise stated)  
TEXT ADDED FOR SPACING  
TEXT ADDED FOR SPACING  
30  
25  
20  
15  
10  
5
100  
10  
VGS = 8V  
VDS = 5V  
VGS = 4.5V  
1
TC = -55°C  
VGS = 3.5V  
0.1  
TC = 25°C  
VGS = 3V  
VGS = 2.5V  
0.01  
0.001  
TC = 125°C  
0
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
1.6  
0
1
2
3
4
5
VDS - Drain-to-Source Voltage - V  
VGS - Gate-to-Source Voltage - V  
G001  
G002  
Figure 2. Saturation Characteristics  
TEXT ADDED FOR SPACING  
Figure 3. Transfer Characteristics  
TEXT ADDED FOR SPACING  
Ciss = Cgd + Cgs  
1
10  
9
8
7
6
5
4
3
2
1
0
ID = 11A  
VDD = 15V  
Coss = Cds + Cgd  
0.1  
Crss = Cgd  
f = 1MHz  
VGS = 0V  
0.01  
0
1
2
3
4
5
6
0
5
10  
15  
20  
VDS - Drain-to-Source Voltage - V  
25  
30  
Qg - Gate Charge - (nC)  
G004  
Figure 4. Gate Charge  
Figure 5. Capacitance  
TEXT ADDED FOR SPACING  
TEXT ADDED FOR SPACING  
2.5  
2
35  
30  
25  
20  
15  
10  
5
ID = 11A  
ID = 250µA  
1.5  
1
0.5  
0
TC = 25°C  
TC = 125ºC  
0
0
1
2
3
4
5
6
7
8
9
10  
-75  
-25  
25  
75  
125  
175  
TC - Case Temperature - °C  
VGS - Gate-to- Source Voltage - V  
G005  
Figure 6. Threshold Voltage vs. Temperature  
Figure 7. On-State Resistance vs. Gate-to-Source Voltage  
4
Copyright © 2011, Texas Instruments Incorporated  
CSD17327Q5A  
www.ti.com  
SLPS332 JUNE 2011  
TYPICAL MOSFET CHARACTERISTICS (continued)  
(TA = 25°C unless otherwise stated)  
TEXT ADDED FOR SPACING  
TEXT ADDED FOR SPACING  
100  
10  
1.8  
1.6  
1.4  
1.2  
1
ID = 11A  
VGS = 10V  
1
TC = 125°C  
0.1  
TC = 25°C  
0.8  
0.6  
0.4  
0.2  
0.01  
0.001  
0.0001  
−75  
−25  
25  
75  
125  
175  
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
VSD - Source-to-Drain Voltage - V  
TC - Case Temperature - ºC  
G008  
Figure 8. Normalized On-State Resistance vs. Temperature  
Figure 9. Typical Diode Forward Voltage  
TEXT ADDED FOR SPACING  
TEXT ADDED FOR SPACING  
1k  
100  
10  
1
100  
TC = 25°C  
101011s0  
10  
1ms  
1
TC = 125°C  
10ms  
Area Limited  
by RDS(on)  
110101m0s  
0.1  
1s  
Single Pulse  
Typical RθJA = 105°C/W (min Cu)  
DC  
0.01  
0.01  
0.1  
1
10  
100  
0.01  
0.1  
1
10  
VDS - Drain-to-Source Voltage - V  
t(AV) - Time in Avalanche - ms  
G009  
G010  
Figure 10. Maximum Safe Operating Area  
Figure 11. Single Pulse Unclamped Inductive Switching  
TEXT ADDED FOR SPACING  
TEXT ADDED FOR SPACING  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
-50  
-25  
0
25  
50  
75  
100 125 150 175  
TC - Case Temperature - °C  
Figure 12. Maximum Drain Current vs. TemperatuGre011  
Copyright © 2011, Texas Instruments Incorporated  
5
CSD17327Q5A  
SLPS332 JUNE 2011  
www.ti.com  
MECHANICAL DATA  
Q5A Package Dimensions  
E2  
L
H
K
q
e
D1  
D2  
b
L1  
Top View  
Side View  
Bottom View  
q
A
c
E1  
E
Front View  
M0135-01  
MILLIMETERS  
DIM  
MIN  
0.90  
0.33  
0.20  
4.80  
3.61  
5.90  
5.70  
3.38  
1.17  
0.41  
1.10  
0.51  
0.06  
0°  
NOM  
1.00  
0.41  
0.25  
4.90  
3.81  
6.00  
5.75  
3.58  
1.27  
0.56  
MAX  
1.10  
0.51  
0.34  
5.00  
4.02  
6.10  
5.80  
3.78  
1.37  
0.71  
A
b
c
D1  
D2  
E
E1  
E2  
e
H
K
L
0.61  
0.13  
0.71  
0.20  
12°  
L1  
θ
6
Copyright © 2011, Texas Instruments Incorporated  
CSD17327Q5A  
www.ti.com  
SLPS332 JUNE 2011  
Recommended PCB Pattern  
4.900 (0.193)  
0.630 (0.025)  
0.605 (0.024)  
0.620 (0.024)  
4.460  
1.270  
(0.050)  
(0.176)  
0.650 (0.026)  
0.700 (0.028)  
3.102 (0.122)  
1.798 (0.071)  
M0139-01  
NOTE: Dimensions are in mm (inches).  
TEXT ADDED FOR SPACING  
Stencil Recommendation  
0.500 (0.020)  
1.235 (0.049)  
0.500 (0.020)  
1.585 (0.062)  
0.450  
(0.018)  
1.570  
(0.062)  
0.620 (0.024)  
1.270  
(0.050)  
4.260  
(0.168)  
1.570  
(0.062)  
PCB Pattern  
0.632 (0.025)  
3.037 (0.120)  
1.088 (0.043)  
Stencil Opening  
M0209-01  
NOTE: Dimensions are in mm (inches).  
TEXT  
ADDED  
FOR  
SPACING  
For recommended circuit layout for PCB designs, see application note SLPA005 Reducing Ringing Through  
PCB Layout Techniques.  
Copyright © 2011, Texas Instruments Incorporated  
7
CSD17327Q5A  
SLPS332 JUNE 2011  
www.ti.com  
Q5A Tape and Reel Information  
K0  
4.00 0.ꢀ0 ꢁ(SS ꢂNoS ꢀ1  
0.30 0.05  
2.00 0.05  
+0.ꢀ0  
–0.00  
Ø ꢀ.50  
ꢀ.75 0.ꢀ0  
5.50 0.05  
ꢀ2.00 0.30  
B0  
R 0.30 MAX  
A0  
8.00 0.ꢀ0  
Ø ꢀ.50 MIꢂ  
R 0.30 TYP  
A0 = 6.50 0.ꢀ0  
B0 = 5.30 0.ꢀ0  
K0 = ꢀ.40 0.ꢀ0  
M0ꢀ38-0ꢀ  
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2  
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm  
3. Material: black static-dissipative polystyrene  
4. All dimensions are in mm (unless otherwise specified)  
5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket  
spacer  
8
Copyright © 2011, Texas Instruments Incorporated  
PACKAGE OPTION ADDENDUM  
www.ti.com  
22-Aug-2011  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
CSD17327Q5A  
ACTIVE  
SON  
DQJ  
8
2500  
Pb-Free (RoHS  
Exempt)  
CU SN  
Level-1-260C-UNLIM  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
2-Mar-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
CSD17327Q5A  
SON  
DQJ  
8
2500  
330.0  
12.4  
6.3  
5.3  
1.2  
8.0  
12.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
2-Mar-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SON DQJ  
SPQ  
Length (mm) Width (mm) Height (mm)  
340.0 340.0 38.0  
CSD17327Q5A  
8
2500  
Pack Materials-Page 2  
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Copyright © 2012, Texas Instruments Incorporated  
配单直通车
CSD17527Q5A产品参数
型号:CSD17527Q5A
Brand Name:Texas Instruments
是否无铅: 不含铅
是否Rohs认证: 符合
生命周期:Active
零件包装代码:SON
包装说明:VSONP-8
针数:8
Reach Compliance Code:not_compliant
ECCN代码:EAR99
HTS代码:8541.29.00.95
风险等级:1.69
其他特性:AVALANCHE RATED
雪崩能效等级(Eas):45 mJ
外壳连接:DRAIN
配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:30 V
最大漏极电流 (Abs) (ID):65 A
最大漏极电流 (ID):13 A
最大漏源导通电阻:0.0155 Ω
FET 技术:METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss):33 pF
JESD-30 代码:R-PDSO-N8
JESD-609代码:e3
湿度敏感等级:1
元件数量:1
端子数量:5
工作模式:ENHANCEMENT MODE
最高工作温度:150 °C
最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE
峰值回流温度(摄氏度):260
极性/信道类型:N-CHANNEL
最大功率耗散 (Abs):3 W
最大脉冲漏极电流 (IDM):85 A
认证状态:Not Qualified
子类别:FET General Purpose Power
表面贴装:YES
端子面层:Matte Tin (Sn)
端子形式:NO LEAD
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
晶体管应用:SWITCHING
晶体管元件材料:SILICON
Base Number Matches:1
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