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产品型号CXP820P60Q-1-XXX的Datasheet PDF文件预览

CXP820P60  
CMOS 8-bit Single Chip Microcomputer  
Description  
100 pin QFP (Plastic)  
The CXP820P60 is a CMOS 8-bit single chip  
microcomputer integrating on a single chip an A/D  
converter, serial interface, timer/counter, time-base  
timer, capture timer/counter, fluorescent display panel  
controller/driver, remote control reception circuit, and  
PWM output circuit besides the basic configurations  
of 8-bit CPU, ROM, RAM, and I/O port.  
The CXP820P60 also provides sleep/stop function  
that enables lower power consumption.  
CXP820P60 is the PROM-incorporated version of the  
CXP82052/82060 with bult-in mask ROM. This provides  
the additional feature of being able to write directly into  
the program. Thus, it is most suitable for evaluation  
use during system development and for small-quantity  
production.  
Structure  
Silicon gate CMOS IC  
Features  
Wide-range instruction system (213 instructions) to cover various types of data  
— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions  
Minimum instruction cycle  
250ns at 16MHz operation  
122µs at 32kHz operation  
60K bytes  
Incorporated PROM capacity  
Incorporated RAM capacity  
Peripheral functions  
3984 bytes (including fluorescent display area)  
— A/D converter  
8 bits, 8 channels, successive approximation method  
(Conversion time of 3.25µs/16MHz)  
— Serial interface  
— Timer  
Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel  
8-bit clock synchronized type, (MSB/LSB first selectable), 1 channel  
Start-stop synchronization (UART), 1 channel  
8-bit timer, 8-bit timer/counter, 19-bit time-base timer  
16-bit capture timer/counter, 32kHz timer/counter  
Supports the universal grid fluorescent display panel  
High voltage drive output port of 56 pins (40V)  
Maximum of 640 segments display possible  
Display timing number of 1 to 20  
— Fluorescent display panel  
controller/driver  
Dimmer function  
Incorporated pull-down resistor (mask option)  
Hardware key scan function (Maximum of 16 × 8 key matrix  
supportable)  
— Remote control reception circuit  
— PWM output  
8-bit pulse measurement counter, 6-stage FIFO  
14 bits, 1 channel  
Interruption  
Standby mode  
17 factors, 15 vectors, multi-interruption possible  
Sleep/stop  
Package  
100-pin plastic QFP  
Piggy/Evaluation chip  
CXP82000 100-pin ceramic QFP  
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by  
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the  
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.  
– 1 –  
E97638A1Y-PS  
CXP820P60  
P O R T A P O R T B P O R T C P O R T D P O R T E P O R T F P O R T G P O R T H P O R T I  
V p p  
S S V  
D D V  
R S T  
X T A L  
E X T A L  
T X  
T E X  
I N T 3 / N
I N T 2  
I N T 1  
I N T 0  
I N T E R R U P T C O N T R O L L E R  
– 2 –  
CXP820P60  
Pin Assignment (Top View)  
99 98  
96 95 94 93 92 91  
90 89 88 87 86 85 84 83 82 81  
100  
97  
1
2
G1/A1  
G0/A0  
Vpp  
A21  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
A22  
3
A23  
4
PH7/A24  
PH6/A25  
PH5/A26  
PH4/A27  
PH3/A28  
PH2/A29  
PH1/A30  
PH0/A31  
PG7/A32  
PG6/A33  
PG5/A34  
PG4/A35  
PG3/A36  
PG2/A37  
PG1/A38  
PG0/A39  
PF7/A40  
PF6/A41  
PF5/A42  
PF4/A43  
PF3/A44  
PF2/A45  
PF1/A46  
PF0/A47  
PD7/A48  
PD6/A49  
PD5/A50  
PE0/EC0/INT0  
PE1/EC1/INT1  
PE2/INT2  
PE3/INT3/NMI  
PE4/RMC  
PE5/CINT  
PE6/PWM  
PE7/TO/ADJ  
PC0/KR0  
PC1/KR1  
PC2/KR2  
PC3/KR3  
PC4/KR4  
PC5/KR5  
PC6/KR6  
PC7/KR7  
PB0/TxD  
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
PB1/CS0/RxD  
PB2/SCK0  
PB3/SI0  
PB4/SO0  
PB5/SCK1  
PB6/SI1  
PB7/SO1  
PI0  
PA0/AN0  
PA1/AN1  
31  
32 33  
34  
35  
36 37 38  
39  
40 41 42  
43 44 45 46  
47  
48 49 50  
Note) 1. Vpp (Pin 3) is left open.  
2. VDD (Pins 44 and 89) are both connected to VDD.  
3 –  
CXP820P60  
Pin Description  
Symbol  
I/O  
Functions  
(Port A)  
8-bit I/O port. I/O can be set in a  
unit of single bits. Incorporation  
of the pull-up resistor can be set  
through the program in a unit of  
4 bits.  
PA0/AN0  
to  
PA7/AN7  
Analog inputs to A/D converter.  
(8 pins)  
I/O/  
Analog input  
(8 pins)  
PB0/TxD  
UART transmission data output.  
I/O/Output  
UART reception  
data input.  
Chip select input for  
serial interface (CH0).  
PB1/CS0/RxD  
I/O/Input/Input  
(Port B)  
8-bit I/O port. I/O can be set in a  
unit of single bits. Incorporation  
of the pull-up resistor can be set  
through the program in a unit of  
4 bits.  
PB2/SCK0  
PB3/SI0  
Serial clock I/O (CH0).  
Serial data input (CH0).  
Serial data output (CH0).  
Serial clock I/O (CH1).  
Serial data input (CH1).  
Serial data output (CH1).  
I/O/I/O  
I/O/Input  
I/O/Output  
I/O/I/O  
PB4/SO0  
PB5/SCK1  
PB6/SI1  
(8 pins)  
I/O/Input  
I/O/Output  
PB7/SO1  
(Port C)  
8-bit I/O port. I/O can be set in a  
unit of single bits. Capable of  
driving 12mA sink current.  
Incorporation of the pull-up  
resistor can be set through the  
program in a unit of 4 bits.  
(8 pins)  
Serves as key return inputs when  
operating key scan with fluorescent  
display panel (FDP) segment signal.  
(8 pins)  
PC0/KR0  
to  
PC7/KR7  
I/O/Input  
(Port D)  
PD0/A55  
to  
PD7/A48  
8-bit I/O port. I/O can be set in a FDP segment signal (anode  
unit of single bits.  
(8 pins)  
I/O/Output  
connection) outputs.  
PE0/INT0/  
EC0  
Input/Input/Input  
External event inputs  
for timer/counter.  
(2 pins)  
Inputs for  
external  
interruption  
request.  
(4 pins)  
PE1/INT1/  
EC1  
Input/Input/Input  
Input/Input  
PE2/INT2  
(Port E)  
Non-maskable  
interruption request input.  
PE3/INT3/  
NMI  
Input/Input/Input  
Input/Input  
8-bit port. Lower 6 bits are for  
inputs; upper 2 bits are for  
outputs.  
Remote control reception circuit input.  
PE4/RMC  
PE5/CINT  
PE6/PWM  
(8 pins)  
External capture input for 16-bit  
timer/counter.  
Input/Input  
14-bit PWM output.  
Output/Output  
Output for the 16-bit timer/counter  
rectangular waves, and 32kHz  
oscillation frequency division.  
PE7/TO/  
ADJ  
Output/Output/  
Output  
4 –  
CXP820P60  
Symbol  
I/O  
Functions  
FDP segment signal (anode  
(Port F)  
PF0/A47  
to  
PF7/A40  
8-bit output port. I/O can be set  
in a unit of single bits.  
(8 pins)  
I/O/Output  
connection) outputs.  
(8 pins)  
PG0/A39  
to  
PG7/A32  
(Port G)  
8-bit output port.  
(8 pins)  
FDP segment signal (anode  
connection) outputs.  
(8 pins)  
Output/Output  
Output/Output  
(Port H)  
8-bit output port.  
(8 pins)  
PH0/A31  
to  
PH7/A24  
FDP segment signal (anode  
connection) outputs.  
(8 pins)  
PI0  
Input  
Input  
Input  
(Port I)  
4-bit input port.  
(4 pins)  
PI1  
Crystal connectors for 32kHz timer/counter clock  
oscillation. For usage as event counter, input to TEX,  
and leave TX open.  
PI2/TX  
Input/Input  
Output  
PI3/TEX  
FDP segment signal (anode connection) outputs.  
(8 pins)  
A16 to A23  
Outputs for FDP timing signals (grid connection)/segment signals (anode  
connection).  
(16 pins)  
G0/A0  
to  
G15/A15  
Output/Output  
FDP voltage supply for incorporated pull-down (PD) resistor.  
VFDP  
Crystal connectors for system clock oscillation. When the clock is  
supplied externally, input to EXTAL; opposite phase clock should be  
input to XTAL.  
Input  
Input  
EXTAL  
XTAL  
RST  
Low-level active, system reset.  
Vcc supply for incorporated PROM writing.  
Leave this pin open during normal operation.  
Vpp  
VDD  
Positive power supply.  
GND.  
VSS  
5 –  
CXP820P60  
I/O Circuit Format for Pins  
Pin  
Circuit format  
After a reset  
Port A  
Pull-up registor  
"0" after a reset  
Port A data  
PA0/AN0  
to  
PA7/AN7  
Port A direction  
"0" after a reset  
IP  
Input protection circuit  
Hi-Z  
Internal  
data bus  
RD (Port A)  
Port A input selecton  
"0" after a reset  
Input multiplexer  
A/D converter  
8 pins  
Pull-up transistor approx. 100kΩ  
Port B  
Pull-up registor  
"0" after a reset  
TxD  
UART output selection  
"0" after a reset  
PB0/TxD  
Hi-Z  
Port B data  
IP  
Port B direction  
"0" after a reset  
Internal  
data bus  
RD (Port B)  
1 pin  
Pull-up transistor approx. 100kΩ  
Port B  
Pull-up registor  
"0" after a reset  
Port B data  
PB1/CS0/RxD  
PB3/SI0  
PB6/SI1  
Port B direction  
"0" after a reset  
IP  
Hi-Z  
Schmitt input  
Internal  
data bus  
RD (Port B)  
CS0  
SI0  
SI1  
RxD  
Pull-up transistor approx. 100kΩ  
3 pins  
6 –  
CXP820P60  
Pin  
Circuit format  
After a reset  
Port B  
Pull-up registor  
"0" after a reset  
SCK OUT  
Serial clock output enable  
Port B output selecton  
"0" after a reset  
PB2/SCK0  
PB5/SCK1  
Hi-Z  
Port B data  
IP  
Port B direction  
"0" after a reset  
Schmitt input  
Internal  
data bus  
RD (Port B)  
2 pins  
Pull-up transistor approx. 100kΩ  
SCK IN  
Port B  
Pull-up registor  
"0" after a reset  
SO  
Serial data output enable  
Port B outputput selecton  
"0" after a reset  
PB4/SO0  
PB7/SO1  
Hi-Z  
Port B data  
IP  
Port B direction  
"0" after a reset  
Internal  
data bus  
RD (Port B)  
2 pins  
Pull-up transistor approx. 100kΩ  
Port C  
2
Pull-up registor  
"0" after a reset  
Port C data  
PC0/KR0  
to  
1
PC7/KR7  
Hi-Z  
Port C direction  
"0" after a reset  
IP  
Internal  
data bus  
RD (Port C)  
Key input signal  
1
Large current 12mA  
Pull-up transistor approx. 100kΩ  
8 pins  
2
7 –  
CXP820P60  
Pin  
Circuit format  
After a reset  
Port E  
PE0/EC0/INT0  
PE1/EC1/INT1  
PE2/INT2  
PE3/INT3/NMI  
PE4/RMC  
EC0/INT0  
EC1/INT1  
INT2  
INT3/NMI  
RMC  
Schmitt input  
IP  
Hi-Z  
CINT  
Internal data bus  
PE5/CINT  
RD (Port E)  
6 pins  
Port E  
PWM  
Port E output selecton  
"0" after a reset  
PE6/PWM  
High level  
Port E data  
Output enable  
"1" after a reset  
Internal  
data bus  
RD (Port E)  
1 pin  
Port E  
Internal reset signal  
MPX  
00  
Port E data  
"1" after a reset  
TO  
01  
10  
11  
High level  
(High level at  
ON resistance  
of pull-up  
1
ADJ16K  
2
2
ADJ2K  
PE7/TO/ADJ  
Port E output selecton (upper)  
transistor  
during a reset)  
Port E output selecton (lower)  
"00" after a reset  
1 ADJ signal is a frequency dividing output  
for 32kHz oscillation frequency adjustment.  
ADJ2K can be used for buzzer output.  
TO output enable  
2 Pull-up transistor approx. 150kΩ  
1 pin  
Port D  
Port F  
Segment output data  
Output selection control signal  
("0" after a reset)  
PD0/A55  
to  
PD7/A48  
PF0/A47  
to  
Port D and F data  
Hi-Z  
IP  
Port D and F direction  
"1" after a reset  
PF7/A40  
Internal  
data bus  
RD (Port D and F)  
16 pins  
High voltage drive transistor  
8 –  
CXP820P60  
Pin  
Circuit format  
After a reset  
Port G  
Port H  
Segment output data  
PG0/A39  
to  
Output selection control signal  
("0" after a reset)  
PG7/A32  
PH0/A31  
to  
Port G and H data  
"0" after a reset  
Hi-Z  
PH7/A24  
Internal  
data bus  
High voltage drive transistor  
16 pins  
RD (Port G and H)  
Segment output data  
Output selection control signal  
("0" after a reset)  
Hi-Z or Low  
level (when  
PD resistor is  
connected)  
A16 to A23  
8 pins  
Pull-down registor  
VFDP  
High voltage drive transistor  
Segment output data  
Timing output data  
G0/A0  
to  
Hi-Z or Low  
level (when  
PD resistor is  
connected)  
Output selection control signal  
("0" after a reset)  
G15/A15  
Pull-down registor  
VFDP  
16 pins  
High voltage drive transistor  
Diagram shows circuit  
composition during  
oscillation.  
EXTAL  
XTAL  
IP  
EXTAL  
XTAL  
IP  
Oscillation  
Feedback resistor is  
removed and XTAL  
becomes High level  
during stop.  
2 pins  
PI0  
PI1  
IP  
Internal data bus  
Hi-Z  
RD (Port I)  
2 pins  
9 –  
CXP820P60  
Pin  
Circuit format  
After a reset  
TEX oscillation circuit control  
"1" after a reset  
Internal  
data bus  
RD  
Internal  
data bus  
PI2/TX  
PI3/TEX  
Oscillation  
stop port  
input  
RD  
IP  
IP  
PI3/TEX  
Clock input  
PI2/TX  
2 pins  
Pull-up registor  
RST  
1 pin  
Low level  
IP  
Schmitt input  
10 –  
CXP820P60  
Absolute Maximum Ratings  
(Vss = 0V reference)  
Item  
Symbol  
VDD  
Rating  
Unit  
V
Remarks  
0.3 to +7.0  
0.3 to +13.0  
40 2 to +7.0  
Supply voltage  
Vpp  
V
Incorporated PROM  
1
FDP display supply voltage  
Input voltage  
VFDP  
VIN  
V
1
0.3 to +7.0  
0.3 to +7.0  
40 2 to +7.0  
V
1
Output voltage  
VOUT  
VOD  
V
1
Display output voltage  
V
3
All pins excluding display outputs  
(value per pin)  
5  
IOH  
mA  
High level output current  
15  
50  
IODH1  
IODH2  
mA Display outputs A20 to A55 (value per pin)  
Display outputs G0/A0 to G15/A15, and  
mA  
A16 to A19 (value per pin)  
30  
IOH  
mA Total for all pins excluding display outputs  
mA Total for all display outputs  
High level total output  
current  
120  
IODH  
Pins excluding large current output  
(value per pin)  
15  
IOL  
mA  
Low level output current  
20  
100  
IOLC  
IOL  
Topr  
Tstg  
PD  
mA Large current output pins 4 (value per pin)  
Low level total output current  
Operating temperature  
Storage temperature  
Allowable power dissipation  
1
mA Total for all output pins  
20 to +75  
55 to +150  
600  
°C  
°C  
mW  
VIN, VOUT and VOD must not exceed VDD + 0.3V.  
2
3
4
VFDP and VOD must not exceed VDD 40V.  
Specifies output current of general-purpose I/O ports.  
The large current drive transistor is the N-CH transistor of Port C (PC).  
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be  
conducted under the recommended operating conditions. Exceeding these conditions may adversely affect  
the reliability of the LSI.  
11 –  
CXP820P60  
Recommended Operating Conditions  
(Vss = 0V reference)  
Item  
Symbol  
Min.  
4.5  
Max.  
5.5  
Unit  
V
Remarks  
Guaranteed operation range during  
1/2, 1/4 frequency dividing clock modes  
Guaranteed operation range during  
1/16 frequency dividing clock or sleep  
modes  
3.5  
2.7  
5.5  
5.5  
V
V
VDD  
Supply voltage  
Guaranteed operation range with TEX  
clock  
5.5  
VDD  
VDD  
VDD  
V
V
2.5  
Guaranteed data hold range during stop  
1
0.7VDD  
0.8VDD  
0.7VDD  
VIH  
2
3
V
VIHS  
VIHH  
VIHEX  
VIL  
High level input  
voltage  
V
4
V
VDD 0.4 VDD + 0.3  
EXTAL  
1
2
3
0.3VDD  
0.2VDD  
0.7  
V
0
0
V
VILS  
VILH  
VILEX  
Topr  
Low level input  
voltage  
V
0
4
0.4  
V
0.3  
20  
EXTAL  
+75  
°C  
Operating temperature  
1
Value for each pin of normal input port (PA, PB0, PB4, PB7, PC).  
Value of the following pins:  
2
RST, CINT, CS0/RxD, SI0, SI1, SCK0, SCK1, EC0/INT0, EC1/INT1, INT2, INT3/NMI, RMC.  
Value for each pin (PD, PF).  
3
4
Specifies only during external clock input.  
12 –  
CXP820P60  
Electrical Characteristics  
DC Characteristics  
(Ta = 20 to +75°C, VSS = 0V reference)  
Item  
Symbol  
Pins  
Conditions  
Min.  
4.0  
Typ.  
Max.  
Unit  
V
VDD = 4.5V, IOH = 0.5mA  
VDD = 4.5V, IOH = 1.2mA  
VDD = 4.5V, IOL = 1.8mA  
VDD = 4.5V, IOL = 3.6mA  
VDD = 4.5V, IOL = 12.0mA  
VDD = 5.5V, VIH = 5.5V  
VDD = 5.5V, VIL = 0.4V  
VDD = 5.5V, VIL = 5.5V  
VDD = 5.5V, VIL = 0.4V  
High level  
output current  
PA to PD, PE6,  
PE7, PF to PH  
VOH  
3.5  
V
0.4  
0.6  
V
PA to PC,  
PE6, PE7  
Low level  
output current  
V
VOL  
PC  
1.5  
V
0.5  
0.5  
0.1  
40  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
mA  
IIHE  
IILE  
IIHT  
IILT  
IILR  
EXTAL  
40  
10  
TEX  
RST  
0.1  
1.5  
10  
400  
50  
Input current  
VDD = 5.5V, VIL = 0.4V  
VDD = 4.5V, VIL = 4.0V  
1
IIL  
PA to PC  
3.3  
8  
A20 to A55  
VDD = 4.5V  
VOH = VDD 2.5V  
Display output  
current  
G0/A0 to  
G15/A15,  
A16 to A19  
IOH  
30  
mA  
µA  
kΩ  
µA  
Open drain  
G0/A0 to  
G15/A15,  
A16 to A55  
VDD = 5.5V  
VOL = VDD 35V  
VFDP = VDD 35V  
output leakage  
current (P-CH  
Tr off state)  
ILOL  
RL  
IIZ  
20  
220  
±10  
G0/A0 to  
G15/A15,  
A16 to A23  
Pull-down  
resistance  
VDD = 5V  
VOD VFDP = 30V  
30  
70  
1
PA to PC ,  
2
I/O leakage  
current  
PD ,  
VDD = 5.5V  
VI = 0, 5.5V  
PE0 to PE5,  
2
PF , PI  
13 –  
CXP820P60  
Item  
Symbol  
IDD1  
Pins  
Conditions  
Min.  
Typ.  
27  
Max.  
Unit  
mA  
1/2 frequency dividing clock mode  
operation  
55  
VDD = 5.5V, 16MHz crystal  
oscillation (C1 = C2 = 15pF)  
VDD = 3V, 32kHz crystal  
oscillation (C1 = C2 = 47pF)  
35  
1.5  
15  
110  
8
µA  
IDD2  
Supply  
current  
Sleep mode  
VDD  
3
IDDS1  
mA  
VDD = 5.5V, 16MHz crystal  
oscillation (C1 = C2 = 15pF)  
VDD = 3V, 32kHz crystal  
oscillation (C1 = C2 = 47pF)  
IDDS2  
IDDS3  
30  
10  
µA  
µA  
Stop mode  
VDD = 5.5V, termination of 16MHz  
and 32kHz oscillation  
PA to PC,  
2
PD ,  
Clock 1MHz  
0V for all pins excluding  
measured pins  
Input  
capacity  
PE0 to PE5,  
10  
pF  
20  
CIN  
2
PF , PI,  
EXTAL,  
RST  
1
PA to PC pins specify the input current when pull-up resistor has been selected; leakage current when no  
resistor has been selected.  
2
3
PD and PF pins specify when they are used as input pins by program.  
When all pins are open.  
14 –  
CXP820P60  
AC Characteristics  
(1) Clock timing  
(Ta = 20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)  
Item  
Symbol  
Pin  
Conditions  
Fig. 1, Fig. 2  
Min.  
1
Typ.  
Max. Unit  
XTAL  
EXTAL  
16  
200  
20  
System clock frequency  
fC  
MHz  
ns  
Fig. 1, Fig. 2  
External clock drive  
t
t
XL  
28  
System clock input pulse width  
EXTAL  
EXTAL  
XH  
Fig. 1, Fig. 2  
External clock drive  
System clock input rise time,  
fall time  
t
t
CR  
CF  
1
tsys + 50  
ns  
Event count input clock  
pulse width  
t
t
EH  
EL  
EC0,  
EC1  
Fig. 3  
Fig. 3  
ns  
Event count input clock  
rise time, fall time  
t
t
ER  
EF  
EC0,  
EC1  
ms  
VDD = 2.7 to 5.5V  
Fig. 2 (32kHz clock  
applied condition)  
TEX  
TX  
32.768  
System clock frequency  
fC  
kHz  
t
t
TL  
Fig. 3  
Fig. 3  
10  
Event count input pulse width  
TEX  
TEX  
µs  
TH  
Event count input rise time,  
fall time  
t
t
TR  
TF  
20  
ms  
1
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control  
clock register (CLC: 00FEh).  
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")  
1/fc  
VDD 0.4V  
EXTAL  
0.4V  
tXH  
tCF  
tXL  
tCR  
Fig. 1. Clock timing  
Crystal oscillation  
Ceramic oscillation  
32kHz clock applied condition  
Crystal oscillation  
External clock  
EXTAL  
XTAL  
EXTAL  
XTAL  
TEX  
TX  
C1  
C2  
74HC04  
C1  
C2  
Fig. 2. Clock applied conditions  
0.8VDD  
0.2VDD  
TEX  
EC0  
EC1  
tEH  
tTH  
tEF  
tTF  
tEL  
tTL  
tER  
tTR  
Fig. 3. Event count clock timing  
15 –  
CXP820P60  
(2) Serial transfer (CH0)  
(Ta = 20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)  
Item  
Symbol  
Pin  
Condition  
Min.  
Max.  
Unit  
ns  
CS0 ↓ → SCK0  
Chip select transfer mode  
(SCK0 = output mode)  
tsys + 200  
t
t
t
DCSK  
DCSKF  
DCSO  
SCK0  
delay time  
CS0 ↑ → SCK0  
float delay time  
Chip select transfer mode  
(SCK0 = output mode)  
ns  
ns  
ns  
tsys + 200  
tsys + 200  
tsys + 200  
SCK0  
SO0  
CS0 ↓ → SO0  
Chip select transfer mode  
Chip select transfer mode  
delay time  
CS0 ↑ → SO0  
float delay time  
t
t
DCSOF  
WHCS  
SO0  
CS0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CS0 High level width  
Chip select transfer mode  
Input mode  
tsys + 200  
2tsys + 200  
16000/fc  
tsys + 100  
8000/fc 50  
100  
SCK0 cycle time  
t
KCY  
SCK0  
SCK0  
SI0  
Output mode  
Input mode  
t
t
KH  
KL  
SCK0 High, Low level width  
Output mode  
SCK0 input mode  
SCK0 output mode  
SCK0 input mode  
SCK0 output mode  
SCK0 input mode  
SCK0 output mode  
SI0 input setup time  
t
t
t
SIK  
(for SCK0 )  
200  
tsys + 200  
100  
SI0 input hold time  
KSI  
SI0  
(for SCK0 )  
tsys + 200  
100  
SCK0 ↓ → SO0  
KSO  
SO0  
delay time  
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the  
control clock register (CLC: 00FEh).  
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")  
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.  
16 –  
CXP820P60  
tWHCS  
CS0  
0.8VDD  
0.2VDD  
tKCY  
tDCSK  
tDCSKF  
tKL  
tKH  
0.8VDD  
0.8VDD  
0.2VDD  
SCK0  
tSIK tKSI  
0.8VDD  
0.2VDD  
SI0  
Input data  
tDCSO  
tKSO  
tDCSOF  
0.8VDD  
Output data  
SO0  
0.2VDD  
Fig. 4. Serial transfer CH0 timing  
17 –  
CXP820P60  
Serial transfer (CH1)  
(Ta = 20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)  
Item  
Symbol  
Pin  
Condition  
Input mode  
Min.  
1000  
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
SCK1 cycle time  
SCK1  
t
KCY  
Ouput mode  
16000/fc  
400  
Input mode  
SCK1  
t
t
KH  
KL  
SCK1  
SI1  
High, Low level width  
Ouput mode  
8000/fc 50  
100  
SCK1 input mode  
SCK1 ouput mode  
SCK1 input mode  
SCK1 ouput mode  
SCK1 input mode  
SCK1 ouput mode  
SI1 input setup time  
(for SCK1 )  
t
t
t
SIK  
200  
200  
SI1 input hold time  
(for SCK1 )  
SI1  
KSI  
100  
200  
100  
SCK1 ↓ → SO1 delay time  
SO1  
KSO  
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.  
tKCY  
tKL  
tKH  
0.8VDD  
0.2VDD  
SCK1  
tSIK  
tKSI  
0.8VDD  
0.2VDD  
SI1  
Input data  
tKSO  
0.8VDD  
SO1  
Output dat  
0.2VDD  
Fig. 5. Serial transfer CH1 timing  
18 –  
CXP820P60  
(3) A/D converter characteristics  
(Ta = 20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)  
Item  
Resolution  
Symbol  
Pin  
Condition  
Min.  
Typ.  
Max.  
8
Unit  
Bits  
LSB  
±3  
Linearity error  
Ta = 25°C  
VDD = 5.0V  
VSS = 0V  
Zero transition  
voltage  
1
VZT  
10  
10  
70  
mV  
mV  
Full-scale  
transition voltage  
2
VFT  
4910  
4970  
5030  
3
26/fADC  
6/fADC  
0
µs  
µs  
V
Conversion time  
Sampling time  
t
CONV  
SAMP  
3
t
AN0 to AN7  
VDD  
Analog input voltage VIAN  
FFh  
FEh  
1
VZT: Value at which the digital conversion value changes  
from 00h to 01h and vice versa.  
2
3
VFT: Value at which the digital conversion value changes  
from FEh to FFh and vice versa.  
fADC indicates the below values due to the contents of bit 6  
(CKS) of the A/D control register (ADC: 00F9h) and bits 7  
(PCK1) and 6 (PCK0) of the clock control register (CLC:  
00FEh).  
Linearity error  
01h  
00h  
However, the selection for fADC = fC (CKS = "0") is limited in  
the clock range of fC = 1 to 14MHz (VDD = 4.5 to 5.5V).  
VZT  
VFT  
Analog input  
Fig. 6. Definition of A/D converter terms  
19 –  
CXP820P60  
(4) Interruption, reset input  
(Ta = 20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)  
Item  
Symbol  
Pin  
INT0  
Condition  
Min.  
Max.  
Unit  
External interruption  
High, Low level width  
t
t
IH  
IL  
INT1  
INT2  
NMI/INT3  
1
µs  
Reset input Low level width  
32/fc  
µs  
t
RSL  
RST  
tIH  
tIL  
0.8VDD  
INT0  
0.2VDD  
INT1  
tIL  
tIH  
INT2  
NMI/INT3  
(NMI specifies only for the  
falling edge.)  
Fig. 7. Interruption input timing  
tRSL  
RST  
0.2VDD  
Fig. 8. RST input timing  
20 –  
CXP820P60  
Appendix  
(i) Main clock  
EXTAL  
(ii) Main clock  
EXTAL  
(iii) Sub clock  
TEX
XTAL  
Rd  
XTAL  
Rd  
TX
Rd  
C1  
C2  
C1  
C2  
C1 C2  
Fig. 9. Recommended oscillation circuit  
Circuit  
example  
Manufacturer  
fc (MHz)  
C1 (pF)  
C2 (pF)  
Model  
Rd ()  
Remarks  
CSA10.0MTZ  
10.0  
12.0  
16.0  
10.0  
12.0  
16.0  
8.0  
30  
5
30  
5
(i)  
CSA12.0MTZ  
MURATA  
MFG  
CO., LTD.  
CSA16.00MXZ040  
CST10.0MTW  
CST12.0MTW  
CST16.00MXW0C1  
0
30  
30  
(ii)  
5
18  
5
18  
RIVER ELETEC  
CO., LTD  
330  
HC-49/U03  
12.0  
16.0  
8.0  
12  
12  
10  
10  
(i)  
10  
10  
KINSEKI  
LTD.  
0
HC-49/U (-S)  
12.0  
16.0  
5
5
Open  
Open  
VTC-200  
SP-T  
Seiko Instruments  
Inc.  
CL = 12.5pF  
32.768kHz  
330k  
(iii)  
18  
18  
Models marked with an asterisk ( ) have the built-in ground capacitance (C1, C2).  
Mask Option Table  
Item  
Mask ROM  
100-pin plastic QFP  
52K/60K byte  
CXP820P60Q-1-  
Package  
100-pin plastic QFP  
PROM 60K byte  
Existent  
ROM capacitance  
Reset pin pull-up resistor  
Existent/Non-existent  
High voltage drive pin  
pull-down resistor  
Non-existent (PH7/A24 to PD0/A55)  
Existent (G0/A0 to A23)  
Existent/Non-existent  
21 –  
CXP820P60  
Characteristics Curve  
IDD vs. VDD  
IDD vs. fc  
100  
25  
20  
15  
1/2 dividing mode  
1/2 dividing mode  
1/4 dividing mode  
10  
1/16 dividing mode  
Sleep mode  
1
1/4 dividing mode  
10  
5
0.1  
32kHz mode  
1/16 dividing mode  
32kHz  
Sleep mode  
Sleep mode  
20  
0.01  
0
3
0
1
2
4
5
6
7
0
5
10  
15  
VDD Supply voltage [V]  
fc System clock [MHz]  
22 –  
CXP820P60  
Package Outline  
Unit: mm  
100PIN QFP (PLASTIC)  
23.9 ± 0.4  
+ 0.1  
0.15 0.05  
+ 0.4  
20.0 0.1  
80  
51  
50  
81  
A
31  
100  
1
30  
+ 0.15  
0.65  
+ 0.35  
2.75 0.15  
0.3 0.1  
0.13  
0.15  
M
+ 0.2  
0.1 0.05  
0˚ to 10˚  
DETAIL  
A
PACKAGE STRUCTURE  
PACKAGE MATERIAL  
LEAD TREATMENT  
EPOXY RESIN  
SOLDER PLATING  
QFP-100P-L01  
QFP100-P-1420  
SONY CODE  
EIAJ CODE  
LEAD MATERIAL  
PACKAGE MASS  
42/COPPER ALLOY  
1.7g  
JEDEC CODE  
100PIN QFP (PLASTIC)  
23.9 ± 0.4  
+ 0.1  
0.15 0.05  
+ 0.4  
20.0 0.1  
80  
51  
50  
81  
A
31  
100  
1
30  
+ 0.15  
0.65  
+ 0.35  
2.75 0.15  
0.3 0.1  
0.13  
0.15  
M
+ 0.2  
0.1 0.05  
0˚ to 10˚  
DETAIL  
A
PACKAGE STRUCTURE  
PACKAGE MATERIAL  
LEAD TREATMENT  
EPOXY RESIN  
SOLDER PLATING  
QFP-100P-L01  
QFP100-P-1420  
SONY CODE  
EIAJ CODE  
LEAD MATERIAL  
PACKAGE MASS  
42/COPPER ALLOY  
1.7g  
JEDEC CODE  
LEAD PLATING SPECIFICATIONS  
ITEM  
SPEC.  
42 ALLOY  
LEAD MATERIAL  
SOLDER COMPOSITION  
PLATING THICKNESS  
Sn-Bi Bi:1-4wt%  
5-18µm  
Sony Corporation  
23 –  
配单直通车
CXP820P60Q-1产品参数
型号:CXP820P60Q-1
是否Rohs认证: 不符合
生命周期:Active
IHS 制造商:SONY CORP
包装说明:QFP, QFP100,.7X.9
Reach Compliance Code:unknown
风险等级:5.84
具有ADC:YES
地址总线宽度:
位大小:8
CPU系列:SPC700
最大时钟频率:16 MHz
DAC 通道:NO
DMA 通道:NO
外部数据总线宽度:
JESD-30 代码:R-PQFP-G100
JESD-609代码:e0
长度:20 mm
I/O 线路数量:68
端子数量:100
最高工作温度:70 °C
最低工作温度:-20 °C
PWM 通道:YES
封装主体材料:PLASTIC/EPOXY
封装代码:QFP
封装等效代码:QFP100,.7X.9
封装形状:RECTANGULAR
封装形式:FLATPACK
电源:3/5 V
认证状态:Not Qualified
RAM(字节):3984
ROM(单词):61440
ROM可编程性:UVPROM
速度:16 MHz
子类别:Microcontrollers
最大压摆率:55 mA
最大供电电压:5.5 V
最小供电电压:4.5 V
标称供电电压:5 V
表面贴装:YES
技术:CMOS
温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING
端子节距:0.65 mm
端子位置:QUAD
宽度:14 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1
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