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产品型号CY7C1061AV33-12ZXC的概述

芯片CY7C1061AV33-12ZXC的概述 CY7C1061AV33-12ZXC是一款由赛普拉斯（Cypress Semiconductor）公司生产的高性能静态随机存取存储器（SRAM）。该芯片以高速度、高带宽和低功耗为特点，适合在多个应用中使用，包括网络设备、通信系统、工业控制、图像处理等。CY7C1061AV33-12ZXC属于赛普拉斯的高性能SRAM系列，具有完善的功能和可靠性。 SRAM是一种易失性存储器，与动态随机存取存储器（DRAM）相比，SRAM在数据存储和读取方面通常提供更快的速度，且不需要定期刷新。CY7C1061AV33-12ZXC的设计目标是提供高速度和高可靠性，同时满足电子设备对低功耗的要求。芯片CY7C1061AV33-12ZXC的详细参数 - 类型: SRAM - 容量: 1 Mbit - 数据位宽: 1-bit - 工作电压: 3.3 V - 最大...

产品型号CY7C1061AV33-12ZXC的Datasheet PDF文件预览

CY7C1061AV33

16-Mbit (1M x 16) Static RAM

Features

Functional Description

• High speed

The CY7C1061AV33 is a high performance CMOS Static RAM

organized as 1,048,576 words by 16 bits.

— t_AA= 10 ns

To write to the device, enable the chip (CE₁LOW and CE₂

HIGH) while forcing the Write Enable (WE) input LOW. If Byte

Low Enable (BLE) is LOW, then data from IO pins (IO₀through

IO₇), is written into the location specified on the address pins

(A₀through A₁₉). If Byte High Enable (BHE) is LOW, then data

from IO pins (IO₈through IO₁₅) is written into the location

specified on the address pins (A₀through A₁₉).

• Low active power

— 990 mW (max)

• Operating voltages of 3.3 ± 0.3V

• 2.0V data retention

• Automatic power down when deselected

• TTL compatible inputs and outputs

• Easy memory expansion with CE₁and CE₂features

To read from the device, enable the chip by taking CE₁LOW

and CE₂HIGH while forcing the Output Enable (OE) LOW and

the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is

LOW, then data from the memory location specified by the

address pins will appear on IO₀to IO₇. If Byte High Enable

(BHE) is LOW, then data from memory will appear on IO₈to

IO₁₅. See “Truth Table” on page 7 for a complete description

of Read and Write modes.

• Available in Pb-free and non Pb-free 54-pin TSOP II

package and non Pb-free 60-ball fine pitch ball grid array

(FBGA) package

The input/output pins (IO₀through IO₁₅) are placed in a

high-impedance state when the device is deselected (CE₁

HIGH/CE₂LOW), the outputs are disabled (OE HIGH), the

BHE and BLE are disabled (BHE, BLE HIGH), or a Write

operation is in progress (CE₁LOW, CE₂HIGH, and WE LOW).

Logic Block Diagram

INPUT BUFFER

IO₀–IO₇

1M x 16

ARRAY

IO₈–IO₁₅

COLUMN

DECODER

BHE

CE₂

CE₁

BLE

Cypress Semiconductor Corporation

Document #: 38-05256 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 26, 2007

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CY7C1061AV33

Selection Guide

–10

–12

Unit

Maximum Access Time

Maximum Operating Current

Commercial

275

260

Industrial

Maximum CMOS Standby Current

Commercial/Industrial

Pin Configurations ^{[1, 2]}

60-ball FBGA

Top View

54-pin TSOP II

(Top View)

49 IO

CE₂

BLE

BHE

CE₁IO

BHE

CE₁13

DNU

BLE

CE₂

A₁₇

DNU

28 IO

Notes

1. NC pins are not connected on the die.

2. DNU (Do Not Use) pins have to be left floating or tied to VSS to ensure proper operation.

Document #: 38-05256 Rev. *G

Page 2 of 10

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CY7C1061AV33

DC Input Voltage ^[3]............................... –0.5V to V_CC+ 0.5V

Current into Outputs (LOW)......................................... 20 mA

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. These user guidelines are not tested.

Operating Range

Storage Temperature .................................–65°C to +150°C

Ambient

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V_CCto Relative GND ^[3]... –0.5V to +4.6V

Range

V_CC

Temperature

0°C to +70°C

–40°C to +85°C

Commercial

Industrial

3.3V ± 0.3V

DC Voltage Applied to Outputs

in High-Z State ^[3]...................................–0.5V to V_CC+ 0.5V

DC Electrical Characteristics (Over the Operating Range)

–10

–12

Parameter

Description

Test Conditions

Unit

Min

Max

Min

Max

V_OH

V_OL

V_IH

V_IL

I_IX

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage ^[3]

I_OH= –4.0 mA

I_OL= 8.0 mA

2.4

0.4

2.0

V_CC+ 0.3

0.8

2.0

–0.3

–1

V_CC+ 0.3

0.8

–0.3

–1

Input Leakage Current GND < V_I< V_CC

µA

I_OZ

I_CC

Output Leakage Current GND < V_O< V_CC, Output Disabled

–1

V_CCOperating

Supply Current

V_CC= max,

f = f_max= 1/t_RC

Commercial

Industrial

275

260

I_SB1

Automatic CE

Power-down Current

—TTL Inputs

CE₂<= V_IL,max V_CC, CE > V_IH

V_IN> V_IHor

_IN< V_IL, f = f_max

CE₂<= 0.3V

max V_CC

I_SB2

Automatic CE

Power-down Current

—CMOS Inputs

Commercial/

Industrial

CE > V_CC– 0.3V,

V_IN> V_CC– 0.3V,

or V_IN< 0.3V, f = 0

Capacitance ^[4]

Parameter

Description

Test Conditions

T_A= 25°C, f = 1 MHz, V_CC= 3.3V

TSOP II

FBGA

Unit

C_IN

Input Capacitance

IO Capacitance

C_OUT

AC Test Loads and Waveforms ^[5]

50Ω

R1 317

Ω

= 1.5V

OUTPUT

V_TH

3.3V

Z = 50Ω

OUTPUT

30 pF* * Capacitive Load consists of all com-

ponents of the test environment.

351Ω

5 pF*

(a)

INCLUDING

JIG AND

SCOPE

ALL INPUT PULSES

3.3V

(b)

90%

10%

90%

10%

GND

Fall time:

> 1V/ns

Rise time > 1V/ns

(c)

Notes

4. Tested initially and after any design or process changes that may affect these parameters.

5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0V). As soon as 1 ms (T

(min) = –2.0V for pulse durations of less than 20 ns.

) after reaching the

power

minimum operating V , normal SRAM operation can begin including reduction in V to the data retention (V , 2.0V) voltage.

CCDR

Document #: 38-05256 Rev. *G

Page 3 of 10

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CY7C1061AV33

AC Switching Characteristics (Over the Operating Range) ^[6]

–10

–12

Parameter

Description

Unit

Min

Max

Min

Max

Read Cycle

t_power

t_RC

V_CC(typical) to the first access ^[7]

Read Cycle Time

t_AA

Address to Data Valid

t_OHA

t_ACE

Data Hold from Address Change

CE₁LOW/CE₂HIGH to Data Valid

OE LOW to Data Valid

t_DOE

t_LZOE

t_HZOE

t_LZCE

t_HZCE

t_PU

OE LOW to Low-Z

OE HIGH to High-Z ^[8]

CE₁LOW/CE₂HIGH to Low-Z ^[8]

CE₁HIGH/CE₂LOW to High-Z ^[8]

CE₁LOW/CE₂HIGH to Power Up ^[9]

CE₁HIGH/CE₂LOW to Power Down ^[9]

Byte Enable to Data Valid

Byte Enable to Low-Z

t_PD

t_DBE

t_LZBE

t_HZBE

Write Cycle ^{[10, 11]}

t_WC

Byte Disable to High-Z

Write Cycle Time

t_SCE

CE₁LOW/CE₂HIGH to Write End

Address Setup to Write End

Address Hold from Write End

Address Setup to Write Start

WE Pulse Width

t_AW

t_HA

t_SA

t_PWE

t_SD

Data Setup to Write End

Data Hold from Write End

WE HIGH to Low-Z ^[8]

5.5

t_HD

t_LZWE

t_HZWE

t_BW

WE LOW to High-Z ^[8]

Byte Enable to End of Write

Notes

6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

[5]

/I and specified transmission line loads. Test conditions for the Read cycle use output loading shown in (a) of the “AC Test Loads and Waveforms ” on

OL OH

page 3, unless specified otherwise.

7. This part has a voltage regulator that steps down the voltage from 3V to 2V internally. t

time must be provided initially before a Read/Write operation is started.

power

[5]

, t

and t

, t

are specified with a load capacitance of 5 pF as in (b) of “AC Test Loads and Waveforms ” on page 3.

HZOE HZCE HZWE HZBE

LZOE LZCE \LZWE LZBE

Transition is measured ±200 mV from steady-state voltage.

9. These parameters are guaranteed by design and are not tested.

10. The internal Write time of the memory is defined by the overlap of CE LOW (CE HIGH) and WE LOW. Chip enables must be active and WE and byte enables

must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data setup and hold timing should be referenced to

the leading edge of the signal that terminates the Write.

11. The minimum Write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of t

and t

HZWE

Document #: 38-05256 Rev. *G

Page 4 of 10

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CY7C1061AV33

Data Retention Waveform

DATA RETENTION MODE

> 2V

3.0V

CDR

Switching Waveforms

Read Cycle No. 1 (Address Transition Controlled) ^{[12, 13]}

ADDRESS

OHA

DATA OUT

PREVIOUS DATA VALID

DATA VALID

Read Cycle No. 2 (OE Controlled) ^{[13, 14]}

ADDRESS

CE₁

t_RC

t_PD

HZCE

CE₂

t_ACE

BHE/BLE

t_DBE

t_HZBE

t_LZBE

t_HZOE

t_DOE

t_LZOE

HIGH

IMPEDANCE

HIGH IMPEDANCE

DATA OUT

DATA VALID

t_LZCE

I_CC

I_SB

t_PU

V_CC

SUPPLY

CURRENT

50%

Notes

12. Device is continuously selected. OE, CE, BHE or BHE, or both = V . CE2 = V

13. WE is HIGH for Read cycle.

14. Address valid prior to or coincident with CE transition LOW and CE transition HIGH.

Document #: 38-05256 Rev. *G

Page 5 of 10

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CY7C1061AV33

Switching Waveforms (continued)

Write Cycle No. 1 (CE₁or CE₂Controlled) ^{[15, 16]}

t_WC

ADDRESS

CE₁

t_SCE

CE₂

t_SA

t_AW

t_HA

t_PWE

BHE/BLE

t_BW

t_HD

t_SD

VALID DATA

DATA IO

NOTE 17

t_HZOE

Write Cycle No. 2 (WE Controlled, OE LOW) ^{[15, 16]}

t_WC

ADDRESS

CE₁

t_SCE

CE₂

t_BW

BHE/BLE

t_AW

t_HA

t_SA

t_PWE

t_SD

VALID DATA

t_HD

NOTE 17

DATA IO

t_LZWE

t_HZWE

Notes

15. Data IO is high impedance if OE, or BHE or BLE or both = V

16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.

17. During this period, the IOs are in output state and input signals should not be applied.

Document #: 38-05256 Rev. *G

Page 6 of 10

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CY7C1061AV33

Switching Waveforms (continued)

Write Cycle No. 3 (BHE/BLE Controlled)

t_WC

ADDRESS

CE₁

CE₂

t_SCE

t_AW

t_HA

t_BW

BHE/BLE

t_SA

t_PWE

t_SD

t_HD

NOTE 17

DATA IO

VALID DATA

Truth Table

CE₁CE₂OE WE BLE

BHE

IO₀–IO₇

High-Z

IO₈–IO₁₅

High-Z

Mode

Power

Standby (I_SB

Power Down

Read All Bits

)

High-Z

Data Out

High-Z

Data In

High-Z

Data Out

High-Z

Active (I_CC

)

Read Lower Bits Only

Read Upper Bits Only

Write All Bits

Data Out

Data In

High-Z

Write Lower Bits Only

Write Upper Bits Only

Selected, Outputs Disabled

Data In

High-Z

Document #: 38-05256 Rev. *G

Page 7 of 10

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CY7C1061AV33

Ordering Information

Speed

(ns)

Package

Diagram

Ordering Code

Package Type

Operating Range

CY7C1061AV33-10ZXC

CY7C1061AV33-10BAC

CY7C1061AV33-10ZI

CY7C1061AV33-10ZXI

CY7C1061AV33-10BAXI

CY7C1061AV33-12ZC

CY7C1061AV33-12ZXC

CY7C1061AV33-12BAC

CY7C1061AV33-12ZXI

51-85160

51-85162

51-85160

54-pin TSOP II (Pb-free)

60-ball FBGA

Commercial

54-pin TSOP II

Industrial

Commercial

Industrial

54-pin TSOP II (Pb-free)

60-ball FBGA (Pb-free)

54-pin TSOP II

51-85162

51-85160

54-pin TSOP II (Pb-free)

60-ball FBGA

51-85162

51-85160

54-pin TSOP II (Pb-free)

Contact local Cypress representative for availability of the these parts.

Package Diagrams

Figure 1. 54-pin TSOP II, 51-85160

51-85160-**

Document #: 38-05256 Rev. *G

Page 8 of 10

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CY7C1061AV33

Package Diagrams (continued)

Figure 2. 60-ball FBGA (8 x 20 x 1.2 mm), 51-85162

TOP VIEW

A1 CORNER

BOTTOM VIEW

(

A1 CORNER

(

DUMMY BALL ꢀ0.3X 812

Ø0.05 M C

Ø0.25 M C A B

Ø0.30 0.05ꢀ(48X

DIMENSIONS IN MM

PART #

STANDARD PKG.

LEAD FREE PKG.

BA60A

BK60A

1.475

4.00 0.10

0.75

1.00

PKG WEIGHT: 0.30 gms

3.75

6.00

4.00 0.10

0.15ꢀ(8X

SEATING PLANE

51-85162-*D

All products and company names mentioned in this document may be the trademarks of their respective holders.

Document #: 38-05256 Rev. *G

Page 9 of 10

use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to

be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C1061AV33

Document History Page

Document Title: CY7C1061AV33 16-Mbit (1M x 16) Static RAM

Document Number: 38-05256

Issue

Date

Orig. of

Change

REV.

ECN NO.

Description of Change

113725

117058

117989

03/28/02

07/31/02

08/30/02

NSL

DFP

New Data Sheet

Removed 15-ns bin

Added 8-ns bin

Changed Icc for 8, 10, 12 bins

_powerchanged from 1 µs to 1 ms.

Load Cap Comment changed (for Tx line load)

t_SDchanged to 5.5 ns for the 10-ns bin

Changed some 8-ns bin numbers (t_HZ, t_DOE, t_DBE

)

Removed hz<lz comments from data sheet

120383

11/06/02

DFP

Final data sheet

Added note 3 to “AC Test Loads and Waveforms” and note 7 to t_puand t_pd

Updated Input/Output Caps (for 48BGA only) to 8 pF/10 pF and for the

54-pin TSOP to 6/8 pF

124439

492137

2/25/03

MEG

NXR

Changed ISB1 from 100 mA to 70 mA

Shaded fBGA production ordering information

See ECN

Corrected Block Diagram on page #1

Removed 8 ns speed bin

Changed 48-Ball FBGA to 60-Ball FBGA in Pin Configuration

Included Note #1 and 2 on page #2

Changed the description of I_IXfrom Input Load Current to Input Leakage

Current in DC Electrical Characteristics table

Updated the Ordering Information Table

508117

877322

See ECN

NXR

VKN

Updated FBGA Pin Configuration

Updated Ordering Information table

Document #: 38-05256 Rev. *G

Page 10 of 10

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CY7C1061AV33-12ZXC相关文章

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CY7C1061AV33-12ZXC产品参数

型号:	CY7C1061AV33-12ZXC
是否Rohs认证：	符合
生命周期：	Obsolete
零件包装代码：	TSOP2
包装说明：	LEAD FREE, TSOP2-54
针数：	54
Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41
风险等级：	7.87
最长访问时间：	12 ns
I/O 类型：	COMMON
JESD-30 代码：	R-PDSO-G54
JESD-609代码：	e3
长度：	22.415 mm
内存密度：	16777216 bit
内存集成电路类型：	STANDARD SRAM
内存宽度：	16
湿度敏感等级：	3
功能数量：	1
端子数量：	54
字数：	1048576 words
字数代码：	1000000
工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C
最低工作温度：
组织：	1MX16
输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2
封装等效代码：	TSOP54,.46,32
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE
并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260
电源：	3.3 V
认证状态：	Not Qualified
座面最大高度：	1.2 mm
最大待机电流：	0.05 A
最小待机电流：	3 V
子类别：	SRAMs
最大压摆率：	0.275 mA
最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES
技术：	CMOS
温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子节距：	0.8 mm
端子位置：	DUAL
处于峰值回流温度下的最长时间：	20
宽度：	10.16 mm
Base Number Matches：	1

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