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    • BA7078AS图

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    • BA7078AS
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    • BA7078AS
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    产品型号BA7078AS的Datasheet PDF文件预览

    BA7078AF/AS  
    Multimedia ICs  
    Synchronization signal processor for  
    high definition displays  
    BA7078AF/AS  
    The BA7078AF is a synchronization signal processing LSI chip designed for multiscan high-definition displays. It  
    generates a synchronization signal and clamp pulse for three types of input signals: separate synchronization, composite  
    synchronization, and synchronization on video.  
    !Application  
    CRT displays  
    !Features  
    1) Operates on a single 5V power supply, with low power consumption.  
    2) Synchronization signal existence and polarity detec-tion output.  
    3) Adjustable clamp pulse width, allowing for the selec-tion of front or back editing.  
    4) Vertical synchronization separation is based on hori-zontal frequency tracking, for separation starting at 1H.  
    5) Minimal attached components.  
    !Absolute maximum ratings (Ta = 25°C)  
    Parameter  
    Symbol  
    Limits  
    7.0  
    Unit  
    V
    Power supply voltage  
    VCC  
    1 450(BA7078AF)  
    2 600(BA7078AS)  
    −25 to +75  
    ∗
    Power dissipation  
    Pd  
    mW  
    ∗
    Topr  
    Tstg  
    °C  
    °C  
    Operating temperature  
    Storage temperature  
    −55 to +125  
    1 Reduced by 4.5mW for each increase in Ta of 1°C over 25°C.  
    ∗
    2 Reduced by 6.0mW for each increase in Ta of 1°C over 25°C.  
    ∗
    !Recommended operating conditions (Ta = 25°C)  
    Parameter  
    Symbol Min.  
    Typ.  
    Max.  
    Unit  
    V
    VCC  
    4.5  
    5.0  
    5.5  
    Power supply voltage  
    1/12  
    BA7078AF/AS  
    Multimedia ICs  
    !Block diagram  
    1
    2
    3
    18  
    17  
    16  
    HSCTL  
    POLH  
    EXIH  
    H
    SYNC DET.  
    C / HSYNC IN  
    VIDEO IN  
    POLV  
    SYNC SEPA.  
    15  
    14  
    4
    5
    VSEPA  
    EXIV  
    Vcc  
    HOR. SYNC  
    CONTROL  
    V
    SYNC SEPA.  
    VSYNC IN  
    6
    CVPOL  
    13  
    12  
    11  
    HDRV  
    V
    SYNC DET.  
    7
    8
    CVEXI  
    CPSEL  
    CLAMP  
    VDRV  
    CLAMP PULSE GEN.  
    10  
    9
    GND  
    CPWID  
    2/12  
    BA7078AF/AS  
    Multimedia ICs  
    !Pin descriptions  
    Pin No.  
    Pin name  
    Functions  
    Used to select whether to output the VDRV section of the HDRV output  
    signal.  
    High : VDRV section of HDRV is output  
    Low : VDRV section of HDRV is not output  
    1
    HSCTL  
    HDRV output  
    Input either the composite synchronization signal or the horizontal  
    synchronization signal. Input is clamped, and is initiated by capacitor  
    coupling.  
    Composite sync / H SYNC  
    input  
    2
    3
    C / HSYNC IN  
    VIDEO IN  
    Inputs the SYNC ON VIDEO signal(green).  
    Input is sink chip clamped. Input is initiated by capacitor coupling.  
    SYNC ON VIDEO input  
    f-V conversion  
    Converts the horizontal synchronization signal frequency into a voltage.  
    The voltage generated is proportional to the frequency of the horizontal  
    synchronization signal. Attach a 0.56µF capacitor between the ground  
    pins.  
    4
    VSEPA  
    5
    6
    VSYNC IN V SYNC input  
    Inputs the vertical synchronization signal.  
    Integrates the vertical synchronization signal polarity detection circuit.  
    Attach a 1.5µF capacitor between this pin and the ground.  
    CVPOL  
    CVEXI  
    Vertical polarity integration  
    Integrates the vertical synchronization signal existence detection circuit.  
    Attach a 1µF capacitor between this pin and the ground.  
    7
    Vertical existence integration  
    Used to set the clamp pulse generation position to either the front or  
    back edge of HSYNC  
    High : The front edge is the generation position  
    8
    CPSEL  
    Setting the clamp position  
    Open : Composite / H SYNC IN  
    VIDEO IN  
    :
    :
    The front edge is the generation position  
    The back edge is the generation position  
    Low : The back edge is the generation position  
    −
    9
    GND  
    Ground  
    Sets the clamp pulse width according to the attached time constant.  
    Attach a resistor between this pin and VCC and, a capacitor between  
    this pin and GND. When R = 3.9kΩ and C = 100pF, pulse width is  
    approximately 400 ns. Set the resistor to register an abnormality at 1kΩ.  
    10  
    CPWID  
    Setting the clamp pulse width  
    Outputs the vertical synchronization signal.  
    The output signal has positive polarity.  
    11  
    12  
    VDRV  
    CLAMP  
    HDRV  
    VDRV output  
    Clamp output  
    Outputs the clamp pulse generated from the vertical synchronization  
    signal. The output signal has a positive polarity.  
    Outputs the clamp pulse generated from the horizontal synchronization  
    signal. The output signal has positive polarity.  
    13  
    14  
    15  
    HDRV output  
    V
    CC  
    Power supply  
    −
    Indecates whether the vertical synchronization signal exists.  
    For the output logic, refer to the separate table.  
    EXIV  
    POLV  
    EXIH  
    POLH  
    Vertical existence output  
    Indicates the polarity of the vertical synchronization signal.  
    For the output logic, refer to the separate table.  
    16  
    17  
    18  
    Vertical polarity output  
    Indicates whether the horizontal synchronization signal exists.  
    For the output logic, refer to the separate table.  
    Horizontal existence output  
    Horizontal polarity output  
    Indicates the polarity of the horizontal synchronization signal.  
    For the output logic, refer to the separate table.  
    3/12  
    BA7078AF/AS  
    Multimedia ICs  
    !Input / output circuits  
    HSCTL  
    VSEPA  
    C / HSYNC IN  
    V
    CC  
    V
    CC  
    V
    CC  
    670Ω  
    60kΩ  
    200Ω  
    1kΩ  
    51kΩ  
    2pin  
    4pin  
    1pin  
    30kΩ  
    10µA  
    CVPOL  
    VSYNC IN  
    VIDEO IN  
    VCC  
    V
    CC  
    VCC  
    2kΩ  
    200Ω  
    200Ω  
    6pin  
    5pin  
    3pin  
    CVEXI  
    CPSEL  
    CPWID  
    VCC  
    V
    CC  
    V
    CC  
    50kΩ  
    1kΩ  
    8pin  
    10pin  
    7pin  
    50kΩ  
    4/12  
    BA7078AF/AS  
    Multimedia ICs  
    GND  
    VDRV  
    CLAMP  
    V
    CC  
    VCC  
    9pin  
    12pin  
    11pin  
    HDRV  
    POLV  
    V
    CC  
    V
    CC  
    VCC  
    V
    CC  
    10kΩ  
    14pin  
    13pin  
    16pin  
    EXIH  
    POLH  
    EXIV  
    VCC  
    V
    CC  
    VCC  
    10kΩ  
    10kΩ  
    10kΩ  
    17pin  
    15pin  
    18pin  
    5/12  
    BA7078AF/AS  
    Multimedia ICs  
    !Electrical characteristics (unless otherwise noted, VCC = 5V, Ta = 25°C)  
    Parameter  
    Symbol  
    Min.  
    Typ.  
    Max.  
    Unit  
    Conditions  
    V
    CC  
    Power supply voltage  
    4.5  
    21  
    4.5  
    −
    5.0  
    30  
    5.0  
    0.2  
    −
    5.5  
    39  
    −
    V
    mA  
    V
    I
    CC  
    Quiescent current  
    V VDH  
    V VDL  
    I VDL  
    VDRV output voltage "H"  
    VDRV output voltage "L"  
    0.5  
    −
    V
    VDRV output current "L"  
    8
    mA  
    ns  
    V
    trdVD  
    VDRV rising delay time  
    −
    280  
    5.0  
    0.2  
    −
    450  
    −
    VSYNC IN  
    V HDH  
    V HDL  
    I HDL  
    HDRV output voltage "H"  
    4.5  
    −
    HDRV output voltage "L"  
    0.5  
    −
    V
    HDRV output current "L"  
    8
    mA  
    ns  
    ns  
    V
    trdHD1  
    trdHD2  
    V CPH  
    V CPL  
    I CPL  
    HDRV rising delay time (1)  
    −
    65  
    95  
    5.0  
    0.2  
    −
    115  
    145  
    −
    C / HSYNC IN  
    VIDEO IN  
    HDRV rising delay time (2)  
    −
    CLAMP output voltage "H"  
    4.5  
    −
    CLAMP output voltage "L"  
    0.5  
    −
    V
    CLAMP output current "L"  
    8
    mA  
    ns  
    ns  
    V
    trdCP1  
    trdCP2  
    V DH  
    CLAMP rising delay time (1)  
    CLAMP rising delay time (2)  
    Synchronization detection output voltage "H"  
    Synchronization detection output voltage "L"  
    Synchronization detection output current "L"  
    Synchronization detection output impedance  
    Minimum synchronization separation level  
    HSCTL "H" level threshold voltage  
    HSCTL "L" level threshold voltage  
    CPSEL "H" level threshold voltage  
    CPSEL "L" level threshold voltage  
    −
    75  
    95  
    5.0  
    0.2  
    −
    125  
    145  
    −
    front edge  
    back edge  
    −
    4.5  
    −
    V DL  
    0.5  
    −
    V
    I DL  
    3
    mA  
    kΩ  
    Z oD  
    7
    10  
    −
    13  
    0.2  
    −
    V SMin.  
    V tHSH  
    V tHSL  
    V tCPH  
    V tCPL  
    −
    VP-P  
    2.5  
    −
    −
    V
    V
    V
    V
    −
    1.5  
    −
    3.8  
    −
    −
    −
    1.2  
    !Synchronization signal detection chart  
    INPUT  
    OUTPUT  
    EXIH  
    H
    Composite / HSYNC  
    VSYNC  
    No signal  
    EXIV  
    L
    POLH  
    POLV  
    L
    L
    L
    L
    H. COMP  
    (Positive)  
    H
    H
    Positive  
    Negative  
    No signal  
    Positive  
    Negative  
    No signal  
    Positive  
    Negative  
    H
    H
    L
    H
    L
    H
    L
    H
    H
    H
    L
    H. COMP  
    (Negative)  
    H
    H
    L
    H
    H
    H
    L
    L
    L
    L
    No signal  
    L
    L
    H
    H
    L
    L
    H
    6/12  
    BA7078AF/AS  
    Multimedia ICs  
    !Relationship between INPUT to OUTPUT  
    INPUT  
    OUTPUT  
    VDRV  
    VIDEO  
    Composite / HSYNC  
    VSYNC  
    HDRV  
    VIDEO  
    CS  
    CLAMP  
    VIDEO  
    CS  
    −
    −
    VIDEO  
    CS  
    VS  
    −
    −
    −
    −
    VIDEO  
    CS  
    VIDEO  
    CS  
    VS  
    −
    −
    −
    −
    −
    −
    −
    −
    −
    CS  
    CS  
    VS  
    CS  
    −
    −
    CS  
    VS  
    CS  
    Explanation of symbol  
    : Signal Input  
    −
    : No Signal  
    !Input signal range  
    Parameter  
    Vert. separate sync Hor. separate sync  
    Composite sync  
    Posi. / Neg.  
    Sync on Video  
    Neg.  
    Posi. / Neg.  
    Posi. / Neg.  
    Polarity  
    Amplitude (Sync) : Vs  
    1.0 to 5.0VP-P  
    1.0 to 5.0VP-P  
    1.0 to 5.0VP-P  
    0.2 to 0.6VP-P  
    0 to 2.1VP-P  
    40 to 200Hz  
    ∗ 1HMin.  
    (Video) : Vv  
    Vert. sync frequency range : fV  
    40 to 200Hz  
    −
    40 to 200Hz  
    ∗ 1HMin. to 400µs  
    15k to 200kHz  
    Vert. sync pulse width range : pwV  
    Hor. sync frequency range : fH  
    8.0µs to Duty35%  
    −
    −
    −
    15k to 200kHz  
    94ns to Duty35%  
    15k to 200kHz  
    Duty30% Max.  
    Hor. sync pulse width range : pwH  
    94ns to Duty30%  
    ∗ 1H = 1 / fH  
    !Input signal waveform  
    Vert. / Hor.separate sync  
    T=1/f  
    VS  
    pw  
    Duty=pw/T(%)  
    Composite sync  
    TH=1/fH  
    VS  
    pwH  
    pwV  
    Duty=pwH/TH(%)  
    (ex.pwV=1H)  
    Sync on Video  
    V
    V
    S
    V
    pwH  
    pwV  
    Duty=pwH/TH(%)  
    (ex.pwV=1H)  
    TH=1/fH  
    7/12  
    BA7078AF/AS  
    Multimedia ICs  
    !Measurement circuit  
    1
    18  
    17  
    16  
    15  
    14  
    13  
    POLH  
    HSCTL  
    SW18  
    2
    4
    3
    1
    1
    1
    V1  
    A
    V
    V
    V
    V
    3mA  
    Oscilloscope  
    2
    EXIH  
    C / HSYNC IN  
    VIDEO IN  
    VSEPA  
    SW17  
    SW2  
    2
    3
    1
    2
    4
    3
    4.7µF  
    A
    4.7µF  
    V
    V2  
    3mA  
    75Ω  
    Oscilloscope  
    3
    POLV  
    SW16  
    SW3  
    2
    4
    2
    3
    1
    3
    1µF  
    A
    1µF  
    V3  
    V
    3mA  
    75Ω  
    Oscilloscope  
    4
    SW15  
    EXIV  
    0.56µF  
    2
    4
    3
    1
    A
    V
    V
    3mA  
    Oscilloscope  
    Vcc 5V  
    A
    5
    V
    CC  
    VSYNC IN  
    SW5  
    47µF  
    0.01µF  
    2
    3
    1
    4.7µF  
    V5  
    75Ω  
    1MΩ  
    6
    CVPOL  
    HDRV  
    SW13  
    2
    1.5µF  
    3
    3
    3
    1
    1
    1
    V
    V
    V
    V
    8mA  
    Oscilloscope  
    7
    12  
    SW12  
    2
    CVEXI  
    CLAMP  
    1µF  
    V
    8mA  
    Oscilloscope  
    11  
    8
    VDRV  
    SW11  
    2
    CPSEL  
    V8  
    V
    8mA  
    V
    Oscilloscope  
    CC  
    9
    10  
    CPWID  
    GND  
    3.9kΩ  
    100pF  
    Fig.1  
    8/12  
    BA7078AF/AS  
    Multimedia ICs  
    !Conditions for measurement of electrical characteristics  
    Switch condition  
    Parameter  
    2
    1
    1
    1
    1
    1
    3
    3
    3
    2
    1
    2
    2
    3
    2
    1
    2
    2
    3
    3
    2
    1
    3
    3
    1
    1
    1
    1
    1
    1
    1
    1
    1
    2
    2
    1
    2
    3
    1
    1
    1
    1
    1
    1
    1
    1
    1
    2
    1
    1
    1
    1
    2
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    2
    1
    1
    2
    1
    5
    1
    3
    3
    3
    2
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    2
    2
    3
    3
    2
    1
    3
    3
    1
    2
    2
    1
    1
    11  
    1
    1
    1
    2
    3
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    12  
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    3
    3
    2
    3
    3
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    3
    3
    13  
    1
    1
    1
    1
    1
    1
    1
    2
    3
    3
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    3
    3
    3
    3
    3
    15  
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    2
    4
    1
    1
    1
    1
    1
    16  
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    2
    4
    1
    1
    1
    1
    1
    1
    1
    1
    1
    17  
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    2
    4
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    18  
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    2
    4
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    1
    Quiescent current  
    VDRV output voltage "H"  
    VDRV output voltage "L"  
    VDRV output current "L"  
    VDRV rising delay time  
    HDRV output voltage "H"  
    HDRV output voltage "L"  
    HDRV output current "L"  
    HDRV rising delay time (1)  
    HDRV rising delay time (2)  
    CLAMP output voltage "H"  
    CLAMP output voltage "L"  
    CLAMP output current "L"  
    CLAMP rising delay time (1)  
    CLAMP rising delay time (2)  
    POLH output voltage "H"  
    POLH output voltage "L"  
    POLH output current "L"  
    POLH output impedance  
    EXIH output voltage "H"  
    EXIH output voltage "L"  
    EXIH output current "L"  
    EXIH output impedance  
    POLV output voltage "H"  
    POLV output voltage "L"  
    POLV output current "L"  
    POLV output impedance  
    EXIV output voltage "H"  
    EXIV output voltage "L"  
    EXIV output current "L"  
    EXIV output impedance  
    Minimum synchronization separation level  
    HSCTL "H" level threshold voltage  
    HSCTL "L" level threshold voltage  
    CPSEL "H" level threshold voltage  
    CPSEL "L" level threshold voltage  
    9/12  
    BA7078AF/AS  
    Multimedia ICs  
    !Application example  
    HSCTL  
    18  
    1
    2
    3
    POLH  
    C1  
    H
    SYNC DET.  
    17  
    C / H SYNC IN  
    EXIST H  
    4.7µF  
    C2  
    16  
    15  
    VIDEO IN  
    POLV  
    SYNC SEPA.  
    1µF  
    4
    5
    EXIST V  
    HOR. SYNC  
    CONTROL  
    C3  
    0.56µF  
    0.47µF  
    V
    cc 5V  
    V
    SYNC SEPA.  
    14  
    VSYNC IN  
    C7  
    R2  
    1MΩ  
    47µF  
    0.01µF  
    6
    13  
    12  
    11  
    HDRV  
    C4  
    C5  
    1.5µF  
    V
    SYNC DET.  
    7
    8
    CLAMP  
    VDRV  
    1µF  
    CPSEL  
    CLAMP PULSE GEN.  
    OPEN : AUTO  
    H : Front  
    V
    cc  
    L : Back  
    3.9kΩ  
    R1  
    10  
    9
    C6  
    100pF  
    Fig.2  
    10/12  
    BA7078AF/AS  
    Multimedia ICs  
    !Attached components  
    R :  
    The resistor for limiting the LED current.  
    Use the resistor of not less than 1W.  
    R
    RPM-850  
    LED  
    C1 : 47µF  
    C2 : 1µF  
    Coupling capacitor for C / H SYNC IN  
    A low capacitance increases the size of the input pin waveform’s sag.  
    Coupling capacitor for VIDEO IN  
    A low capacitance increase the size of the input pin waveform’s sag.  
    C3 : 0.56µF Conversion capacitor for f-V  
    A low capacitance increase the size of the ripple of the f-V conversion voltage. A large capacitance is not a  
    problem, but will delay the reaction speed.  
    C4 : 1.5 µF Capacitor for POLH (detection of the vertical synchronization signal’s polarity)  
    The minimum capacitance is determined as follows:  
    The internal hysteresis comparator does not react when the duty of minimum frequency synchronization  
    (fV = 40Hz, T = 25ms) is 50%.  
    CMin. = 16µ × T [F]  
    A large capacitance is not a probrem, built will deray the reaction speed.  
    C5 : 1µF  
    Capacitor for EXIH (detection of the vertical synchronization signal’s existance)  
    The minimum capacitance is determined as follows:  
    The internal hysteresis comparator does not react at the minimum frequency synchronization (fV = 40Hz,  
    T = 25ms)  
    CMin. = 16µ × T [F]  
    A large capacitance is not a problem, but will deray the reaction speed.  
    C6 : 100pF Constant for setting the clamp pulse width  
    C7 : 0.47µF Coupling capacitor for VSYNC IN  
    A low capacitance increases the size of the input pin waveform’s sag.  
    R1 : 3.9kΩ A low resistance results in a narrow clamp pulse width. Set no lower than 1kΩ.  
    R2 : 1MΩ  
    Discharge current setting resistor for CLAMP IN  
    11/12  
    BA7078AF/AS  
    Multimedia ICs  
    !Electrical characteristic curves  
    140  
    120  
    100  
    80  
    100  
    90  
    160  
    140  
    120  
    100  
    80  
    Output position : front edge  
    80  
    70  
    60  
    50  
    40  
    30  
    20  
    60  
    60  
    40  
    20  
    0
    40  
    20  
    0
    10  
    Vcc=5.0V  
    Vcc=5.0V  
    V
    CC=5.0V  
    75 100  
    0
    −50 −25  
    0
    25  
    50  
    −50 −25  
    0
    25  
    50  
    75  
    100  
    −50 −25  
    0
    25  
    50  
    75  
    100  
    TEMPERATURE : Ta(°C)  
    TEMPERATURE : Ta (°C)  
    TEMPERATURE : Ta (°C)  
    Fig.3 C / HSYNC IN-HDRV  
    Rising delay time vs.  
    temperature  
    Fig.5 VIDEO IN−HDRV  
    Rising delay time vs.  
    temperature  
    Fig.4 C / HSYNC IN-CLAMP  
    Rising delay time vs.  
    temperature  
    3
    2.5  
    2
    140  
    120  
    100  
    80  
    260  
    240  
    Output position back edge  
    220  
    200  
    180  
    160  
    140  
    1.5  
    1
    60  
    40  
    20  
    0
    0.5  
    0
    120  
    100  
    VCC=5.0V  
    Vcc=5.0V  
    V
    CC=5.0V  
    75 100  
    80  
    100 120 140 160 180 200  
    0
    20 40 60  
    −50 −25  
    0
    25  
    50  
    75  
    100  
    −50  
    −25  
    0
    25  
    50  
    HORIZONTAL FREQUENCY : fH (kHz)  
    TEMPERATURE : Ta (°C)  
    TEMPERATURE : Ta (°C)  
    Fig.8 VSEPA horizontal  
    frequency vs.  
    Fig.6 VIDEO IN-CLAMP  
    Rising delay time vs.  
    temperature  
    Fig.7 VSYNC IN-VDRV  
    Rising delay time vs.  
    temperature  
    pin voltage  
    !External dimensions (Unit : mm)  
    BA7078AF  
    BA7078AS  
    11.2 0.2  
    19.4 0.3  
    18  
    10  
    18  
    1
    10  
    9
    7.62  
    1
    9
    1.27  
    0.4 0.1  
    0.3Min.  
    0
    ∼ 15  
    1.778  
    0.5 0.1  
    0.15  
    SOP18  
    SDIP18  
    12/12  
    Appendix  
    Notes  
    No technical content pages of this document may be reproduced in any form or transmitted by any  
    means without prior permission of ROHM CO.,LTD.  
    The contents described herein are subject to change without notice. The specifications for the  
    product described in this document are for reference only. Upon actual use, therefore, please request  
    that specifications to be separately delivered.  
    Application circuit diagrams and circuit constants contained herein are shown as examples of standard  
    use and operation. Please pay careful attention to the peripheral conditions when designing circuits  
    and deciding upon circuit constants in the set.  
    Any data, including, but not limited to application circuit diagrams information, described herein  
    are intended only as illustrations of such devices and not as the specifications for such devices. ROHM  
    CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any  
    third party's intellectual property rights or other proprietary rights, and further, assumes no liability of  
    whatsoever nature in the event of any such infringement, or arising from or connected with or related  
    to the use of such devices.  
    Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or  
    otherwise dispose of the same, no express or implied right or license to practice or commercially  
    exploit any intellectual property rights or other proprietary rights owned or controlled by  
    ROHM CO., LTD. is granted to any such buyer.  
    Products listed in this document use silicon as a basic material.  
    Products listed in this document are no antiradiation design.  
    The products listed in this document are designed to be used with ordinary electronic equipment or devices  
    (such as audio visual equipment, office-automation equipment, communications devices, electrical  
    appliances and electronic toys).  
    Should you intend to use these products with equipment or devices which require an extremely high level of  
    reliability and the malfunction of with would directly endanger human life (such as medical instruments,  
    transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other  
    safety devices), please be sure to consult with our sales representative in advance.  
    About Export Control Order in Japan  
    Products described herein are the objects of controlled goods in Annex 1 (Item 16) of Export Trade Control  
    Order in Japan.  
    In case of export from Japan, please confirm if it applies to "objective" criteria or an "informed" (by MITI clause)  
    on the basis of "catch all controls for Non-Proliferation of Weapons of Mass Destruction.  
    Appendix1-Rev1.0  
    配单直通车
    BA7078AS产品参数
    型号:BA7078AS
    是否无铅： 不含铅
    是否Rohs认证： 符合
    生命周期：Active
    零件包装代码：DIP
    包装说明：SDIP, SDIP18,.3
    针数：18
    Reach Compliance Code：compliant
    HTS代码：8542.39.00.01
    风险等级：5.63
    Is Samacsys：N
    商用集成电路类型：CONSUMER CIRCUIT
    JESD-30 代码：R-PDIP-T18
    JESD-609代码：e3/e2
    长度：19.4 mm
    功能数量：1
    端子数量：18
    最高工作温度：75 °C
    最低工作温度：-25 °C
    封装主体材料：PLASTIC/EPOXY
    封装代码：SDIP
    封装等效代码：SDIP18,.3
    封装形状：RECTANGULAR
    封装形式：IN-LINE, SHRINK PITCH
    峰值回流温度（摄氏度）：260
    电源：5 V
    认证状态：Not Qualified
    座面最大高度：4.25 mm
    子类别：Other Consumer ICs
    最大压摆率：39 mA
    最大供电电压 (Vsup)：5.25 V
    最小供电电压 (Vsup)：4.75 V
    表面贴装：NO
    技术：BIPOLAR
    温度等级：COMMERCIAL EXTENDED
    端子面层：TIN/TIN COPPER
    端子形式：THROUGH-HOLE
    端子节距：1.778 mm
    端子位置：DUAL
    处于峰值回流温度下的最长时间：10
    宽度：7.62 mm
    Base Number Matches：1
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