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产品型号BCT574的Datasheet PDF文件预览

SN54BCT574, SN74BCT574  
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCBS074C – SEPTEMBER 1991 – REVISED MARCH 2003  
Operating Voltage Range of 4.5 V to 5.5 V  
State-of-the-Art BiCMOS Design  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Significantly Reduces I  
CCZ  
– 1000-V Charged-Device Model (C101)  
Full Parallel Access for Loading  
SN54BCT574 . . . J OR W PACKAGE  
SN74BCT574 . . . DB, DW, N, OR NS PACKAGE  
(TOP VIEW)  
SN54BCT574 . . . FK PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
CLK  
3
2
1
20 19  
18  
4
5
6
7
8
3D  
4D  
5D  
6D  
7D  
2Q  
3Q  
4Q  
5Q  
6Q  
17  
16  
15  
14  
9 10 11 12 13  
GND  
description/ordering information  
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
The eight flip-flops of the ’BCT574 devices are edge-triggered D-type flip-flops. On the positive transition of the  
clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without interface or pullup components.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
Tube  
SN74BCT574N  
SN74BCT574N  
Tube  
SN74BCT574DW  
SN74BCT574DWR  
SN74BCT574NSR  
SN74BCT574DBR  
SNJ54BCT574J  
SNJ54BCT574W  
SNJ54BCT574FK  
SOIC – DW  
BCT574  
0°C to 70°C  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP – NS  
SSOP – DB  
CDIP – J  
BCT574  
BT574  
SNJ54BCT574J  
SNJ54BCT574W  
SNJ54BCT574FK  
–55°C to 125°C  
CFP – W  
Tube  
LCCC – FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54BCT574, SN74BCT574  
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCBS074C SEPTEMBER 1991 REVISED MARCH 2003  
description/ordering information (continued)  
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLK  
D
H
L
H
L
L
L
H or L  
X
X
X
Q
0
H
Z
logic diagram (positive logic)  
1
OE  
11  
CLK  
C1  
1D  
19  
1Q  
2
1D  
To Seven Other Channels  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V  
I
Voltage range applied to any output in the disabled or power-off state, V . . . . . . . . . . . . . . . . 0.5 V to 5.5 V  
O
Voltage range applied to any output in the high state, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V  
O
CC  
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA  
IK  
I
Current into any output in the low state: SN54BCT574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA  
SN74BCT574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA  
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W  
JA  
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W  
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W  
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C  
stg  
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
2. The package thermal impedance is calculated in accordance with JESD 51-7.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54BCT574, SN74BCT574  
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCBS074C SEPTEMBER 1991 REVISED MARCH 2003  
recommended operating conditions (see Note 3)  
SN54BCT574  
MIN NOM MAX  
SN74BCT574  
MIN NOM MAX  
UNIT  
V
V
V
Supply voltage  
4.5  
2
5
5.5  
4.5  
2
5
5.5  
V
V
CC  
IH  
IL  
High-level input voltage  
Low-level input voltage  
Input clamp current  
0.8  
18  
12  
48  
0.8  
18  
15  
64  
V
I
I
I
mA  
mA  
mA  
°C  
IK  
High-level output current  
Low-level output current  
Operating free-air temperature  
OH  
OL  
T
A
55  
125  
0
70  
NOTE 3: All unused inputs of the device must be held at V  
or GND to ensure proper device operation. Refer to the TI application report,  
CC  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
SN54BCT574  
SN74BCT574  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN TYP  
MAX  
MIN TYP  
MAX  
V
V
V
= 4.5 V,  
= 4.5 V  
I = 18 mA  
1.2  
1.2  
V
IK  
CC  
I
I
I
I
I
I
= 3 mA  
= 12 mA  
= 15 mA  
= 48 mA  
= 64 mA  
2.4  
2
3.3  
3.2  
2.4  
2
3.3  
3.1  
OH  
OH  
OH  
OL  
OL  
V
OH  
V
CC  
0.38  
0.55  
V
OL  
V
CC  
= 4.5 V  
V
0.42  
0.55  
0.4  
20  
I
I
I
I
I
I
I
I
I
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5 V,  
V = 5.5 V  
I
0.4  
20  
mA  
µA  
I
V = 2.7 V  
I
IH  
IL  
V = 0.5 V  
I
0.6  
225  
50  
0.6  
225  
50  
mA  
mA  
µA  
V
O
V
O
V
O
= 0  
100  
100  
OS  
= 2.7 V  
= 0.5 V  
OZH  
OZL  
CCL  
CCH  
CCZ  
50  
62  
50  
62  
µA  
Outputs open  
Outputs open  
Outputs open  
38.1  
4.9  
38.1  
4.9  
4.9  
5.5  
7.5  
mA  
mA  
mA  
pF  
8
8
4.5  
8
8
C
C
V = 2.5 V or 0.5 V  
I
i
= 5 V,  
V
O
= 2.5 V or 0.5 V  
pF  
o
All typical values are at V  
= 5 V, T = 25°C.  
A
CC  
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.  
timing requirements over recommended ranges of supply voltage and operating free-air  
temperature (unless otherwise noted)  
V
T
= 5 V,  
= 25°C  
CC  
A
SN54BCT574 SN74BCT574  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
f
t
Clock frequency  
77  
77  
77  
MHz  
ns  
clock  
Pulse duration, CLK high or low  
6.5  
4.5  
6
6.5  
4.5  
6
6.5  
4.5  
6
w
High  
t
ns  
ns  
Setup time, data before CLK↑  
Hold time, data after CLK↑  
su  
h
Low  
t
High or low  
0
1
0
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54BCT574, SN74BCT574  
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCBS074C SEPTEMBER 1991 REVISED MARCH 2003  
switching characteristics over recommended ranges of supply voltage and operating free-air  
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)  
L
V
T
= 5 V,  
= 25°C  
CC  
A
SN54BCT574 SN74BCT574  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
MIN  
77  
TYP  
MAX  
MIN  
77  
MAX  
MIN  
77  
MAX  
f
t
t
t
t
t
t
MHz  
ns  
max  
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
2.2  
2.8  
2.5  
3.7  
1
6.5  
6.1  
6.4  
7.3  
4.4  
4.2  
8.6  
8
2.2  
2.8  
2.5  
3.7  
1
11.2  
9.7  
10.9  
11.3  
8
2.2  
2.8  
2.5  
3.7  
1
10  
8.9  
CLK  
Q
Q
Q
8.1  
9.2  
7.4  
5.8  
10.4  
10.9  
7.5  
ns  
ns  
OE  
OE  
1.3  
1.3  
7.1  
1.3  
6.4  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SN54BCT574, SN74BCT574  
OCTAL TRANSPARENT D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCBS074C SEPTEMBER 1991 REVISED MARCH 2003  
PARAMETER MEASUREMENT INFORMATION  
7 V (t  
, t  
, O.C.)  
PZL PLZ  
Open  
(all others)  
S1  
From Output  
Under Test  
Test  
Point  
C
L
R1  
R1  
(see Note A)  
From Output  
Under Test  
Test  
Point  
C
L
R2  
(see Note A)  
LOAD CIRCUIT FOR  
TOTEM-POLE OUTPUTS  
R
= R1 = R2  
L
LOAD CIRCUIT FOR  
3-STATE AND OPEN-COLLECTOR OUTPUTS  
High-Level  
Pulse  
(see Note B)  
3 V  
0 V  
1.5 V  
1.5 V  
3 V  
Timing Input  
(see Note B)  
1.5 V  
t
w
0 V  
3 V  
0 V  
3 V  
0 V  
t
h
Low-Level  
Pulse  
t
1.5 V  
su  
1.5 V  
Data Input  
(see Note B)  
1.5 V  
1.5 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
3 V  
0 V  
Output  
Control  
(low-level enable)  
3 V  
1.5 V  
1.5 V  
Input  
(see Note B)  
1.5 V  
1.5 V  
0 V  
PHL  
t
t
PZL  
t
t
PLZ  
t
PLH  
3.5 V  
In-Phase  
Output  
(see Note D)  
V
OH  
1.5 V  
Waveform 1  
(see Notes C and D)  
1.5 V  
1.5 V  
1.5 V  
t
V
OL  
V
OL  
0.3 V  
t
PHZ  
PLH  
t
PHL  
PZH  
V
OH  
V
OH  
Out-of-Phase  
Output  
(see Note D)  
Waveform 2  
(see Notes C and D)  
1.5 V  
1.5 V  
0.3 V  
0 V  
V
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES (see Note D)  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS  
NOTES: A.  
C includes probe and jig capacitance.  
L
B. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, t = t 2.5 ns, duty cycle = 50%.  
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
D. The outputs are measured one at a time with one transition per measurement.  
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.  
F. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
4-Jun-2007  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
LCCC  
CDIP  
CFP  
Drawing  
5962-9583601Q2A  
5962-9583601QRA  
5962-9583601QSA  
SN74BCT574DBR  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
FK  
J
20  
20  
20  
20  
1
1
1
TBD  
TBD  
TBD  
POST-PLATE N / A for Pkg Type  
A42 SNPB  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
W
SSOP  
DB  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74BCT574DBRE4  
SN74BCT574DBRG4  
SN74BCT574DW  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SSOP  
SSOP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SO  
DB  
DB  
DW  
DW  
DW  
DW  
DW  
DW  
N
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74BCT574DWE4  
SN74BCT574DWG4  
SN74BCT574DWR  
SN74BCT574DWRE4  
SN74BCT574DWRG4  
SN74BCT574N  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
20  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
SN74BCT574NE4  
SN74BCT574NSR  
SN74BCT574NSRE4  
SN74BCT574NSRG4  
N
20  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
NS  
NS  
NS  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SNJ54BCT574FK  
SNJ54BCT574J  
SNJ54BCT574W  
ACTIVE  
ACTIVE  
ACTIVE  
LCCC  
CDIP  
CFP  
FK  
J
20  
20  
20  
1
1
1
TBD  
TBD  
TBD  
POST-PLATE N / A for Pkg Type  
A42 SNPB  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
W
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
4-Jun-2007  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
19-May-2007  
TAPE AND REEL INFORMATION  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
19-May-2007  
Device  
Package Pins  
Site  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) (mm) Quadrant  
(mm)  
330  
(mm)  
16  
SN74BCT574DBR  
SN74BCT574DWR  
SN74BCT574NSR  
DB  
DW  
NS  
20  
20  
20  
MLA  
MLA  
MLA  
8.2  
10.8  
8.2  
7.5  
2.5  
2.7  
2.5  
12  
12  
12  
16  
24  
24  
Q1  
Q1  
Q1  
330  
24  
13.0  
13.0  
330  
24  
TAPE AND REEL BOX INFORMATION  
Device  
Package  
Pins  
Site  
Length (mm) Width (mm) Height (mm)  
SN74BCT574DBR  
SN74BCT574DWR  
SN74BCT574NSR  
DB  
DW  
NS  
20  
20  
20  
MLA  
MLA  
MLA  
342.9  
333.2  
333.2  
336.6  
333.2  
333.2  
28.58  
31.75  
31.75  
Pack Materials-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
19-May-2007  
Pack Materials-Page 3  
MECHANICAL DATA  
MLCC006B – OCTOBER 1996  
FK (S-CQCC-N**)  
LEADLESS CERAMIC CHIP CARRIER  
28 TERMINAL SHOWN  
A
B
NO. OF  
TERMINALS  
**  
18 17 16 15 14 13 12  
MIN  
MAX  
MIN  
MAX  
0.342  
(8,69)  
0.358  
(9,09)  
0.307  
(7,80)  
0.358  
(9,09)  
19  
20  
11  
10  
9
20  
28  
44  
52  
68  
84  
0.442  
(11,23)  
0.458  
(11,63)  
0.406  
(10,31)  
0.458  
(11,63)  
21  
B SQ  
22  
0.640  
(16,26)  
0.660  
(16,76)  
0.495  
(12,58)  
0.560  
(14,22)  
8
A SQ  
23  
0.739  
(18,78)  
0.761  
(19,32)  
0.495  
(12,58)  
0.560  
(14,22)  
7
24  
25  
6
0.938  
(23,83)  
0.962  
(24,43)  
0.850  
(21,6)  
0.858  
(21,8)  
5
1.141  
(28,99)  
1.165  
(29,59)  
1.047  
(26,6)  
1.063  
(27,0)  
26 27 28  
1
2
3
4
0.080 (2,03)  
0.064 (1,63)  
0.020 (0,51)  
0.010 (0,25)  
0.020 (0,51)  
0.010 (0,25)  
0.055 (1,40)  
0.045 (1,14)  
0.045 (1,14)  
0.035 (0,89)  
0.045 (1,14)  
0.035 (0,89)  
0.028 (0,71)  
0.022 (0,54)  
0.050 (1,27)  
4040140/D 10/96  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a metal lid.  
D. The terminals are gold plated.  
E. Falls within JEDEC MS-004  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001  
DB (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
28 PINS SHOWN  
0,38  
0,22  
0,65  
28  
M
0,15  
15  
0,25  
0,09  
5,60  
5,00  
8,20  
7,40  
Gage Plane  
1
14  
0,25  
A
0°ā8°  
0,95  
0,55  
Seating Plane  
0,10  
2,00 MAX  
0,05 MIN  
PINS **  
14  
16  
20  
24  
28  
30  
38  
DIM  
6,50  
5,90  
6,50  
5,90  
7,50  
8,50  
7,90  
10,50  
9,90  
10,50 12,90  
A MAX  
A MIN  
6,90  
9,90  
12,30  
4040065 /E 12/01  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-150  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,  
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Customers should obtain the latest relevant information before placing orders and should verify that such information is current and  
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s  
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask  
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TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products  
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:  
Products  
Amplifiers  
Data Converters  
DSP  
Applications  
Audio  
amplifier.ti.com  
dataconverter.ti.com  
dsp.ti.com  
www.ti.com/audio  
Automotive  
Broadband  
Digital Control  
Military  
www.ti.com/automotive  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
interface.ti.com  
logic.ti.com  
Logic  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
www.ti-rfid.com  
www.ti.com/lpw  
Telephony  
Low Power  
Wireless  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2007, Texas Instruments Incorporated  
配单直通车
BCT8-08产品参数
型号:BCT8-08
是否Rohs认证: 符合
生命周期:Contact Manufacturer
包装说明:R-MXFM-D3
Reach Compliance Code:unknown
风险等级:5.7
其他特性:LOW POWER LOSS
应用:EFFICIENCY
配置:COMMON CATHODE, 2 ELEMENTS
二极管元件材料:SILICON
二极管类型:RECTIFIER DIODE
最大正向电压 (VF):1 V
JESD-30 代码:R-MXFM-D3
最大非重复峰值正向电流:300 A
元件数量:2
相数:1
端子数量:3
最高工作温度:150 °C
最低工作温度:-55 °C
最大输出电流:4 A
封装主体材料:METAL
封装形状:RECTANGULAR
封装形式:FLANGE MOUNT
峰值回流温度(摄氏度):NOT SPECIFIED
最大重复峰值反向电压:800 V
最大反向电流:10 µA
端子形式:SOLDER LUG
端子位置:UNSPECIFIED
处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1
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