BD8174MU各脚功能电路原理芯片引脚定义引脚图及功能IC贸易商-中国IC网-芯三七

Datasheet

Power Supply IC Series for TFT-LCD Panels

Output voltage fixed-type

Multi-channel System Power Supply IC

BD8174MUV

General Description

Key Specifications

The BD8174MUV is a system power supply IC that

generates 6 power supply channels required by TFT-LCD

panels on a single chip.



Power Supply Voltage 1 Range:

Oscillating Frequency:

Operating Temperature Range:

10V to 14V

700kHz(Typ)

-40°C to +105°C

Output voltage and sequence is fixed so that it is possible

to control output with few external components.

Package

W(Typ) x D(Typ) x H(Max)

Features



Step-up DC/DC Converter with Built-in 3A FET

Synchronous Step-down DC/DC Converter with

Built-in 2A FET



High Voltage LDO (50mA)

Low Voltage LDO (400mA)

Positive/ Negative Charge Pumps (Integrated-diode)

10bit DAC 4CH

VCOM Amplifier

Gate Shading Function

All-output Shut Down Function

Power Good Function

VQFN048V7070

7.00mm x 7.00mm x 1.00mm

Protection Circuits:

 Under-Voltage Lockout Protection Circuit

 Thermal Shutdown Circuit

 Over Current Protection Circuit

 Over Voltage Protection Circuit

 Timer Latch Type Short-Circuit Protection Circuit

Constant Startup Sequence



Applications

LCD TV power supplies

○Product structure：Silicon monolithic integrated circuit ○This product has no designed protection against radioactive rays

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Typical Application Circuit (1)

LVLDO

(1.2/1.5/1.8V)

VDD

(3.3V)

1.

VCC12V input application

BOOT

LVCTL

PG

OUT0

SCP

OUT0

LVCTL

VDD

PG

DACGND

FBLD1

HVLDO

INP

PVCC2

FB1

HVLDO

COMP1

PGND1

SW1

VCOM

BD8174MUV

INN

VCOM

THR

CTL

SW1

CTL

LSO1

DRN

COM

VIN

(12V)

VGH

(35.2V)

VLS

VGL

(-6V)

2.

Startup sequence

VDD1

VIN input

VLS

(Step-up)

VGL

VGH

GS

PG

(Step-down)

LVLDO

(Negative charge pump) (Positive charge pump)

HVLDO (15.2V)

DAC OUT

VCOM

DAC Control

VGH(35.2V)

80%

3.

Power up sequence

VIN(12V)

VLS(15.6V)

HVLDO(15.2V)

2m(typ)

PG

DAC OUT

VDD(3.3V)

VCOM

LVLDO(1.2/1.5/1.8V)

DAC Control

GS logic

VGL(-6V)

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Block Diagram

VIN(12V)

C12

C15

GCTL

PVCC1

1

2

34

VCC

OCP

PVCC2

40

LSO1

Load SW

Control

C22

L21

47

48

VDD

3.3V

L11

D11

SW2

STEP DOWN

DC/DC

35

36

OCP

SW1₄₅

C21

PGND2

46

STEP UP

DC/DC

REG5

VDD

C11

C25

PGND

37

33

43

BOOT

44

Soft

Start

Soft

Start

R11

REF

C13

VDD_S

SEQUENCE

CONTROL

ERR

REF

FB1 ₄₁

ERR

COMP1

FB2

R12

42

C14 R14

VLS

15.6V

HVCC

OVP

HVCC

4

UVLO

C32

HVLDO

15.2V

HV LDO

OVP

OCP

HVLDO

C33

20

21

R31

R32

C31

HVCC

UVLO

TSD

VGH

FBLD1

35.2V

VGH

12

D51

REG5

CPD2

CPD1

C51

10

11

REG5

32

VREF

REG

REG5

CPP1

CPP2

7

8

C53 C52

C92

VDD

Positive

Charge Pump

OSC

LVLDO

1.8V/1.5V/1.2V

FBCP1

LV LDO

LVLDO

LVCTL

C54

31

38

VDD

C41

FBLD2

CPPCTL ³

R91

39

PG

1.5V

COM

REF

13

DRN

FBCP2

Gate

14

Shading

C81

R81

CTL

15

VGL_S

5

6

THR

16

CPN

Negative

Charge Pump

FB1

D61

C62

VGL

-6V

FB2

FBLD1

FBLD2

FBCP1

FBCP2

Timer

Latch

HVCC

C61

INP

From Calibrator

VCOM

19

INN

SCP

18

23

C93

17

HVLDO

VCOM

R73

VCC

28

9

VDD

GND

C71

CPGND

Power

On Reset

DACVREF

HVCC

DACVREF

c

DACGND

22

I2C

I/F

DAC Control

29

SDA

SCL

30

×4

AMP1

AMP3

AMP0

24

AMP2

26

25

27

OUT1

OUT3

OUT0

OUT2

C901

C903

C900

C902

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Application Parts List (When VLS=15.6V, HVLDO=15.2V is configured)

PARTS LOCATION

Value

130kΩ+16kΩ

10kΩ

Company

ROHM

PRODUCT NUMBER

MCR01MZPD

R11

R12

MCR01MZPD

R14

R31

R32

R73

R81

R91

C11

C12

C13

C14

C15

C21

C22

C25

C31

C32

C33

C41

C51

C52

C53

C54

C61

C62

C71

C81

C92

C93

C900

C901

C902

C903

L11

3kΩ

130kΩ+12kΩ

10kΩ

430Ω

4.3kΩ

100kΩ

10µF

100pF

2200pF

-

10µF

0.1µF

4.7µF

10µF

22pF

4.7µF

1.0µF

0.1µF

-

1.0µF

22000pF

1.0µF

1000pF

1.0µF

0.1µF

10µF

10µH

-

ROHM

Murata

-

Murata

-

MCR01MZPD

MCR18EZHF

MCR03EZPD

MCR01MZPD

GRM31CB31E106KA75

GRM1882C1H101JA01

GRM188B11H222KA01

-

GRM31CB31E106KA75

GRM188R11H104KA93

GRM319B31E475KA75

GRM31CB31E106KA75

GRM1882C1H220JA01

GRM21BB31C475KA75

GRM21BB31H105KA12

GRM188R11H104KA93

-

GRM188R11H104KA93

GRM188B11H223KA01

GRM21BB31H105KA12

GRM188B11H102KA01

GRM21BB31H105KA12

GRM188R11H104KA93

GRM31CB31E106KA75

NR6045T100M

Murata

TAIYOYUDEN

TAIYO YUDEN

ROHM

L21

NR6045T100M

RSX501L-20

RB162M-40

RB550EATR

D11

D51

D61

-

Pin Configuration

TOP VIEW

36 35 34 33 32 31 30 29 28 27 26 25

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

9 10 11 12

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BD8174MUV

Pin Description

Pin name

Function

NO.

1

PVCC1

CPPCTL

HVCC

Boost DC/DC load switch input. See Boost DC/DC (1) for more information.

Positive charge pump control input. See charge pump (4) for more information.

Power supply pin for charge pump, buffer amplifier and HV_LDO.

Negative charge pump output VGL feedback input.

Negative charge pump regulator driver output. Drive pin for negative charge pump.

See charge pump (4) for more information.

2

3

4

VGL_S

5

CPN

6

7

8

Positive charge pump regulator driver output1. Drive pin for positive charge pump.

See charge pump (4) for more information.

CPP1

CPP2

Positive charge pump regulator driver output2. Drive pin for positive charge pump.

See charge pump (4) for more information.

CPGND

CPD2

CPD1

VGH

9

Power grounding pin at charge pump.

10

11

12

13

14

15

16

17

18

19

20

21

22

Positive charge pump internal switching diode output2.

Positive charge pump internal switching diode output1.

Positive charge pump output VGH. Connect output capacitor from this pin to GND.

Gate shading output pin.

COM

DRN

Termination of the low side switch of the gate voltage shading block.

Gate shading control input pin.

CTL

THR

Gate shading Low level setting pin.

VCOM

INN

VCOM Output

VCOM input-.

INP

VCOM input+.

HVLDO

FBLD1

DACGND

HV_LDO output pin. Insert output capacitance for GND.

HV_LDO feedback input pin.

GND pin for DAC.

Short protection delay pin. To set short protection delay time, connect capacitor for GND pair.

For details, refer to information in common block (6).

Gamma output pin.

SCP

23

OUT0

OUT1

OUT2

OUT3

GND

24

25

26

27

28

29

30

31

32

33

34

35

36

Gamma output pin.

Grounding pin.

SDA

Serial data input pin.

SCL

Serial clock input pin.

LVLDO

REG5

VDD_S

GCTL

SW2

LV_LDO output pin. Output outputs 1.8V/ 1.5V/ 1.2V (typ). Insert output capacitance for GND.

Internal power supply 5.0V output pin. Connect 0.1µF from this pin to ground.

Buck DC/DC output VDD feedback input. No external registance necessary for feedback register.

Boost DC/DC load switch PGATE control input. For details, refer to information in Boost DC/DC (1).

Buck DC/DC switching output. Due to reduce EMI, make a wiring thick and short.

Buck DC/DC switching node power grounding pin. Due to reduce EMI, make a wiring thick and short.

Buck DC/DC bootstrap pin. This pin generates the gate drive voltage for the Buck converter.

Connect 0.1µF from this pin to the switch pin of step down converter, SW2.

LVLDO output voltage setting pin.

PGND2

BOOT

LVCTL

PG

37

38

39

40

Power good output. After positive charge pump output VGH startup, It will be ON. For Buck DC/DC output,

Pull-UP and use it. If you don’t use it, It will open.

PVCC2

Buck DC/DC high side MOSFET power supply input. Connect a capacitor as close to PVCC pin as possiple.

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BD8174MUV

Pin Description – Continued

Pin name

Function

NO.

Boost DC/DC output VLS feedback input. Connect a external resister and insert resistance for phase

compensation setting between VLS. For details, refer to information in Boost DC/DC (1).

Boost DC/DC error amplifier output pin. Connect a resistance for phase compensation and capacitor.

For details, refer to information in Boost DC/DC (1).

FB1

41

COMP1

42

PGND1

SW1

43

44

45

46

47

48

Boost DC/DC switching node power ground pin. Due to reduce EMI, make a wiring thick and short.

Boost DC/DC switching output. Due to reduce EMI, make a wiring thick and short.

Boost DC/DC load switch output. For details, refer to information in Boost DC/DC (1).

SW1

LSO1

Absolute Maximum Ratings (Ta=25°C)

Parameter

Symbol

Rating

15

Unit

V

Power Supply Voltage 1

Power Supply Voltage 2

SW1 Pin Voltage

V_PVCC1,V_PVCC2

V_HVCC

V_SW1

20

V

20

V

VGH Pin Voltage

V_VGH

40

V

Maximum Junction Temperature

Power Dissipation

Tjmax

Pd

150

°C

W

°C

4.83 ^{(Note 1)}

-40 to 105

-55 to 150

Operating Temperature Range

Topr

Storage Temperature Range

Tstg

(Note 1) To use the IC at temperatures over Ta25°C, derate power rating by 38.61mW/°C.

When mounted on a four-layer glass epoxy board measuring 74.2mm x 74.2mm x 1.6mm (with all layer of copper foil 5505mm²).

Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over

the absolute maximum ratings.

Recommended Operating Conditions (Ta-40°C to +105°C)

Parameter

Power Supply Voltage 1

Power Supply Voltage 2

SW1 Pin Voltage

Symbol

V_PVCC1,V_PVCC2

V_HVCC

Min

Max

14

Unit

V

10

-

18

V

V_SW1

18

V

SW1 Pin Current

I_SW1

-

3 ^{(Note 2)}

2 ^{(Note 2)}

5.5

A

SW2 Pin Current

I_SW2

-

A

Power Good Pull-up Voltage

V_PG

-

V

V_GCTL, V_CPPCTL

V_CTL

,

CTL Pin Voltage

-

5.5

V

THR Pin Voltage

V_THR

V_LVCTL

1.0

2.5

14

V

LVCTL Pin Voltage

-

INP,INN Pin Voltage

V_INP,V_INN

(Note 2) Not to exceed Pd.

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Electrical Characteristics (Unless otherwise noted, Ta25°C, V_CC12V, V_HVCC15V )

Limit

Parameter

Symbol

Unit

Condition

MIN

TYP

MAX

【DC/DC】

Step Up

Reference Voltage

Step Down

V_LSREF1

V_LSREF2

V_DD1

0.985

0.982

3.25

1.00

1.015

1.018

3.35

V

-

3.30

-

-25°C < Ta < 105°C

Output Voltage

V_DD2

3.24

3.36

-25°C < Ta < 105°C

V_COMP1=1.0V, V_FB1=0.5V

-25°C < Ta < 105°C

COMP1 Source Current

I_CSO

I_CSI

-

-20

-

µA

V_COMP1=1.0V, V_FB1=1.5V

-25°C < Ta < 105°C

COMP1 Sink Current

SW1,2, MAX Duty

+20

MDT

R_ON11

75

-

90

0.2

-

99

%

Ω

-

I_SW=0.8A

SW1 ON Resistance

R_ON12

-

Ω

I_SW=10mA, -25°C < Ta < 105°C

-25°C < Ta < 105°C

I_SW=0.8A

SW1 Current Limit

SW2 High side

ON Resistance

I_SW1OCP

R_ON2H1

R_ON2H2

R_ON2L1

R_ON2L2

I_SWLEAK

I_SW2OCP

V_GCTLH

V_GCTLL

I_GCTL

3

-

A

0.2

0

-

Ω

-

Ω

I_SW=10mA, -25°C < Ta < 105°C

I_SW=0.8A

SW2 Low side

ON Resistance

-

Ω

-

Ω

I_SW=10mA, -25°C < Ta < 105°C

SW1,2 Leakage Current

SW2 Current Limit

GCTL Input High Voltage

GCTL Input Low Voltage

GCTL Input Current

VLS

-5

2

-

+5

-

µA

A

-

-25°C < Ta < 105°C

V_GCTL=0V

-

V

-

0.2

-9

V

-20

-14.5

µA

V_OVP1

18

19

20

V

-25°C < Ta < 105°C

Over Voltage Threshold

【Load Switch】

R_ONLSO11

R_ONLSO12

t_{SS_LSO1}

-

0.2

1.5

-

Ω

l_O=-0.8A

ON Resistance

l_O=-10mA, -25°C < Ta < 105°C

R_LSO1=10kΩ, -25°C < Ta < 105°C

Soft Start Period 85%

0.75

3.0

ms

【High Voltage LDO】

V_{HVLDO_H1}

V_{HVLDO_H2}

V_HVDPLDH

0.99

0.982

-

1.00

-

1.01

1.018

0.5

V

LDO_H Reference Voltage

-25°C < Ta < 105°C

V_HVCC=15V, l_O=50mA

I/O Voltage Differential H

0.2

【Low Voltage LDO】

V_{LVLDO_H1}

V_{LVLDO_H2}

V_{LVLDO_M1}

V_{LVLDO_M2}

V_{LVLDO_L1}

V_{LVLDO_L2}

V_LVDPLDH

1.18

1.16

1.77

1.74

1.48

1.45

-

1.2

-

1.22

1.24

1.83

1.86

1.52

1.55

0.5

V

LVCTL=H

-25°C < Ta < 105°C,LVCTL=H

LVCTL=M

1.8

-

LDO Output Voltage

-25°C < Ta < 105°C,LVCTL=M

LVCTL=L

1.5

-

-25°C < Ta < 105°C,LVCTL=L

V_DD=3.3V, l_O=200mA

I/O Voltage Differential H

0.2

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Electrical Characteristics – continued (Unless otherwise noted, Ta25°C, V_CC12V, V_HVCC15V )

Limit

Parameter

【Charge pumps】

VGH Output Voltage

Symbol

Unit

Condition

MIN

TYP

MAX

V_VGH1

V_VGH2

V_VGL1

V_VGL2

34.6

34.5

-6.12

-6.15

35.2

35.8

35.9

-5.88

-5.85

V

-

-6.0

-

-25°C < Ta < 105°C

VGL Output Voltage

-25°C < Ta < 105°C

CPP1,2,CPN High side

ON Resistance

R_ONCH

-

5

-

Ω

CPP1,2,CPN Low side

ON Resistance

-25°C < Ta < 105°C

R_ONCL

-25°C < Ta < 105°C

V_CPPCTL=0V

CPPCTL Input High Voltage

V_CPCTLH

2

-

0.2

-9

V

CPPCTL Input Low Voltage V_CPCTLL

CPPCTL Pin Input Current

PG ON Voltage

I_CPCTL

PGH

PGL

-20

-

-14.5

80

60

37.5

-

µA

%

V

-

PG OFF Voltage

-

V_OVP2

V_OVP3

36.5

36

38.5

39

VGH

Over Voltage Threshold

【Gate Shading】

CTLInput High Voltage

CTLInputLowVoltage

VGH-COM ON Resistance

COM-DRN ON Resistance

V

-25°C < Ta < 105°C

Input Voltage=3.3V,

-25°C < Ta < 105°C

V_CTLH

V_CTLL

2.3

-

1.0

-

V

Ω

-

R_ONSRC

R_ONDRN

5

30

-

CTL High Input Current

I_CTLH

16.5

33

66

µA

【Operation amplifier】

Input Offset Voltage

V_OFF

I_BAMP

-15

-

+15

mV

µA

Input Bias Current

VCOM

Output Current Capability

Slew Rate

-1.2

+1.2

V_VCOM=0V,INN=VCOM,V_INP=15V,

-25°C < Ta < 105°C

Without external components

I_O=-1mA to +1mA

I_COM

50

150

-

mA

SRCOM

-

15

0

-

V/µs

mV

Load Stability

ΔVo

-15

+15

I_O=-1mA, V_INP=14V, V_INN=0V

-25°C < Ta < 105°C

Output Swing-High

V_OH

V_OL

V_HVCC-1.0 V_HVCC-0.8

-

V

I_O=1mA, V_INP=0V, V_INN=14V

-25°C < Ta < 105°C

Output Swing-Low

-

0.1

0.2

【Gamma Amplifier】

Source Current Capability

DAC=1B5h, V_OUT=0V,

-25°C < Ta < 105°C

I_ooA

I_oiA

-

30

-

mA

DAC=1B5h, OUT=HVCC,

-25°C < Ta < 105°C

Sink Current Capability

-30

Load Regulation

ΔVo

V_OH1

V_OH2

V_OL1

V_OL2

-

15

-

mV

V

I_O=-15mA to 15mA

I_O=-4mA

V_HVCC-0.2

Output Swing - High

V_HVCC-0.3

-

V

I_O=-4mA, -25°C < Ta < 105°C

I_O=4mA

-

0.2

0.3

V

Output Swing – Low

-

V

I_O=4mA, -25°C < Ta < 105°C

【DAC】

Resolution

Res

LE

10

-

Bit

Integral Non-linearity Error

(INL)

00A to 3F5 is the allowable margin of

error against the ideal linear.

-2

+2

LSB

00A to 3F5 is the allowable margin of

error against the ideal increase of

Differential

Error (DNL)

Non-linearity

DLE

-

LSB

【Control Signal SDA, SCL】

Input Voltage H

-25°C < Ta < 105°C

I_SDA=3mA

V_TH1

V_TH2

V_SDA

1.7

-

V

Input Voltage L

-

0.5

0.4

Min Output Voltage

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BD8174MUV

Electrical Characteristics – continued (Unless otherwise noted, Ta25°C, V_CC12V, V_HVCC15V )

Limit

Parameter

【Overall】

Symbol

Unit

Condition

MIN

TYP

MAX

f_SW1

f_SW2

600

500

7.6

700

-

800

900

8.4

kHz

V

Oscillator Frequency

-25°C < Ta < 105°C

VCC Under-Voltage Lockout

Threshold ON/OFF Voltage

HVCC Under-Voltage

Lockout Threshold ON/OFF

Voltage

-25°C < Ta < 105°C

V_CCUV

8.0

V_HVCCUV

-

8.5

-

V

SCP Source Current

SCP Sink Current

I_SCPSO

I_SCPSI

V_SCP

2

1

-

5

2

8

6

-

µA

mA

V

-25°C < Ta < 105°C

SCP Threshold Voltage

1.5

Average Current

Consumption 1 (VCC,PVCC)

Average Current

Consumption 2 (VCC,PVCC)

Average Current

Consumption 3 (HVCC)

Average Current

I_CC1

I_CC2

I_HICC1

I_HICC2

-

3.5

-

mA

No Switching

-25°C < Ta < 105°C, No Switching

No Switching

-25°C < Ta < 105°C, No Switching

Consumption 4 (HVCC)

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Typical Performance Curves

(Unless otherwise noted, Ta=25°C)

1.05

1.04

1.03

1.02

1.01

1

3.6

3.5

3.4

3.3

3.2

3.1

3

0.99

0.98

0.97

0.96

0.95

2.9

-40 -20

0

20

40

60

80 100

7

9

11

PVCC[V]

13

Temperature [°C]

温度[℃]

PVCC[V]

Figure 1. ICC vs PVCC

Figure 2. VLSREF vs Temperature

800

780

760

740

720

700

680

660

640

620

600

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0

1

2

3

4

-40 -20

0

20

40

60

80

100

Temperature [°C]

温度[℃]

VDD[V]

Figure 4. Divided Voltage vs VDD

Figure 3. Oscillation Frequency vs

Temperature

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Typical Performance Curves – continued

20

15

1.4

1.2

1

10

5

0.8

0.6

0.4

0.2

0

-5

-10

-15

-20

0

0.5

1

1.5

2

0

5

10

15

20

25

30

35

40

FB1 Voltage [V]

FB1電圧[V]

VGH[V]

Figure 5. Divided Voltage vs VGH

Figure 6. ICOMP vs FB1 Voltage

100

1

0.8

90

80

70

60

50

40

30

20

10

0

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

0

0.5

1

1.5

2

0

0.5

1

1.5

2

COMP1 Voltage [V]

FB1 Voltage [V]

COMP1電圧[V]

FB1電圧[V]

Figure 7. IFB1 vs FB1 Voltage

Figure 8. DUTY vs COMP1 Voltage

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Typical Performance Curves – continued

1.55

1.53

1.51

1.49

1.47

1.45

15.5

15.4

15.3

15.2

15.1

15

14.9

14.8

14.7

14.6

14.5

0

100

200

300

400

0

10

20

30

40

50

Load Current [mA]

負荷電流[mA]

Load Current [mA]

負荷電流[mA]

Figure 9. Output Voltage vs Load Current

Figure 10. Output Voltage vs Load Current

1.25

1.85

1.83

1.81

1.79

1.77

1.75

1.23

1.21

1.19

1.17

1.15

0

100

200

300

400

0

100

200

300

400

Load Current [mA]

負荷電流[mA]

Load Current [mA]

負荷電流[mA]

Figure 11. Output Voltage vs Load Current

Figure 12. Output Voltage vs Load Current

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Typical Performance Curves – continued

14

12

10

8

7

6

5

4

3

2

1

0

6

4

2

0

0.5

1

1.5

2

2.5

3

-40 -20

0

20

40

60

80 100

GCTL Voltage [V]

GCTL電圧[V]

Temperature [°C]

温度[℃]

Figure 13. SCP Source Current vs

Temperature

Figure 14. LSO1 Voltage vs GCTL Voltage

14

12

10

8

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0%

V_PVCC=12V

6

4

2

0

0.5

1

1.5

2

2.5

3

100

300

500

700

900

CPPCTL Voltage [V]

CPPCTL電圧[V]

Load Current [mA]

負荷電流[mA]

Figure 15. VGH Voltage vs CPPCTL Voltage

Figure 16. Frequency vs Load Current

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Typical Performance Curves – continued

100%

90%

80%

V_PVCC=12V

70%

60%

50%

40%

30%

20%

10%

0%

100

300

500

700

900

Load Current [mA]

負荷電流[mA]

Figure 17. Frequency vs Load Current

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Typical Waveforms

(Unless otherwise noted, Ta=25°C)

INP

5.0[V/div]

VCOM

5.0[V/div]

400[ns/div]

Figure 18.

VCOMAMP slew rate

Figure 19.

VCOMAMP slew rate

DAC resistor 3FFh→000h

DAC resistor 000h→3FFh

OUT0

5.0[V/div]

OUT0

5.0[V/div]

400[ns/div]

Figure 20.

DAC slew rate

Figure 21. DAC slew rate

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Typical Waveforms – continued

VGH

VLS

PVCC 12V

OUT0

OUT2

PVCC 12V

VLS,HVLDO

VDD

OUT1

OUT3

LVLDO

VGL

2.0[ms/div]

Figure 22. Startup sequence1

Figure 23. Startup sequence2

VLS(AC)

200[mV/div]

FB1

1.0[V/div]

Load current

500[mA/div]

VLS

10[V/div]

4.0[ms/div]

4.0[µs/div]

Figure 24. VLS OVP operation

Figure 25. Step-up DC/DC transient response

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Typical Waveforms – continued

VDD(AC)

200[mV/div]

CTL

2.0[V/div]

Load current

500[mA/div]

COM

10[V/div]

10[µs/div]

4.0[µs/div]

Figure 26. Step-down DC/DC transient response

Figure 27. Gate shading waveform

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Description of Operation of Each Block and Procedure for Selecting Application Components

(1)

Step-up DC/DC Converter Block

PVCC1

M1

3.3V

200kO

GCTL

LSO1

SW1

Load SW

Control

VDD_DET

Cgct1

VLS_DET

OCP

REF×0.9

VLS

REF

ERR

PWM

DRV

PGND1

Soft

Start

OVP

HVCC

FB1

R11

R12

C13

COMP1

Rcp

Ccp

Figure 28. Step-up DC/DC Converter Block

Step-up DC/DC block is able to set output voltage by an external feedback resistor R11, R12.

Output voltage VLS is calculated by equation below.

R11 R12

VLS  1.0

R12

Also, OVP function is incorporated for protecting output voltage overshoot, so that if VLS voltage overshoots over

19V(Typ), prevents over voltage output by stopping switching.

(1.1)

Startup sequence

After step-down DC/DC converter startup, Start-up sequence is fixed to start up.

When Step-down DC/DC(3.3V output) reaches 90% of the set voltage, step-up DC/DC will start operation.

Soft start function is incorporated (About 1.5ms typ) in order to prevent overshooting during startup.

Also, controlling the startup timing of load switch (M1) by GCTL pin enables to control the VLS rising sequence.

For the startup timing of load switch (M1), there are two patterns: Use or Not use the GCTL pin.

①

Case of Not using GCTL pin（Connect GCTL pin to OPEN or 3.3V.）

When disuse GCTL pin, if step-down DC/DC output (VDD) reach 90% of the configured voltage, load switch (M1)

turns ON.

VIN(12V)

VDD (3.3V)

GCTL

M1 Gate

VLS

tld

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・Setting of load switch (M1) ON delay time (tld)

②

Case of using GCTL pin

Using GCTL pin makes it possible to have ON timing of load switch (M1) can be delayed more than not using

GCTL pin.

There are two methods for setting delay time by GCTL pin: Set the timing by inputting H/L logic signal to GCTL

pin, or Set by constant time by inserting capacitor to GCTL pin.

When setting the PGATE ON timing by constant time, ON delay time Tgctl is determined by the equation below.

VREF Vth

Tgctl  Cgctl・Rgct・In

VREF

3.31.6

3.3

 Cgctl・200k・In

VIN(12V)

VDD (3.3V)

■ About GCTL delay time fluctuation

Tgctl

GCTL

The rgdt1 has variation in current and voltage of ±50%

that includes absolute variations and temperature

characteristic, design systems with sufficient margin.

M1 Gate

VLS

tld

(1.2)

Selecting the output L constant

The inductance L to be used for output is determined by the rated current I_LRand the maximum input current value I_INMAXof the

inductor.

IL

⊿IL

IINMAX+

should not reach the rated value level.

2

ILR

IINMAX mean current

⊿IL

t

Figure 29. Coil Current Waveform (Step-up DC/DC Converter)

Make adjustments so that I_INMAX+ΔI_L/ 2 will not reach the rated current I_LR.At this time, ΔI_Lis obtained by the following equation.

1

ΔI_L V_CC

L

V_OV_CC

1



[A]

V_O

f

wherein f ： Switching frequency

In addition, since the coil L value may have variations in the range of approximately ±30%, set this value with sufficient margin.

If the coil current exceeds the rated current I_LR, the internal IC element may be damaged because of Large – current.

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(1.3)

Output capacitor setting

For capacitor C_Oto be used for output, set it to the permissible value of the ripple voltage VPP or that of the drop voltage at the time

of a sudden load change, whichever is large.

The output ripple voltage is obtained by the following equation.

1

V_CC

ΔI_L

ΔVPP  I_LMAX R_ESR





(I_LMAX



)

fC_O

V_O

2

Make this setting so that the voltage will fall within the permissible ripple voltage range.

For the drop voltage VDR during a sudden load change, estimate the VDR with the following equation.

ΔI

VDR 

10sec [V]

C_O

Wherein, 10 μsec is the estimate of DC/DC response speed. Set C_Oso that these two values will fall within the limit values.

Since the DC/DC converter causes a peak current to flow between input and output, capacitors must also be

mounted on the input side. For this reason, it is recommended to use low-ESR capacitors above 10μF and below

100mΩ as the input capacitors. Using input capacitors outside of this range may superimpose excess ripple voltage upon the input

voltage, causing the IC to malfunction.

However, since the aforementioned conditions vary with load current, input voltage, output voltage, inductor value,

and switching frequency, be sure to verify the margin using the actual product.

(1.4)

Output rectifier diode setting

For the rectifier diodes to be used as the output stage of the DC/DC converter, it is recommended to use Schottky

diodes. Select diodes with careful attention paid to the maximum inductance current, maximum output voltage, and

power supply voltage.

ΔI

L

Maximum inductance current: IINMAX ＋

< Rated current of diode

2

Maximum output voltage: VOMAX < Rated voltage of diode

In addition, since each parameter has variation in current and voltage of 30% to 40%, design systems with sufficient

margin.

(1.5)

Phase compensation setting

Phase setting procedure

The following conditions are required to ensure the stability of the negative feedback system.

・When the gain is set to “1” (0 dB), the phase leg should not be more than 150°

(i.e., phase margin should not be less than 30°).

In addition, since DC/DC converter applications are sampled according to the switching frequency, the overall system

GBW should be set to not more than 1/10 of the switching frequency. The targeted characteristics of the applications

can be summarized as follows.

・When the gain is set to “1” (0 dB), the phase lag should not be more than 150° (i.e., phase margin should not be

less than 30°).

・The GBW at that time (i.e., frequency when the gain is set to “0 dB”) should not be more than 1/10 of the switching

frequency.

The responsiveness is determined by the GBW limitation. Consequently, to raise the responsiveness, higher

switching frequencies are required.

To ensure the stability through the phase compensation, it is necessary to cancel the secondary phase delay (-180°)

caused by LC resonance with the secondary phase lead (in other words, by adding two phase leads).

The GBW (i.e., frequency when the gain is set to “0 dB”) is determined by phase compensation capacitance

connected to the error amplifier. If GBW needs to be reduced, increase the capacitance of the capacitor.

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Open loop characteristics of integrator

( i ) Ordinary integrator(Low-pass filter)

( ii ) Open loop characteristics of integrator

(a)

-20dB/decade

A

0

Gain

[dB]

GBW(b)

f

COMP

Feedback

A

0

R

Phase

[deg]

-90°

-90

C

Phase margin

-180°

-180

f

Figure 30

Figure 31

1

Point(a) fa 

[Hz]

Point(b) fb  GBW 

[Hz]

2RCA

2RC

Since the phase compensation like that shown in (a) and (b) applies to the error amplifier, it will act as a low-pass

filter.

For DC/DC converter applications, R represents feedback resistors connected in parallel.

According to the LC resonance of the output, two phase leads should be added.

Vo

R3

1

LC resonant frequency fp 

[Hz]

R1

R2

2 LC

C1

1

COMP

Rcp

Phase lead fz1 

Phase lead fz2 

[Hz]

2R1C1

1

A

[Hz]

2RcpCcp

Ccp

Figure 32

Set the lead frequency of one of the phases close to the LC resonant frequency for the purpose of canceling the LC

resonance.

Note: If high-frequency noise occurs in output, it will pass through capacitor C1 and affect the feedback. To avoid this problem, add resistor R3 of

approximately 1kΩ in series with capacitor C1.

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(2)

Step-down DC/DC block

REG5

BOOT

PVCC

DET

VDD_DET

REF×0.9

REF

Cboot

PVCC2

SW2

VDD(3.3V)

PWM

DRV

ERR

CO

Rcp

Ccp

PGND2

VDD_S

Soft

Start

OCP

R23

C23

R21

R22

Figure 33. Step-down DC/DC

Step-down DC/DC block incorporates feedback resistor, and output voltage is 3.3V(TYP) fixed.

Also, built-in error amp (ERR) phase compensation (Rcp,Ccp) minimizes the external components.

(2.1)

Startup sequence

After VIN12V startup, step-down DC/DC starts up with UVLO cancellation as trigger.

Soft start function (about 2ms Typ) is built in to limit overshooting while startup.

(2.2)

Selecting the output L constant

The inductor to be used for output is determined by the rated current I_LRand the maximum input current value I_OMAXof the inductor.

IL

I_OMAX+

^⊿ILshould not reach the rated value level.

2

ILR

I_OMAXmean current

⊿IL

t

Figure 34. Inductor Current Waveform Step-down DC/DC)

Make adjustments so that I_OMAX+ ΔI_L/ 2 will not reach the rated current I_LR.At this time, ΔI_Lis obtained by the following equation.

1

V_O

1

ΔI_L (V_CCV_O)



L

V_CC

f

Wherein f：Switching frequency

In addition, sine the inductor Lvalue may have variations in the range of approximately ±30%, set this value with sufficient margin.

If the inductor current exceeds the rated current I_LR, the internal IC element may be damaged because of large rush current.

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(2.3)

Selecting I/O capacitors

To select I/O capacitors, refer to information in Section (1.3).

However, the output ripple voltage of the step-down DC/DC converter is calculated by the following equation.

ΔI_LV_O



1

ΔV_PPΔI_L R_ESR





[V]

2C_OV_CC

f

Cboot is a flying capacitor in bootstrap circuit for driving high side switch. 0.1µF is recommended.

(3)

HV_LDO block

REF×0.9

DET

HVLDO_DET

HVCC

REF

VLDO(15.2V)

ERR

LDO_H

FBLD

CO

R31

R32

Figure 35. HV_LDO block

(3.1)

Selecting I/O capacitors

The HV_LDO is ceramic capacitor compatible.

Capacitance in the range of 4.7µF to 10µF is recommended.

(3.2)

Output voltage setting

Output voltage is variable output by the external resistor R31,R32.

Output voltage HVLDO is calculated by the equation below.

R31 R32

HVLDO  1.0

R32

(3.3)

Startup sequence

After under voltage protection for VCC release, starts up with HVCC startup.

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(4)

LV_LDO block

REF×0.9

REF

DET

LVLDO_DET

VDD_S

LVLDO

LVLDO(1.8/1.5/1.2V)

CO

ERR

R41

R42

LVCTL

Figure 36. LV_LDO block

(4.1)

Selecting I/O capacitors

LV_LDO is ceramic capacitor compatible.

Capacitance in the range of 4.7µF to 10µF is recommended.

(4.2)

Output voltage setting

Output voltage is switching output by LVCTL pin.

Where LVCTL pin=VIN(PVCC1,2)、

Where LVCTL pin=M（OPEN）、

Where LVCTL pin= GND、

LVLDO output = 1.2[V]

LVLDO output = 1.8[V]

LVLDO output = 1.5[V]

(4.3)

Startup sequence

After under voltage protection for VCC release, starts up with VDD startup.

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(5)

Charge pump block

HVCC

CIN

HVCC

VGH

CO

VREF

(3.3V)

OCP

OVP

CPD2

CPPCTL

CPD1

HVCC

CCPP1

CLK

LVS

C53

CPP1

CCPP2

CPGND

HVCC

COUNTER VGL DET

2ms(typ)

PG

CPP2

REF

COUNTER

2ms(typ)

ERR

CPGND

R51

DET

R52

REF×0.8

VGH_DET

R53

CPGND

Figure 37. Positive charge pump block

HVCC

CIN

HVCC

CLK

DET VLS

HVCC UVLO

GCTL

CCPN

VGL

CPN

LVS

CO

REG2

(1.5V)

REF

ERR

CPGND

R62

R61

VGL_S

DET

REF×0.8

VGL_DET

C63

R63

Figure 38. Negative charge pump block

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The charge pump block starts operation, when it reaches 90% of Boost DC/DC output, GCTL=High and cancels

HVCC low voltage protection. The startup sequences are internally fixed. First, negative-side charge pump starts

operation. Next, when the negative-side charge pump reaches 80% of the set voltage, after 2ms (typ), the

positive-side charge pump will start operation. When both negative and positive-side charge pumps reach 80% of the

set voltage, after 2ms (typ), the power-good signal outputs from the CPPG pin.

The positive-side charge pump have an overvoltage protection function that turns off HVCC-side load switch and

prevents overshoot of output voltage, When VGH voltage reaches 37.5V (typ).

(5.1)

Selecting output diodes

Select Schottky diodes having a current capability two times (negative side) as high as the maximum output current

and a withstand voltage higher than the output voltage.

Due to the aforementioned requirements, it is recommended to use the RB550EA dual Schottky barrier diode.

(5.2)

Selecting output capacitors

CCPP1,CCPP2,CCPN is flying capacitor. A capacitance in the range of 0.01µF to 1µF is recommended.

CO serves as charge pump output capacitors; a capacitance in the range of 0.47µF to 10µF is recommended.

(5.3)

Output voltage setting

Positive charge pump output VGH is 35.2V(TYP) fixed output.

Negative charge pump output VGL is -6V(TYP) fixed output.

(6)

Gate shading block

Gate shading block activates when positive charge pump output (VGH) is over 80%, CTL logic comes in.

Inside FET M1 turns ON and FET M2 turns OFF when positive charge pump output (VGH) is below 80%.

When CTL logic is LOW, inside FET M1 turns ON and M2 turns OFF.

When CTL logic is HIGH, inside FET M1 turns OFF and M2 turns ON. While M2 turns ON, if DRN pin voltage

reaches ten times of a voltage inputting to THR, M2 turns OFF.

VGH

M1

LVS

CTL

COM

DRN

M2

VGH_DET

100kO

LVS

9R

REF

R

THR

Figure 39. Gate shading block

VGH voltage under 80%

VGH voltage over 80%

CTL logic

FET M1

ON

FET M2

OFF

FET M1

ON

FET M2

OFF

L

H

ON

OFF

ON

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Common amplifier

VCOM operates in the range of 0.1V to HVCC-0.8V(TYP). Normally, use the VCOM amplifier as a buffer type

amplifier as shown in (a).

Use the output voltage of the HVLDO block for power supply on the reference side.

To increase the current drive capability, use the PNP and NPN transistors as shown in (b).

When the VCOM amplifier is not used, set the block to the buffer type as shown in (a) and ground the INP pin.

In this case, it is recommended to set the RCOM1 and RCOM2 resistors in the range of 10kΩ to 100kΩ .

Setting them to not more than 10kΩ may increase current consumption, thus resulting in degraded power efficiency.

Setting them to not less than 100kΩ may result in higher offset voltage due to the input bias current of 0.1µA (Typ).

(a)

(b)

HVLDO

RCOM1

RCOM2

RCOM1

RCOM2

30kΩ

INP

VCOM

INN

1000pF

VCOM

Vo1

RCOM3

1kΩ

Figure 40. VCOM

RCOM2

VCOM 

 HVLDO

RCOM1 RCOM2

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(7)

DAC block

The serial data control block consists of a register that stores data from the SDA, SCL pins, and a DAC circuit that

receives the output from this register and provides adjusted voltages to other IC blocks.

REGISTER 0

REGISTER 1

REGISTER 2

REGISTER 3

DAC

×4

OUT0

OUT1

OUT2

OUT3

SDA

Acknowledge

Shift resistor

SCL

Figure 41. Serial block

・

Output Voltage setting mode

Writes to a register address specified by I²C BUS.

For writing mode from I²C BUS to register, there are (ⅰ)Single mode , (ⅱ)Multi mode.

On single mode, write data to one designated register.

On multi mode, as a start address register specified in the second byte of data entry by multiple data write can

be performed continuously.

Single mode or multi mode can be configured by having or not having “stop bit”.

(i). Single mode timing chart

Write single DAC register. R3-R0 specify DAC address.

start

Device Address

Write Ackn Start DAC address pointer. R6-R2 have no meaning Ackn DAC(pointer) MSbyte. D15-D10 have no meaning Ackn

DAC(pointer) LSbyte.

Ackn

Stop

SCL

A6

A5

A4

A3

A2

A1

A0 R/W Ackn WS

R6

R5

R4

R3

R2

R1

R0 Ackn D15 D14 D13 D12 D11 D10 D9

D8 Ackn D7

D6

D5

D4

D3

D2

D1

D0 Ackn

SDA_in

Device_Out

The whole DAC Register D9-D0 is

update in this moment.

(ii). Multi mode timing chart

Write multiple DAC registers. R3-R0 specify start DAC

address

start

Device Address

Write Ackn Start DAC address pointer. R6-R2 have no meaning Ackn DAC(pointer) MSbyte. D15-D10 have no meaning Ackn

DAC(pointer) LSbyte.

Ackn

・・・

SCL

SDA_in

A6

A5

A4

A3

A2

A1

A0 R/W Ackn WS

R6

R5

R4

R3

R2

R1

R0 Ackn D15 D14 D13 D12 D11 D10 D9

D8 Ackn D7

D6

D5

D4

D3

D2

D1

D0 Ackn

・・・

Device_Out

The whole DAC Register D9-D0 is

update in this moment.

DAC(3) MSbyte. D15-D10 have no meaning

Ackn

DAC(3) LSbyte.

Ackn

Stop

・・・

D15 D14 D13 D12 D11 D10 D9

D8 Ackn D7

D6

D5

D4

D3

D2

D1

D0 Ackn

The whole DAC Register D9-D0 is

update in this moment.

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Resistor address

BIT

Register name

DATA0

Initial value Output pin

R1

R0

7

X

6

X

5

X

4

X

3

X

2

X

1

0

D9 D8

Register

0

02C5h

0230h

01EDh

014Dh

OUT0

OUT1

OUT2

OUT3

DATA1 D7 D6 D5 D4 D3 D2 D1 D0

DATA0 D9 D8

DATA1 D7 D6 D5 D4 D3 D2 D1 D0

DATA0 D9 D8

DATA1 D7 D6 D5 D4 D3 D2 D1 D0

DATA0 D9 D8

DATA1 D7 D6 D5 D4 D3 D2 D1 D0

X

Register

0

1

0

1

X

Register

2

X

Register

3

DATA0：Upper 8 bits, DATA1：Lower 8 bits, X：don’t care, D9 to D0：Data bit

REGISTER ADDRESS

Device addresses A6 to A0 are specific to the IC and should be set as follows: （A6 to A0）=1110101.

The lower 2 bits (R1 to R0) of the second byte are used to store the register address. R6 to R2 should be set to

0 as usual.

・

Command interface

Use I²C BUS for command interface with host. Writing or reading by specifying 1 byte select address, along with

slave address. I²C BUS Slave mode format is shown below.

MSB

LSB

MSB

LSB

MSB

LSB

S

Slave Address

A

Select Address

A

DATA

A

P

S

:

Start condition

After slave mode (7bit),, with read mode (H) or light mode (L), send 8 bit data in all.

Acknowledge Added acknowledge bit per byte in sending and receiving data.

Slave Address :

A

:

If the data is sent/ received properly, ”L” is send/receives.

Sending/ Receiving ”H” means lack of acknowledge.

Use 1 byte select address.

Select Address :

DATA

P

:

Data byte. Sending/ Receiving data（MSB first）

Stop condition

The case where writing 3FCh to DAC1（Single mode）

S

Slave Address

EAh

A

Select Address

01h

A

Register1 DATA0

03h

A

Register1 DATA1

FCh

A

P

(ex.)

: Slave from master

Master from slave

The case where writing 3FCh from DAC0 to DAC3 (Multi mode)

Register

0

Register

Register1 to 3

A

Slave Address

Select Address

0

1

S

A

P

DATA0,DATA1

DATA0

DATA1

DATA0

(ex.)

EAh

00h

03h

FCh

03h

: Slave from master

Master from slave

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・

I²C Timing

tHIGH

tR

tF

SCL

tLOW

tPD

tHD:STA

tSU;DAT

tHD;DAT

SDA

(IN)

tBUF

tDH

SDA

(OUT)

SCL

SDA

tSU;STA

tHD;STA

tSU;STO

tl

S：START bit

P：STOP bit

S

P

・

Timing regulation

Parameter

FAST mode

Symbol

Unit

MIN

TYP

MAX

SCL Frequency

SCL ”H” Time

SCL ”L” Time

Rise Time

f_SCL

t_HIGH

t_LOW

t_R

-

0.6

1.2

-

400

kHz

µs

ns

µs

-

0.3

Fall Time

t_F

-

0.3

Start Condition Holding Time t_HD;STA

0.6

100

-

Start Condition Setup Time

SDA Holding Time

t_SU;STA

t_HD;DAT

t_SU;DAT

t_PD

-

SDA Setup Time

-

Acknowledge Delay Time

Acknowledge Holding Time

Stop Condition Setup Time

BUS Open Time

0.9

t_DH

-

0.1

-

t_SU;STO

t_BUF

0.6

1.2

-

Noise Spike Width

t_l

0.1

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・

Buffer output setting

The relation between buffer output voltage (OUT0 to OUT3) and DAC setting value is shown below.

DAC setting value 1

Output voltage (OUT0 to OUT3) 

 HVLDO

1024

Buffer output terminals OUT0 to OUT3 output after UVLO release of HVCC.

While UVLO detection, the output is HiZ.

(8)

Common block

UVLO function

(8.1)

When VCC is below 8.0V(TYP), UVLO function activates and be canceled when VCC is over 8.4V(TYP).

(8.2) SCP function

5uA

SCP

LATCH

1.5V

CSCP

Figure 42. SCP

The SCP function protects against short-circuits in the outputs of the step-up DC/DC converter, step-down DC/DC

converter, HV_LDO, LV_LDO and charge pump blocks. When any one of these outputs falls below 60% of the set

voltage, it will be regarded as a short-circuit in output, thus activating the short-circuit protection function.

If a short-circuit is detected, source current of 5 μA (Typ) will be output from the SCP pin. Then, delay time will be set

with external capacitance. When the SCP pin voltage exceeds 1.5V (Typ), the state will be latched to shut down all

outputs. Once the state has been latched, it will not be canceled unless VCC restarts. The delay time setting is

obtained by using the following equation.

C_SCP1.5

TL[s] 

510^6

Even if none of the output startup sequences is complete at startup of the IC, short-circuits will be detected and the

SCP function activated. For this reason, set the delay time substantially longer than the startup time.

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I/O Equivalent Circuits

3.CPPCTL

5.VGL_S

6.CPN

7.CPP1 8.CPP2

HVCC

PVCC1

1.5V

VREF

10.CPD2

11.CPD1

13.COM

HVCC

VGH

14.DRN

15.CTL

16.THR

VGH

VREF

PVCC1

17.VCOM

18.INN 19.INP

20.HVLDO

HVCC

21.FBLD1

23.SCP

24.OUT0 25.OUT1

26.OUT2 27.OUT3

PVCC

HVCC

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I/O Equivalent Circuits - Continued

29.SDA

30.SCL

31.LVLDO

35.SW2

39.PG

VDD

32.REG5

34.GCTL

PVCC1

PVCC2

VREF

37.BOOT

38.LVCTL

PVCC1

REG5

SW2

41.FB1

42.COMP1

45.SW1 46.SW1

PVCC1

47.LSO1 48.LSO1

PVCC1

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Operational Notes

1.

2.

Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power

supply pins.

Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the

digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog

block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and

aging on the capacitance value when using electrolytic capacitors.

3.

4.

Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.

Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5.

Thermal Consideration

Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may

result in deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the

board size and copper area to prevent exceeding the maximum junction temperature rating.

6.

7.

Recommended Operating Conditions

These conditions represent a range within which the expected characteristics of the IC can be approximately

obtained. The electrical characteristics are guaranteed under the conditions of each parameter.

Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may

flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power

supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring,

and routing of connections.

8.

9.

Operation Under Strong Electromagnetic Field

Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.

Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may

subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply

should always be turned off completely before connecting or removing it from the test setup during the inspection

process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during

transport and storage.

10. Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)

and unintentional solder bridge deposited in between pins during assembly to name a few.

11. Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small

charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and

cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the

power supply or ground line.

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Operational Notes – continued

12. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should

be avoided.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure 43. Example of monolithic IC structure

13. Thermal Shutdown Circuit(TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always

be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction

temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below

the TSD threshold, the circuits are automatically restored to normal operation.

Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no

circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from

heat damage.

14. Over Current Protection Circuit (OCP)

This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This

protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should

not be used in applications characterized by continuous operation or transitioning of the protection circuit.

15. DC/DC switching line wiring pattern

DC/DC converter switching line (wiring from switching pin to inductor, Nch MOS) should be connected with short and

wide wiring. If the wiring is long, ringing by switching would increase. That may cause excess voltage of absolute

maximum ratings. If the wiring is obliged to lengthen by parts location limits, please consider inserting snubber circuit.

16. Discontinuous mode

The step-up and step-down DC/DC converters used in this IC have been designed on the assumption that the

converters are used in continuous mode. Using the IC constantly while in discontinuous mode may result in

malfunctions. To avoid this problem, make coil adjustments or insert a resistor between output and GND to prevent

the IC from entering discontinuous mode while in use.

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Ordering Information

B

D

8

1

7

4

M U V -

E 2

Part number

Package

MUV: VQFN048V7070

Packaging and forming specification

E2: Embossed tape and reel

Marking Diagram

VQFN048V7070 (TOP VIEW)

Part Number Marking

BD8174MU

LOT Number

1PIN MARK

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Physical Dimension, Tape and Reel Information

Package Name

VQFN048V7070

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Revision History

Date

Revision

001

Changes

17.Feb.2016

New Release

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Notice

Precaution on using ROHM Products

1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,

OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you

intend to use our Products in devices requiring extremely high reliability (such as medical equipment ^{(Note 1)}, transport

equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car

accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or

serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.

Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any

damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific

Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are designed and manufactured for use under standard conditions and not under any special or

extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any

special or extraordinary environments or conditions. If you intend to use our Products under any special or

extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of

product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of

flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning

residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PGA-E

Rev.003

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PGA-E

Rev.003

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