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产品型号BD9012KV的Datasheet PDF文件预览

TECHNICAL NOTE  
Large Current External FET Controller Type Switching Regulator  
Dual-output, high voltage,  
high-efficiency step-down  
switching controller  
BD9012KV  
Overview  
The BD9012KV is a 2-ch synchronous controller with rectification switching for enhanced power management efficiency. It  
supports a wide input range, enabling low power consumption ecodesign for an array of electronics.  
Features  
1) Wide input voltage range: 4.5V to 30V  
2) Precision voltage references: 0.8V±1%  
3) FET direct drive  
4) Rectification switching for increased efficiency  
5) Variable frequency: 250k to 1200kHz (external synchronization to 1200kHz)  
6) Built-in selected auto remove over current protection  
7) Built-in independent power up/power down sequencing control  
8) Make various application , step-down , step-up and step-up-down  
9) Small footprint packages: VQFP48C  
Applications  
Car audio and navigation systems, CRTTVLCDTVPDPTVSTBDVDand PC systemsportable CD and DVD players,  
etc.  
Absolute Maximum Ratings (Ta=25)  
Parameter  
Symbol  
VCC  
Parameter  
Symbol  
Limits  
34 *1  
Unit  
V
Limits  
Unit  
V
VCC Voltage  
VREG33 Voltage  
VREG33  
SS1,2FB1,2  
EXTVCC Voltage  
EXTVCC  
SS1,2FB1,2  
34 *1  
V
Voltage  
VREG5  
VCCCL1,2 Voltage  
CL1,2 Voltage  
VCCCL1,2  
CL1,2  
COMP1,2 Voltage  
DET1,2 Voltage  
COMP1,2  
DET1,2  
RTSYNC  
Pd  
34  
34  
V
V
V
V
SW1,2 Voltage  
SW1,2  
RTSYNC Voltage  
Power Dissipation  
34 *1  
40 *1  
BOOT1,2 Voltage  
BOOT1,2  
1.1 *2  
W
BOOT1,2-SW1,2  
Voltage  
BOOT1,2  
-SW1,2  
Operating  
Temperature Range  
Storage Temperature  
Range  
Maximum Junction  
Temperature  
Topr  
Tstg  
Tj  
7 *1  
VCC  
7 *1  
V
V
V
-40 to +105  
STB, EN1,2 Voltage  
VREG5,5A Voltage  
STB, EN1,2  
VREG5,5A  
-55 to +150  
+150  
*1 Regardless of the listed rating, do not exceed Pd in any circumstances.  
*2 Pd de-rated at 7mW/for temperature above Ta=25, Mounted on PCB 70mm×70mm×1.6mm.  
Apr.2008  
Operating conditions (Ta=25)  
Parameter  
Symbol  
EXTVCC  
VCC  
Min.  
4.5 *1  
4.5 *1  
4.5  
Typ.  
12  
12  
5
Max.  
30  
Unit  
V
*2  
*2  
Input voltage 1  
Input voltage 2  
30  
V
BOOTSW voltage  
Carrier frequency  
BOOTSW  
OSC  
VREG5  
1200  
1200*3*4  
60  
V
250  
300  
-
kHz  
kHz  
Synchronous frequency  
Synchronous pulse duty  
Min OFF pulse  
SYNC  
OSC  
40  
-
Duty  
50  
150  
TMIN  
-
nsec  
This product is not designed to provide resistance against radiation.  
*1 After more than 4.5V, voltage range.  
*2 In case of using less than 6V, Short to VCC, EXTVCC and VREG5.  
*3 Please do not exceed OSC×1.5.  
*4 Do not do such things as switching over to internal oscillating frequency while external synchronization frequency is used.  
Electrical characteristics (Unless otherwise specified, Ta=25VCC=12V STB=5V EN1,2=5V)  
Limit  
Parameter  
Symbol  
Unit  
Conditions  
Min.  
Typ.  
6
Max.  
10  
VIN bias current  
Shutdown mode current  
Error Amp Block]  
IIN  
-
-
mA  
IST  
0
10  
μA  
VSTB=0V  
VOB  
0.792  
0.784  
0.800  
0.800  
0.808  
0.816  
V
V
Feedback reference voltage  
Feedback reference voltage  
VOB+  
Ta=-40 to 105℃ ※  
(Ta=-40 to 105)  
Open circuit voltage gain  
VO input bias current  
Oscillator]  
Averr  
IVo+  
-
-
46  
-
-
dB  
1
μA  
Carrier frequency  
FOSC  
Fsync  
900  
-
1000  
1200  
1100  
-
kHz  
kHz  
RT=27 kΩ  
Synchronous frequency  
Over Current Protection Block]  
CL threshold voltage  
RT=27 kΩ,SYNC=1200kHz  
Vswth  
70  
67  
90  
90  
110  
113  
V  
V  
CL threshold voltage  
Ta=-40 to 105℃)  
Vswth+  
Ta=-40 to 105℃ ※  
VREG Block]  
VREG5 output voltage  
VREG33 reference voltage  
VREG5 threshold voltage  
VREG5 hysteresis voltage  
Soft start block]  
VREG5  
VREG33  
4.8  
3.0  
2.6  
50  
5
5.2  
3.6  
3.0  
200  
V
V
IREF=6mA  
3.3  
2.8  
100  
IREG=6mA  
VREG_UVLO  
DVREG_UVLO  
V
VREG:Sweep down  
VREG:Sweep up  
mV  
ISS  
6.5  
6
10  
10  
13.5  
14  
μA  
μA  
VSS=1V  
Charge current  
Charge current  
ISS+  
VSS=1V,Ta=-40 to 105℃ ※  
(Ta=-40 to 105)  
Note: Not all shipped products are subject to outgoing inspection.  
2/16  
Reference data (Unless otherwise specified, Ta=25)  
100  
90  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
6
5
4
3
2
1
0
5.0V  
80  
70  
60  
50  
40  
30  
20  
10  
0
3.3V  
25℃  
105℃  
-40℃  
5.0V  
3.3V  
Io=2A  
Rt=27kΩ  
VIN=12V  
6
9
12  
15  
18  
21  
24  
0
1
2
3
0
10  
20  
30  
IN  
INPUT VOLTAGE : V [V]  
OUTPUT CURRENT:Io[A]  
INPUT VOLTAGE:VIN[V]  
Fig.1 Efficiency 1  
Fig.2 Efficiency 2  
Fig.3 Circuit current  
1100  
1080  
1060  
1040  
1020  
0.816  
0.812  
0.808  
0.804  
0.800  
0.796  
0.792  
0.788  
0.784  
110  
RT=27kΩ  
100  
90  
80  
70  
60  
1000  
980  
960  
940  
920  
900  
-40 -15  
10  
35  
60  
85  
110  
-40 -15 10  
35  
60  
85 110  
-40 -15 10  
35  
60  
85 110  
AMBIENT TEMPERATURETa[℃]  
AMBIENT TEMPERATURE : Ta[℃]  
AMBIENT TEMPERATURE : Ta[℃]  
Fig.4 Reference voltage vs.  
temperature characteristics  
Fig.5 Over current detection vs.  
temperature characteristics  
Fig.6 Frequency vs.  
temperature characteristics  
5.25  
5.00  
4.75  
4.50  
4.25  
4.00  
3.75  
3.50  
3.25  
3.00  
6
5
4
3
2
1
0
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
VREG5  
RCL=15mΩ  
5.0V  
3.3V  
VREG33  
0.0  
0
-40  
-15  
10  
35  
60  
85  
110  
1
2
3
4
5
6
0
5
10  
15  
20  
25  
AMBIENT TEMPERATURE : Ta[℃]  
INPUT VOLTAGE : VIN[V]  
OUTPUT CURRENT : Io[A]  
Fig.7 Internal Reg vs.  
Fig.8 Line regulation  
Fig.9 Load regulation  
temperature characteristics  
6
5
4
3
2
1
50mV/div  
50mV/div  
VOUT  
VOUT  
105℃  
25℃  
-40℃  
IOUT  
0
0
1A/div  
1A/div  
IOUT  
2
4
6
INPUT VOLTAGE:VEN[V]  
Fig.10 EN threshold voltage  
Fig.11 Load transient response 1  
Fig.12 Load transient response 2  
3/16  
Block diagram  
SYNC  
34  
EXTVCC  
41  
STB  
25  
VCC  
7
RT  
33  
5V Reg  
3.3V Reg  
44  
VREG5  
19  
35  
VREG33  
LLM  
B.G  
SYNC  
UVLO  
OCP  
TSD  
TSD  
OSC  
2.7V  
5
8
VCCCL2  
VCCCL1  
3
2
1
10  
11  
12  
CL2  
BOOT2  
OUTH2  
CL1  
OCP  
SW  
BOOT1  
OUTH1  
Set  
Set  
DRV  
DRV  
TSD  
Reset  
Reset  
48  
13  
SW1  
SW2  
SW  
VREG5  
TSD  
UVLO  
LOGIC  
LOGIC  
4(17)  
3(15)  
VREG5A  
OUTL1  
UVLO  
Q
Q
PWM  
COMP  
PWM  
COMP  
46  
Slope  
UVLO  
Slope  
OUTL2  
Reset Set  
Reset  
Set  
2(14)  
DGND1  
47  
39  
37  
DGND2  
FB2  
21  
23  
Err Amp  
FB1  
SS1  
Err Amp  
SS2  
0.8V  
0.8V  
38  
COMP2  
22  
COMP1  
Q
Reset  
Q
Set  
Set  
Reset  
Sequence DET  
Sequence DET  
0.56V  
36  
0.56V  
31  
LOFF  
27  
26  
30  
29  
24  
DET1  
DET2  
EN2 EN1 (GNDS) GND  
Fig-13  
4/16  
Pin configuration  
Pin function table  
Pin  
No.  
Pin name  
Function  
1
2
3
4
5
6
7
OUTH2  
BOOT2  
CL2  
N.C  
VCCCL2  
N.C  
High side FET gate drive pin 2  
OUTH2 driver power pin  
Over current detection pin 2  
Non-connect (unused) pin  
Over current detection VCC2  
Non-connect (unused) pin  
Input power pin  
36 35 34 33 32 31 30 29 28 27 26 25  
VCC  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
SS2  
COMP2  
FB2  
DET1  
SS1  
8
9
VCCCL1  
N.C  
CL1  
Over current detection CC1  
Non-connect (unused) pin  
Over current detection setting pin 1  
OUTH1 driver power pin  
High side FET gate drive pin 1  
High side FET source pin 1  
Low side FET source pin 1  
Low side FET gate drive pin 1  
Non-connect (unused) pin  
FET drive REG input  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
BOOT1  
OUTH1  
SW1  
COMP1  
FB1  
N.C  
DGND1  
OUTL1  
N.C  
EXTVCC  
N.C  
N.C  
VREG33  
N.C  
VREG5A  
N.C  
N.C  
Non-connect (unused) pin  
Reference input REG output  
Non-connect (unused) pin  
Error amp input 1  
VREG33  
N.C  
VREG5A  
N.C  
VREG5  
N.C  
FB1  
COMP1  
SS1  
Error amp output 1  
OUTL1  
DGND1  
SW1  
OUTL2  
DGND2  
SW2  
Soft start setting pin 1  
DET1  
STB  
FB detector output 1  
Standby ON/OFF pin  
EN1  
Output 1 ON/OFF pin  
EN2  
Output 2 ON/OFF pin  
1
2
3
4
5
6
7
8
9
10 11 12  
N.C  
Non-connect (unused) pin  
Ground  
GND  
GNDS  
LOFF  
N.C  
Sense ground  
Test Mode Terminal  
Non-connect (unused) pin  
Switching frequency setting pin  
External synchronous pulse input pin  
Built-in pull-down resistor pin  
FB detector output 2  
RT  
SYNC  
LLM  
Fig-15  
DET2  
SS2  
Soft start setting pin 2  
COMP2  
FB2  
Error amp output 2  
Error amp input 2  
N.C  
Non-connect (unused) pin  
External power input pin  
Non-connect (unused) pin  
Non-connect (unused) pin  
FET drive REG output  
EXTVCC  
N.C  
N.C  
VREG5  
N.C  
Non-connect (unused) pin  
Low side FET gate drive pin 2  
Low side FET source pin 2  
High side FET source pin 2  
OUTL2  
DGND2  
SW2  
Block functional descriptions  
Error amp  
The error amp compares output feedback voltage to the 0.8V reference voltage and provides the comparison result as COMP voltage, which is  
used to determine the switching Duty. COMP voltage is limited to the SS voltage, since soft start at power up is based on SS pin voltage.  
Oscillator (OSC)  
Oscillation frequency is determined by the switching frequency pin (RT) in this block. The frequency can be set between 250kHz and 550kHz.  
SLOPE  
The SLOPE block uses the clock produced by the oscillator to generate a triangular wave, and sends the wave to the PWM comparator.  
PWM COMP  
The PWM comparator determines switching Duty by comparing the COMP voltage, output from the error amp, with the triangular wave from the  
SLOPE block. Switching duty is limited to a percentage of the internal maximum duty, and thus cannot be 100% of the maximum.  
Reference voltage (5Vreg33Vreg)  
This block generates the internal reference voltages: 5V and 3.3V.  
External synchronization (SYNC)  
Determines the switching frequency, based on the external pulse applied.  
Over current protection (OCP)  
Over current protection is activated when the VCCCL-CL voltage reaches or exceeds 90mV. When over current protection is active, Duty is low,  
and output voltage also decreases. When LOFF=L, the output voltage has fallen to 70% or below and output is latched OFF. The OFF latch  
mode ends when the latch is set to STB, EN.  
Sequence control (Sequence DET)  
Compares FB voltage with reference voltage (0.56V) and outputs the result as DET.  
Protection circuits (UVLO/TSD)  
The UVLO lock out function is activated when VREG falls to about 2.8V, while TSD turns outputs OFF when the chip temperature reaches or  
exceeds 150. Output is restored when temperature falls back below the threshold value.  
5/16  
Application circuit example (Parentheses indicate VQFP48C pin numbers)  
VIN(12V)  
100uF  
23m  
1nF  
23m  
Ω
Ω
10  
Ω
0.33  
uF  
100  
100  
Ω
Ω
SP8K2  
SP8K2  
1nF  
RB160  
VA-40  
RB160  
VA-40  
29  
(2)  
28  
(1)  
36  
35  
34  
33  
(8)  
32  
(7)  
31  
30  
(3)  
(12)  
(11)  
(10)  
(5)  
(SLF10145TDK)  
(SLF10145TDK)  
Vo(1.8V/2A)  
0.1  
uF  
OUTH1  
SW1  
OUTH2  
SW2  
0.1  
uF  
10uH  
Vo(2.5V/2A)  
10uH  
1(13)  
2(14)  
27(48)  
RB051  
L-40  
RB051  
L-40  
DGND1  
26(47)  
25(46)  
DGND2  
OUTL2  
VREG5  
3300pF  
43  
3(15)  
4(17)  
15k  
OUTL1  
Ω
1000pF  
510  
k
Ω
30uF  
(C2012JB  
0J106K  
30uF  
150  
Ω
24(44)  
23  
VREG5A  
VREG33  
(C2012JB  
0J106K  
TDK)  
1uF  
1uF  
Ω
5(19)  
6(21)  
TDK)  
1uF  
EXTVCC 22(41)  
FB1  
0.33uF  
330pF  
12k  
Ω
21(39)  
7(22)  
8(23)  
FB2  
COMP1  
SS1  
330pF  
10000pF 1k  
Ω
20k  
Ω
COMP2  
20(38)  
0.1uF  
3.3k  
3300pF  
Ω
9(24)  
SS2 19(37)  
DET1  
STB  
0.1uF  
DET2  
10  
11  
(26)  
12  
13  
14  
15  
16  
17  
18  
(25)  
(27)  
(29)  
(31)  
(33)  
(34)  
(35)  
(36)  
100k  
Ω
Fig-16BStep-DownCout=Ceramic Capacitor)  
There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics.  
Please verify and confirm using practical applications.  
6/16  
Application component selection  
(1) Setting the output L value  
The coil value significantly influences the output ripple current.  
Thus, as seen in equation (5), the larger the coil, and the higher  
the switching frequency, the lower the drop in ripple current.  
ΔIL  
VCC-VOUT×VOUT  
Fig-17  
ΔIL =  
[A]・・5)  
L×VCC×f  
VCC  
I
L
The optimal output ripple current setting is 30% of maximum current.  
VOUT  
Co  
ΔIL = 0.3×IOUTmax.[A]・・6)  
L
VCC-VOUT×VOUT  
L =  
[H]7)  
ΔIL×VCC×f  
Fig-18  
(ΔILoutput ripple current fswitching frequency)  
Output ripple current  
Outputting a current in excess of the coil current rating will cause magnetic saturation of the coil and decrease  
efficiency.  
Please establish sufficient margin to ensure that peak current does not exceed the coil current rating.  
Use low resistance (DCR, ACR) coils to minimize coil loss and increase efficiency.  
(2) Setting the output capacitor Co value  
Select the output capacitor with the highest value for ripple voltage (VPP) tolerance and maximum drop voltage  
(at rapid load change). The following equation is used to determine the output ripple voltage.  
ΔIL  
Vo  
1
f
Step down ΔVPP = ΔIL × RESR +  
×
×
[V]  
Note: fswitching frequency  
Co  
Vcc  
Be sure to keep the output Co setting within the allowable ripple voltage range.  
Please allow sufficient output voltage margin in establishing the capacitor rating. Note that low-ESR capacitors enable  
lower output ripple voltage.  
Also, to meet the requirement for setting the output startup time parameter within the soft start time range, please factor  
in the conditions described in the capacitance equation (9) for output capacitors, below.  
TSS × (Limit – IOUT)  
Tsssoft start time  
Co ≦  
・・・ (9)  
VOUT  
ILimitover current detection value2/16reference  
Note: less than optimal capacitance values may cause problems at startup.  
(3) Input capacitor selection  
VIN  
The input capacitor serves to lower the output impedance of the power  
source connected to the input pin (VCC). Increased power supply output  
impedance can cause input voltage (VCC) instability, and may negatively  
impact oscillation and ripple rejection characteristics. Therefore, be  
certain to establish an input capacitor in close proximity to the VCC and  
GND pins. Select a low-ESR capacitor with the required ripple current  
capacity and the capability to withstand temperature changes without  
wide tolerance fluctuations. The ripple current IRMSS is determined  
using equation (10).  
Cin  
L
VOUT  
Co  
IRMS = IOUT ×  
[A]10)  
VOUTVCC - VOUT)  
VCC  
Also, be certain to ascertain the operating temperature, load range and  
MOSFET conditions for the application in which the capacitor will be used,  
since capacitor performance is heavily dependent on the application’s  
input power characteristics, substrate wiring and MOSFET gate drain  
capacity.  
Fig-19  
Input capacitor  
7/16  
(4) Feedback resistor design  
Please refer to the following equation in determining the proper feedback resistance. The recommended setting is in a range  
between 10kΩ and 330kΩ. Resistance less than 10kΩ risks decreased power efficiency, while setting the resistance value  
higher than 330kΩ will result in an internal error amp input bias current of 0.2uA increasing the offset voltage. Please use it with  
150nsec or more so that there is a possibility that the output becomes unstable when the output pulse width is small.12)  
Vo  
Internal ref. 0.8V  
R8 +R9  
Vo =  
× 0.8 [V] ・・11)  
150ns ・・12)  
R8  
R9  
R9  
FB  
Vo  
1
f
×
Fig-20  
Vin  
(5) Setting switching frequency  
The triangular wave switching frequency can be set by connecting a resistor to the RT 15(33) pin. The RT sets the frequency  
by adjusting the charge/discharge current in relation to the internal capacitor. Refer to the figure below in determining proper  
RT resistance, noting that the recommended resistance setting is between 50kΩ and 130kΩ. Settings outside this range  
may render the switching function inoperable, and proper operation of the controller overall cannot be guaranteed when  
unsupported resistance values are used.  
Fig-21 RT vs. switching frequency  
(6) Setting the soft start delay  
The soft start function is necessary to prevent an inrush of coil current and output voltage overshoot at startup. The figure  
below shows the relation between soft start delay time and capacitance, which can be calculated using equation (12) at right.  
10  
1
0.8V(typ.)×CSS  
TSS =  
[sec]・・・(12)  
ISS(10μA Typ.)  
0.1  
0.01  
0.001  
0.01  
0.1  
SS CAPACITANCE[uF]  
Fig-22 SS capacitance vs. delay time  
Recommended capacitance values are between 0.01uF and 0.1uF. Capacitance lower than 0.01uF may generate output  
overshoots. Please use high accuracy components (such as X5R) when implementing sequential startups involving other  
power sources. Be sure to test the actual devices and applications to be used, since the soft start time varies, depending on  
input voltage, output voltage and capacitance, coils and other characteristics.  
8/16  
(7) Setting over current detection values  
The current limit valueILimitis determined by the resistance of the RCL established between CL and VCCCL.  
VIN  
Over current detection point  
VCCCL  
CL  
IL  
RCL  
IL  
L
Vo  
90m  
RCL  
ILimit =  
[A]・・・(13)  
Fig-23  
Fig-24  
When the current goes beyond the threshold value, the current can be limited by reducing the ON Duty Cycle. When the load  
goes back to the normal operation, the output voltage also becomes back on to the specific level.  
The current limit value  
Vo  
Fig-25  
Io  
(8) Method for determining phase compensation  
Conditions for application stability  
Feedback stability conditions are as follows:  
When gain is 1 (0dB) and phase shift is 150° or less (i.e., phase margin is at least 30°):  
a dual-output high-frequency step-down switching regulator is required  
Additionally, in DC/DC applications, sampling is based on the switching frequency; therefore, overall GBW may be set at no  
more than 1/10 the switching frequency. In summary, target characteristics for application stability are:  
Phase shift of 150° or less (i.e., phase margin of 30° or more) with gain of 1 (0dB)  
GBW (i.e., gain 0dB frequency) no more than 1/10 the switching frequency.  
Stability conditions mandate a relatively higher switching frequency, in order to limit GBW enough to increase response.  
The key to achieving successful stabilization using phase compensation is to cancel the secondary phase margin/delay  
(-180°) generated by LC resonance, by employing a dual phase lead. In short, adding two phase leads stabilizes the  
application.  
GBW (the frequency at gain 1) is determined by the phase compensation capacitor connected to the error amp. Thus, a larger  
capacitor will serve to lower GBW if desired.  
General use integrator (low-pass filter) Integrator open loop characteristics  
(a)  
-20dB/decade  
GBW(b)  
1
A
point (a) fa =  
1.25[Hz]  
Gain  
[dB]
COMP  
2πRCA  
Feedback  
A
R
0
0
1
point (b)fa = GBW  
[Hz]  
FB  
2πRC  
Phase  
[deg]  
-90°  
Phase margin  
-90  
C
-180°  
-180  
Fig-26  
Fig-27  
The error amp is provided with phase compensation similar to that depicted in figures and above and thus serves  
as the system’s low-pass filter.  
In DC/DC converter applications, R is established parallel to the feedback resistance.  
9/16  
When electrolytic or other high-ESR output capacitors are used:  
Phase compensation is relatively simple for applications employing high-ESR output capacitors (on the order of several  
Ω). In DC/DC converter applications, where LC resonance circuits are always incorporated, the phase margin at these  
locations is -180°. However, wherever ESR is present, a 90° phase lead is generated, limiting the net phase margin to -90°  
in the presence of ESR. Since the desired phase margin is in a range less than 150°, this is a highly advantageous  
approach in terms of the phase margin. However, it also has the drawback of increasing output voltage ripple components.  
LC resonance circuit  
ESR connected  
Vcc  
Vcc  
Vo  
Vo  
L
L
1
ESR  
R
C
C
Fig-28  
Fig-29  
resonance point1  
fr =  
[Hz]Resonance Point  
fr =  
[Hz]  
2π√LC  
2π√LC  
1
Resonance point phase margin -180°  
fESR =  
[Hz] :Zero  
2πRESRC  
-90°:Pole  
Since ESR changes the phase characteristics, only one phase lead need be provided for high-ESR applications. Please choose  
one of the following methods to add the phase lead.  
Add C to feedback resistor  
Vo  
Add R3 to aggregator  
Vo  
C2  
A
R3  
C2  
C1  
R1  
R1  
FB  
FB  
COMP  
COMP  
A
R2  
R2  
Fig-30  
Fig-31  
1
1
Phase lead fz =  
[Hz]  
Phase lead fz =  
[Hz]  
2πC1R1  
2πC2R3  
Set the phase lead frequency close to the LC resonance frequency in order to cancel the LC resonance.  
When using ceramic, OS-CON, or other low-ESR capacitors for the output capacitor:  
Where low-ESR (on the order of tens of mΩ) output capacitors are employed, a two phase-lead insertion scheme is  
required, but this is different from the approach described in figure ~, since in this case the LC resonance gives rise  
to a 180° phase margin/delay. Here, a phase compensation method such as that shown in figure below can be  
implemented.  
Phase compensation provided by secondary (dual) phase lead  
Vo  
1
Phase lead fz1 =  
Phase lead fz2 =  
[Hz]  
[Hz]  
R3  
FB  
C2  
C1  
2πR1C1  
1
2πR3C2  
R1  
R2  
A
COMP  
1
LC resonance frequency fr =  
[Hz]  
2π√LC  
Fig-32  
Once the phase-lead frequency is determined, it should be set close to the LC resonance frequency.  
This technique simplifies the phase topology of the DCDC Converter. Therefore, it might need a certain amount  
of trial-and-error process. There are many factors(The PCB board layout, Output Current, etc.)that can affect  
the DCDC characteristics. Please verify and confirm using practical applications.  
10/16  
9MOSFET selection  
VCC  
FET uses Nch MOS  
VDSVcc  
VDS  
IL  
VGSM1BOOT-SW interval voltage  
VGSM2VREG5  
Vo  
VGSM1  
VGSM2  
Allowable currentvoltage current + ripple current  
Should be at least the over current protection value  
Select a low ON-resistance MOSFET for highest efficiency  
VDS  
Fig-33  
The shoot-through may happen when the input parasitic  
capacitance of FET is extremely big or the Duty ratio is less  
than or equal to 10%. Less than or equal to 1000pF input  
parasitic capacitance is recommended. Please confirm  
operation on the actual application since this character is  
affected by PCB layout and components.  
10Schottky barrier diode selection  
VCC  
Reverse voltage VRVcc  
Allowable currentvoltage current + ripple current  
Should be at least the over current protection value  
Select a low forward voltage, fast recovery diode for highest  
efficiency  
Vo  
VR  
Fig-34  
11Sequence function  
Circuit diagram  
Timing chart  
When EN1 stays ”H” and EN2 returns to ”H”, DET1 is in  
open state; thus SS2 is asserted, and Vo2 output starts.  
With EN1, 2 at ”H” level, when EN1 goes ”L”,  
If Vo2 is 76% of the voltage setting or higher, DET2 goes  
Vo1 turns OFF, but Vo2 output continues.  
open and SS1 is asserted, starting Vo1 output.  
VREG5  
VCC VREG5  
EN1  
EN2  
OUTH1 BOOT1 VCC BOOT2 OUTH2  
Vo2  
Vo1  
DET2  
SS1  
SW1  
SW2  
OUTL1  
OUTL2  
DGND2  
DGND1  
FB1  
FB1  
0.61V  
FB2  
COMP1  
COMP2  
Vo1  
over 76%  
SS1  
SS2  
DET1  
SS2  
DET2  
DET1  
STB EN1 EN2 GND  
0.61V  
FB2  
Vo2  
0.56V  
0.56V  
over 70%  
under 70%  
over 76%  
A
With EN1,2 at “H” level, if  
Vo1 starts at 76% or more of  
voltage setting, DET goes  
open and SS1 is asserted,  
starting Vo2 output.  
With EN2 set ”L”, if Vo2  
A
Same as “A” at left  
goes below 70% the voltage  
setting, DET2 shorts and SS1  
is asserted, turning Vo1 OFF  
Fig-35  
Fig-36  
11/16  
Input/Output equivalent circuits  
1348PINSW1SW2)  
211PINBOOT2BOOT1)  
115PINOUTH1OUTH2)  
1447PINDGND1DGND2)  
1546PINOUTL1OUTL2)  
4417PINVREG5VREG5A)  
31PINLOFF)  
VREG5  
BOOT  
OUTL  
DGND  
OUTH  
LOFF  
172.2k  
135.8k  
100k  
SW  
300k  
34PINSYNC)  
2139PINFB1FB2)  
2337PINSS1SS2)  
VREG5  
/ VREG5A  
VREG5  
/ VREG5A  
VREG5  
5k  
2k  
50k  
1k  
SYNC  
SS  
FB  
250k  
1P  
2.5  
100k  
252627PIN  
STBEN1EN2)  
2436PINDET1DET2)  
33PINRT)  
VREG5  
/ VREG5A  
VCC  
VREG5  
STB  
EN  
10k  
RT  
DET  
172.2k  
100k  
135.8k  
310PINCL2CL1)  
58PINVCCCL2VCCCL1)  
35PINLLM)  
VREG5A  
2238PINCOMP1COMP2)  
VCC  
VREG5  
/ VREG5A  
VCCCL  
5k  
20Ω  
VCC  
LLM  
COMP  
5kΩ  
5P  
308k  
5kΩ  
CL  
1k  
41PINEXTVCC)  
44PINVREG5)  
19PINVREG33)  
17PINVREG5A)  
VCC  
VCC  
VCC  
VREG5A  
EXTVCC  
VREG5  
VCC  
150k  
150k  
VREG5A  
VREG33  
746.32k  
746.32k  
255k  
469.06k  
12/16  
Operation notes  
1Absolute maximum ratings  
Exceeding the absolute maximum ratings for supply voltage, operating temperature or other parameters can damage or  
destroy the IC. When this occurs, it is impossible to identify the source of the damage as a short circuit, open circuit, etc.  
Therefore, if any special mode is being considered with values expected to exceed absolute maximum ratings, consider  
taking physical safety measures to protect the circuits, such as adding fuses.  
2GND electric potential  
Keep the GND terminal potential at the lowest (minimum) potential under any operating condition.  
3Thermal design  
Be sure that the thermal design allows sufficient margin for power dissipation (Pd) under actual operating conditions.  
4Inter-pin shorts and mounting errors  
Use caution when positioning the IC for mounting on printed surface boards. Connection errors may result in damage or  
destruction of the IC. The IC can also be damaged when foreign substances short output pins together, or cause shorts  
between the power supply and GND.  
5Operation in strong electromagnetic fields  
Use caution when operating in the presence of strong electromagnetic fields, as this may cause the IC to malfunction.  
6Testing on application boards  
Connecting a capacitor to a low impedance pin for testing on an application board may subject the IC to stress. Be sure to  
discharge the capacitors after every test process or step. Always turn the IC power supply off before connecting it to or  
removing it from any of the apparatus used during the testing process. In addition, ground the IC during all steps in the  
assembly process, and take similar antistatic precautions when transporting or storing the IC.  
7) The output FET  
The shoot-through may happen when the input parasitic capacitance of FET is extremely big or the Duty ratio is less than  
or equal to 10%. Less than or equal to 1000pF input parasitic capacitance is recommended. Please confirm operation on  
the actual application since this character is affected by PCB layout and components.  
8This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.  
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode  
or transistor. Relations between each potential may form as shown in the example below, where a resistor and transistor  
are connected to a pin:  
With the resistor, when GNDPin A, and with the transistor (NPN), when GNDPin B:  
The P-N junction operates as a parasitic diode  
With the transistor (NPN), when GNDPin B:  
The P-N junction operates as a parasitic transistor by interacting with the N layers of elements in proximity to the  
parasitic diode described above.  
Parasitic diodes inevitably occur in the structure of the IC. Their operation can result in mutual interference between circuits,  
and can cause malfunctions, and, in turn, physical damage or destruction. Therefore, do not employ any of the methods  
under which parasitic diodes can operate, such as applying a voltage to an input pin lower than the (P substrate) GND.  
Resistor  
TransistorNPN)  
(PINA)  
(PINB)  
B
C
E
(PINB)  
(PINA)  
C
E
B
P
P
P+  
P+  
P+  
P+  
N
N
N
N
P
N
GND  
Parasitic element  
GND  
P substrate  
GND  
Parasitic element  
Parasitic element or transistor  
Fig-39  
Parasitic element or transistor  
Fig-38  
Fig-37  
9GND wiring pattern  
Fig-40  
When both a small-signal GND and high current GND are present, single-point grounding (at the set standard point) is  
recommended, in order to separate the small-signal and high current patterns, and to be sure voltage changes stemming  
from the wiring resistance and high current do not cause any voltage change in the small-signal GND. In the same way, care  
must be taken to avoid wiring pattern fluctuations in any connected external component GND.  
10In some application and process testing, Vcc and pin potential may be reversed, possibly causing internal circuit or element  
damage. For example, when the external capacitor is charged, the electric charge can cause a Vcc short circuit to the GND.  
13/16  
In order to avoid these problems, limiting output pin capacitance to 100μF or less and inserting a Vcc series countercurrent  
prevention diode or bypass diode between the various pins and the Vcc is recommended.  
Bypass diode  
Countercurrent prevention diode  
Vcc  
Pin  
Fig-41  
11Thermal shutdown (TSD)  
This IC is provided with a built-in thermal shutdown (TSD) circuit, which is designed to prevent thermal damage to or  
destruction of the IC. Normal operation should be within the power dissipation parameter, but if the IC should run beyond  
allowable Pd for a continued period, junction temperature (Tj) will rise, thus activating the TSD circuit, and turning all output  
pins OFF. When Tj again falls below the TSD threshold, circuits are automatically restored to normal operation. Note that  
the TSD circuit is only asserted beyond the absolute maximum rating. Therefore, under no circumstances should the TSD  
be used in set design or for any purpose other than protecting the IC against overheating  
12The SW pin  
When the SW pin is connected in an application, its coil counter-electromotive force may give rise to a single electric  
potential. When setting up the application, make sure that the SW pin never exceeds the absolute maximum value.  
Connecting a resistor of several Ω will reduce the electric potential. (See Fig. 43)  
Vcc  
BOOT  
OUTH  
R
SW  
Vo  
Fig-42  
OUTL  
DGND  
13Dropout operation  
When input voltage falls below approximately output voltage / 0.9 (varying depending on operating frequency) the ON  
interval on the OUTL side MOS is lost, making boost applications and wrap operation impossible. If a small differential  
between input and output voltage is envisioned for a prospective application, connect the load such that the SW voltage  
drops to the GND level. Managing this load requires discharging the SW line capacitance (SW pin capacitance: approx.  
500pF; OUTL side MOS D-S capacitance; Schottky capacitance). Supported loads can be calculated using the equation  
below.  
Output voltage × SW line capacitance  
ILOAD =  
25n  
Note that SW line capacitance is lower with smaller loads, and more stable operation is attained when low voltage bias  
circuits are configured as in the example below (Fig. 44). However, the degree to which line capacitance is reduced or  
operational stability is attained will vary depending on the board layout and components. Therefore, be certain to confirm  
the effectiveness of these design factors in actual operation before entering mass production.  
Vcc  
Vcc  
VREG  
OUT  
Vo  
SW  
OUT  
Fig-43  
14/16  
14Logic of Output  
When each function operates, each output is as follows.  
Function  
EN= L  
OCP  
Upper side FET  
OFF  
OUTH  
Lower side FET  
OUTL  
L
L
L
L
OFF  
ON  
L
H
L
OFF  
UVLO  
TSD  
OFF  
OFF  
OFF  
OFF  
L
15/16  
Power dissipation vs. temperature characteristics  
VQFP48C  
PD(W)  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
1.1W  
0.75W  
0
25 50 75 100 125 150  
AMBIENT TEMPERATORE:Ta [℃]  
①:Stand-alone IC  
②:Mounted on Rohm standard board  
70mm x 70mm x 1.6mm glass-epoxy board )  
Part order number  
B
D
9
0
1
2
K
V
E
2
ROHM part  
code  
Type/No.  
Package type  
KV VQFP48C  
VQFP48C  
<Dimension>  
< Packing information >  
Embossed carrier tape  
Tape  
1500pcs  
Quantity  
Direction  
of feed  
E2  
(The direction is the 1pin of product is at the upper left when you hold  
reel on the left hand and you pull out the tape on the right hand)  
Direction of feed  
1Pin  
Reel  
Unit:mm)  
When you order , please order in times the amount of package quantity.  
16/16  
Appendix  
Notes  
No technical content pages of this document may be reproduced in any form or transmitted by any  
means without prior permission of ROHM CO.,LTD.  
The contents described herein are subject to change without notice. The specifications for the  
product described in this document are for reference only. Upon actual use, therefore, please request  
that specifications to be separately delivered.  
Application circuit diagrams and circuit constants contained herein are shown as examples of standard  
use and operation. Please pay careful attention to the peripheral conditions when designing circuits  
and deciding upon circuit constants in the set.  
Any data, including, but not limited to application circuit diagrams information, described herein  
are intended only as illustrations of such devices and not as the specifications for such devices. ROHM  
CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any  
third party's intellectual property rights or other proprietary rights, and further, assumes no liability of  
whatsoever nature in the event of any such infringement, or arising from or connected with or related  
to the use of such devices.  
Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or  
otherwise dispose of the same, no express or implied right or license to practice or commercially  
exploit any intellectual property rights or other proprietary rights owned or controlled by  
ROHM CO., LTD. is granted to any such buyer.  
Products listed in this document are no antiradiation design.  
The products listed in this document are designed to be used with ordinary electronic equipment or devices  
(such as audio visual equipment, office-automation equipment, communications devices, electrical  
appliances and electronic toys).  
Should you intend to use these products with equipment or devices which require an extremely high level  
of reliability and the malfunction of which would directly endanger human life (such as medical  
instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers  
and other safety devices), please be sure to consult with our sales representative in advance.  
It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance  
of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow  
for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in  
order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM  
cannot be held responsible for any damages arising from the use of the products under conditions out of the  
range of the specifications or due to non-compliance with the NOTES specified in this catalog.  
Thank you for your accessing to ROHM product informations.  
More detail product informations and catalogs are available, please contact your nearest sales office.  
THE AMERICAS / EUROPE / ASIA / JAPAN  
ROHM Customer Support System  
Contact us : webmaster@ rohm.co.jp  
www.rohm.com  
TEL : +81-75-311-2121  
FAX : +81-75-315-0172  
Copyright © 2008 ROHM CO.,LTD.  
21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan  
Appendix1-Rev2.0  
配单直通车
BD9012KV产品参数
型号:BD9012KV
生命周期:Active
IHS 制造商:ROHM CO LTD
零件包装代码:QFP
包装说明:LFQFP,
针数:48
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:5.23
Is Samacsys:N
模拟集成电路 - 其他类型:DUAL SWITCHING CONTROLLER
控制技术:PULSE WIDTH MODULATION
最大输入电压:30 V
最小输入电压:4.5 V
标称输入电压:12 V
JESD-30 代码:S-PQFP-G48
长度:7 mm
功能数量:1
端子数量:48
最高工作温度:105 °C
最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP
封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH
认证状态:Not Qualified
座面最大高度:1.6 mm
表面贴装:YES
切换器配置:PUSH-PULL
最大切换频率:1200 kHz
温度等级:INDUSTRIAL
端子形式:GULL WING
端子节距:0.5 mm
端子位置:QUAD
宽度:7 mm
Base Number Matches:1
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