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    产品型号BF1202WR,135的Datasheet PDF文件预览

    DISCRETE SEMICONDUCTORS  
    DATA SHEET  
    BF1202; BF1202R; BF1202WR  
    N-channel dual-gate PoLo  
    MOS-FETs  
    Product specification  
    2010 Sep 16  
    Supersedes data of 2000 Mar 29  
    NXP Semiconductors  
    Product specification  
    N-channel dual-gate PoLo MOS-FETs  
    BF1202; BF1202R; BF1202WR  
    FEATURES  
    PINNING  
    PIN  
    Short channel transistor with high  
    forward transfer admittance to input  
    capacitance ratio  
    DESCRIPTION  
    3
    4
    1
    2
    3
    4
    source  
    drain  
    Low noise gain controlled amplifier  
    gate 2  
    gate 1  
    2
    1
    Partly internal self-biasing circuit to  
    ensure good cross-modulation  
    performance during AGC and good  
    DC stabilization.  
    Top view  
    MSB035  
    Marking code legend:  
    BF1202R marking code: LE*  
    * = - : made in Hong Kong  
    * = p : made in Hong Kong  
    * = t : made in Malaysia  
    APPLICATIONS  
    Fig.2 Simplified outline  
    (SOT143R).  
    VHF and UHF applications with  
    3 to 9 V supply voltage, such as  
    digital and analogue television  
    tuners and professional  
    communications equipment.  
    4
    3
    3
    4
    page  
    DESCRIPTION  
    Enhancement type N-channel  
    field-effect transistor with source and  
    substrate interconnected. Integrated  
    diodes between gates and source  
    protect against excessive input  
    voltage surges. The BF1202,  
    BF1202R and BF1202WR are  
    encapsulated in the SOT143B,  
    SOT143R and SOT343R plastic  
    packages respectively.  
    1
    2
    2
    1
    Top view  
    MSB014  
    Top view  
    MSB842  
    BF1202 marking code: LD*  
    BF1202WR marking code: LE*  
    Fig.1 Simplified outline  
    (SOT143B).  
    Fig.3 Simplified outline  
    (SOT343R).  
    QUICK REFERENCE DATA  
    SYMBOL  
    PARAMETER  
    drain-source voltage  
    CONDITIONS  
    MIN.  
    TYP.  
    MAX.  
    10  
    UNIT  
    VDS  
    ID  
    V
    drain current  
    30  
    200  
    40  
    2.2  
    30  
    1.8  
    mA  
    mW  
    mS  
    pF  
    Ptot  
    total power dissipation  
    forward transfer admittance  
    input capacitance at gate 1  
    reverse transfer capacitance  
    noise figure  
    yfs  
    Cig1-ss  
    Crss  
    F
    25  
    30  
    1.7  
    15  
    f = 1 MHz  
    fF  
    f = 800 MHz  
    1.1  
    105  
    dB  
    Xmod  
    cross-modulation  
    input level for k = 1% at  
    40 dB AGC  
    100  
    dBV  
    Tj  
    operating junction temperature  
    150  
    C  
    CAUTION  
    This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport  
    and handling.  
    2010 Sep 16  
    2
    NXP Semiconductors  
    Product specification  
    N-channel dual-gate PoLo MOS-FETs  
    BF1202; BF1202R; BF1202WR  
    LIMITING VALUES  
    In accordance with the Absolute Maximum Rating System (IEC 60134).  
    SYMBOL  
    PARAMETER  
    drain-source voltage  
    CONDITIONS  
    MIN.  
    MAX.  
    10  
    UNIT  
    VDS  
    ID  
    V
    drain current  
    30  
    mA  
    mA  
    mA  
    IG1  
    IG2  
    Ptot  
    gate 1 current  
    10  
    10  
    gate 2 current  
    total power dissipation  
    BF1202; BF1202R  
    BF1202WR  
    Ts 113 C; note 1  
    Ts 119 C; note 1  
    200  
    200  
    +150  
    150  
    mW  
    mW  
    C  
    Tstg  
    Tj  
    storage temperature  
    operating junction temperature  
    65  
    C  
    Note  
    1. Ts is the temperature of the soldering point of the source lead.  
    THERMAL CHARACTERISTICS  
    SYMBOL  
    PARAMETER  
    thermal resistance from junction to soldering point  
    BF1202; BF1202R  
    VALUE  
    UNIT  
    Rth j-s  
    185  
    155  
    K/W  
    K/W  
    BF1202WR  
    MCD951  
    250  
    handbook, halfpage  
    P
    tot  
    (mW)  
    200  
    (1)  
    (2)  
    150  
    100  
    50  
    0
    0
    50  
    100  
    150  
    200  
    T
    (°C)  
    s
    (1) BF1202WR.  
    (2) BF1202; BF1202R.  
    Fig.4 Power derating curve.  
    2010 Sep 16  
    3
     
    NXP Semiconductors  
    Product specification  
    N-channel dual-gate PoLo MOS-FETs  
    BF1202; BF1202R; BF1202WR  
    STATIC CHARACTERISTICS  
    Tj = 25 C unless otherwise specified.  
    SYMBOL  
    PARAMETER  
    CONDITIONS  
    MIN. MAX. UNIT  
    V(BR)DSS  
    drain-source breakdown voltage  
    VG1-S = VG2-S = 0; ID = 10 A  
    VG2-S = VDS = 0; IG1-S = 10 mA  
    VG1-S = VDS = 0; IG2-S = 10 mA  
    VG2-S = VDS = 0; IS-G1 = 10 mA  
    VG1-S = VDS = 0; IS-G2 = 10 mA  
    VG2-S = 4 V; VDS = 5 V; ID = 100 A  
    VG1-S = 5 V; VDS = 5 V; ID = 100 A  
    10  
    6
    V
    V(BR)G1-SS gate 1-source breakdown voltage  
    V(BR)G2-SS gate 2-source breakdown voltage  
    V
    6
    V
    V(F)S-G1  
    V(F)S-G2  
    VG1-S(th)  
    VG2-S(th)  
    IDSX  
    forward source-gate 1 voltage  
    forward source-gate 2 voltage  
    gate 1-source threshold voltage  
    gate 2-source threshold voltage  
    drain-source current  
    0.5  
    0.5  
    0.3  
    0.3  
    8
    1.5  
    1.5  
    1.0  
    1.2  
    16  
    V
    V
    V
    V
    VG2-S = 4 V; VDS = 5 V; RG1 = 120 k;  
    mA  
    note 1  
    IG1-SS  
    IG2-SS  
    gate 1 cut-off current  
    gate 2 cut-off current  
    VG2-S = VDS = 0; VG1-S = 5 V  
    VG1-S = VDS = 0; VG2-S = 4 V  
    50  
    20  
    nA  
    nA  
    Note  
    1.  
    RG1 connects G1 to VGG = 5 V.  
    DYNAMIC CHARACTERISTICS  
    Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; unless otherwise specified.  
    SYMBOL  
    PARAMETER  
    CONDITIONS  
    MIN.  
    25  
    TYP. MAX. UNIT  
    yfs  
    Cig1-ss  
    Cig2-ss  
    Coss  
    Crss  
    forward transfer admittance pulsed; Tj = 25 C  
    30  
    40  
    2.2  
    mS  
    pF  
    pF  
    pF  
    fF  
    input capacitance at gate 1  
    input capacitance at gate 2  
    output capacitance  
    f = 1 MHz  
    f = 1 MHz  
    f = 1 MHz  
    1.7  
    1
    0.85  
    15  
    reverse transfer capacitance f = 1 MHz  
    30  
    11  
    1.5  
    1.8  
    F
    noise figure  
    f = 10.7 MHz; GS = 20 mS; BS = 0  
    9
    dB  
    dB  
    dB  
    dB  
    f = 400 MHz; YS = YS opt  
    f = 800 MHz; YS = YS opt  
    0.9  
    1.1  
    34.5  
    Gtr  
    power gain  
    f = 200 MHz; GS = 2 mS; BS = BS opt  
    GL = 0.5 mS; BL = BL opt  
    ;
    ;
    f = 400 MHz; GS = 2 mS; BS = BS opt  
    GL = 1 mS; BL = BL opt  
    30.5  
    26.5  
    dB  
    dB  
    f = 800 MHz; GS = 3.3 mS; BS = BS opt  
    ;
    GL = 1 mS; BL = BL opt  
    Xmod  
    cross-modulation  
    input level for k = 1%; fw = 50 MHz;  
    funw = 60 MHz; note 1  
    at 0 dB AGC  
    at 10 dB AGC  
    at 40 dB AGC  
    90  
    dBV  
    dBV  
    dBV  
    92  
    105  
    100  
    Note  
    1. Measured in Fig.21 test circuit.  
    2010 Sep 16  
    4
     
     
    NXP Semiconductors  
    Product specification  
    N-channel dual-gate PoLo MOS-FETs  
    BF1202; BF1202R; BF1202WR  
    MCD952  
    MCD953  
    20  
    24  
    handbook, halfpage  
    handbook, halfpage  
    V
    = 4 V  
    G2-S  
    I
    2.5 V  
    D
    V
    = 1.5 V  
    G1-S  
    (mA)  
    16  
    I
    3.5 V  
    3 V  
    D
    (mA)  
    2 V  
    1.4 V  
    1.3 V  
    16  
    12  
    8
    1.2 V  
    1.1 V  
    1.5 V  
    8
    1 V  
    4
    0
    0.9 V  
    1 V  
    0
    0
    0
    0.4  
    0.8  
    1.2  
    1.6  
    2
    (V)  
    2
    4
    6
    8
    10  
    (V)  
    V
    V
    DS  
    G1-S  
    VDS = 5 V.  
    VG2-S = 4 V.  
    Tj = 25 C.  
    Tj = 25 C.  
    Fig.5 Transfer characteristics; typical values.  
    Fig.6 Output characteristics; typical values.  
    MCD954  
    MCD955  
    100  
    40  
    handbook, halfpage  
    handbook, halfpage  
    3.5 V  
    3 V  
    V
    = 4 V  
    I
    G2-S  
    G1  
    (μA)  
    80  
    3.5 V  
    y
    fs  
    (mS)  
    V
    = 4 V  
    G2-S  
    30  
    3 V  
    60  
    40  
    2.5 V  
    2 V  
    20  
    10  
    0
    2.5 V  
    20  
    0
    2 V  
    1.5 V  
    1 V  
    0
    0.5  
    1
    1.5  
    2
    2.5  
    (V)  
    0
    4
    8
    12  
    16  
    I
    20  
    (mA)  
    V
    D
    G1-S  
    VDS = 5 V.  
    VDS = 5 V.  
    Tj = 25 C.  
    Tj = 25 C.  
    Fig.7 Gate 1 current as a function of gate 1  
    voltage; typical values.  
    Fig.8 Forward transfer admittance as a function  
    of drain current; typical values.  
    2010 Sep 16  
    5
    NXP Semiconductors  
    Product specification  
    N-channel dual-gate PoLo MOS-FETs  
    BF1202; BF1202R; BF1202WR  
    MCD956  
    MCD957  
    20  
    16  
    handbook, halfpage  
    handbook, halfpage  
    I
    D
    (mA)  
    16  
    I
    D
    (mA)  
    12  
    12  
    8
    8
    4
    4
    0
    0
    0
    0
    10  
    20  
    30  
    40  
    I
    50  
    (μA)  
    1
    2
    3
    4
    5
    V
    (V)  
    G1  
    GG  
    VDS = 5 V; VG2-S = 4 V; Tj = 25 C.  
    RG1 = 120 k(connected to VGG); see Fig.21.  
    VDS = 5 V; VG2-S = 4 V.  
    Tj = 25 C.  
    Fig.9 Drain current as a function of gate 1 current;  
    typical values.  
    Fig.10 Drain current as a function of gate 1 supply  
    voltage (= VGG); typical values.  
    MCD959  
    MCD958  
    16  
    20  
    handbook, halfpage  
    handbook, halfpage  
    R
    = 68 kΩ  
    I
    G1  
    D
    I
    D
    V
    = 5 V  
    GG  
    (mA)  
    16  
    (mA)  
    82 kΩ  
    4.5 V  
    12  
    8
    4 V  
    100 kΩ  
    120 kΩ  
    3.5 V  
    3 V  
    12  
    8
    150 kΩ  
    180 kΩ  
    220 kΩ  
    4
    4
    0
    0
    0
    2
    4
    6
    0
    2
    4
    6
    (V)  
    V
    (V)  
    G2-S  
    V
    = V  
    GG  
    DS  
    VG2-S = 4 V; Tj = 25 C.  
    G1 connected to VGG; see Fig.21.  
    VDS = 5 V; Tj = 25 C.  
    RG1 = 120 k(connected to VGG); see Fig.21.  
    R
    Fig.11 Drain current as a function of gate 1 (= VGG  
    )
    Fig.12 Drain current as a function of gate 2  
    voltage; typical values.  
    and drain supply voltage; typical values.  
    2010 Sep 16  
    6
    NXP Semiconductors  
    Product specification  
    N-channel dual-gate PoLo MOS-FETs  
    BF1202; BF1202R; BF1202WR  
    MCD960  
    MCD961  
    40  
    0
    handbook, halfpage  
    handbook, halfpage  
    gain  
    reduction  
    (dB)  
    I
    G1  
    (μA)  
    V
    = 5 V  
    GG  
    −10  
    30  
    20  
    10  
    0
    4.5 V  
    4 V  
    −20  
    −30  
    3.5 V  
    3 V  
    −40  
    −50  
    0
    2
    4
    6
    0
    1
    2
    3
    4
    V
    (V)  
    V
    (V)  
    G2-S  
    AGC  
    VDS = 5 V; Tj = 25 C.  
    RG1 = 120 k(connected to VGG); see Fig.21.  
    VDS = 5 V; VGG = 5 V; RG1 = 120 k;  
    f = 50 MHz; Tamb = 25 C.  
    Fig.13 Gate 1 current as a function of gate 2  
    voltage; typical values.  
    Fig.14 Typical gain reduction as a function of the  
    AGC voltage; see Fig.21.  
    MCD962  
    120  
    MCD963  
    handbook, halfpage  
    16  
    handbook, halfpage  
    V
    unw  
    (dBμV)  
    I
    D
    (mA)  
    110  
    12  
    100  
    90  
    8
    4
    0
    80  
    0
    10  
    20  
    30  
    40  
    50  
    0
    10  
    20  
    30  
    40  
    50  
    gain reduction (dB)  
    gain reduction (dB)  
    VDS = 5 V; VGG = 5 V; RG1 = 120 k;  
    f= 50 MHz; funw = 60 MHz; Tamb = 25 C.  
    VDS = 5 V; VGG = 5 V; RG1 = 120 k;  
    f = 50 MHz; Tamb = 25 C.  
    Fig.15 Unwanted voltage for 1% cross-modulation  
    as a function of gain reduction; typical  
    values; Fig.21.  
    Fig.16 Drain current as a function of gain  
    reduction; typical values; see Fig.21.  
    2010 Sep 16  
    7
    NXP Semiconductors  
    Product specification  
    N-channel dual-gate PoLo MOS-FETs  
    BF1202; BF1202R; BF1202WR  
    MCD964  
    2
    10  
    MCD965  
    3
    3
    handbook, halfpage  
    10  
    −10  
    handbook, halfpage  
    Y
    is  
    (mS)  
    ϕ
    (deg)  
    y
    rs  
    rs  
    (μS)  
    ϕ
    10  
    rs  
    2
    2
    −10  
    10  
    b
    is  
    y
    rs  
    g
    is  
    1
    −10  
    −1  
    10  
    −1  
    10  
    10  
    2
    3
    1
    10  
    10  
    2
    3
    10  
    10  
    10  
    f (GHz)  
    f (MHz)  
    VDS = 5 V; VG2 = 4 V.  
    VDS = 5 V; VG2 = 4 V.  
    ID = 12 mA; Tamb = 25 C.  
    ID = 12 mA; Tamb = 25 C.  
    Fig.17 Input admittance as a function of frequency;  
    typical values.  
    Fig.18 Reverse transfer admittance and phase as  
    a function of frequency; typical values.  
    MCD966  
    MCD967  
    2
    2
    10  
    −10  
    10  
    handbook, halfpage  
    handbook, halfpage  
    ϕ
    (deg)  
    y
    Y
    fs  
    fs  
    os  
    (mS)  
    (mS)  
    y
    fs  
    b
    os  
    1
    10  
    −10  
    ϕ
    fs  
    −1  
    10  
    g
    os  
    −2  
    10  
    −1  
    1
    10  
    2
    3
    2
    3
    10  
    10  
    10  
    10  
    10  
    f (MHz)  
    f (MHz)  
    VDS = 5 V; VG2 = 4 V.  
    VDS = 5 V; VG2 = 4 V.  
    I
    D = 12 mA; Tamb = 25 C.  
    ID = 12 mA; Tamb = 25 C.  
    Fig.19 Forward transfer admittance and phase as  
    a function of frequency; typical values.  
    Fig.20 Output admittance as a function of  
    frequency; typical values.  
    2010 Sep 16  
    8
    NXP Semiconductors  
    Product specification  
    N-channel dual-gate PoLo MOS-FETs  
    BF1202; BF1202R; BF1202WR  
    V
    AGC  
    R1  
    10 kΩ  
    C1  
    4.7 nF  
    C3  
    4.7 nF  
    R
    50 Ω  
    L1  
    ≈2.2 μH  
    L
    C2  
    DUT  
    C4  
    4.7 nF  
    R
    GEN  
    50 Ω  
    R2  
    50 Ω  
    R
    G1  
    4.7 nF  
    V
    V
    V
    I
    GG  
    DS  
    MGS315  
    Fig.21 Cross-modulation test set-up.  
    Table 1 Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 C  
    s11  
    s21  
    s12  
    s22  
    f
    MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE  
    (MHz)  
    (ratio)  
    (deg)  
    (ratio)  
    (deg)  
    (ratio)  
    (deg)  
    (ratio)  
    (deg)  
    50  
    100  
    200  
    300  
    400  
    500  
    600  
    700  
    800  
    900  
    1000  
    0.988  
    0.988  
    0.984  
    0.977  
    0.965  
    0.951  
    0.936  
    0.919  
    0.903  
    0.887  
    0.870  
    3.26  
    6.52  
    2.989  
    3.017  
    2.990  
    2.949  
    2.913  
    2.853  
    2.793  
    2.727  
    2.664  
    2.593  
    2.518  
    176.2  
    172.5  
    165.0  
    157.6  
    150.3  
    143.2  
    136.3  
    129.5  
    123.0  
    116.7  
    110.5  
    0.0005  
    0.0009  
    0.0018  
    0.0027  
    0.0036  
    0.0039  
    0.0042  
    0.0044  
    0.0043  
    0.0041  
    0.0038  
    92.6  
    88.0  
    82.5  
    78.2  
    75.4  
    71.8  
    69.9  
    68.9  
    68.5  
    70.7  
    72.4  
    0.995  
    0.995  
    0.994  
    0.992  
    0.990  
    0.988  
    0.986  
    0.984  
    0.980  
    0.975  
    0.970  
    1.50  
    3.01  
    12.99  
    19.39  
    25.65  
    31.76  
    37.68  
    43.42  
    48.94  
    54.25  
    59.34  
    5.95  
    8.86  
    11.79  
    14.65  
    17.41  
    20.10  
    22.69  
    25.27  
    27.90  
    Table 2 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 C  
    opt  
    f
    Fmin  
    (dB)  
    Rn  
    ()  
    (MHz)  
    (ratio)  
    0.805  
    0.725  
    (deg)  
    400  
    800  
    0.9  
    1.1  
    28.5  
    47.2  
    50  
    40  
    2010 Sep 16  
    9
    NXP Semiconductors  
    Product specification  
    N-channel dual-gate PoLo MOS-FETs  
    BF1202; BF1202R; BF1202WR  
    PACKAGE OUTLINES  
    Plastic surface-mounted package; 4 leads  
    SOT143B  
    D
    B
    E
    A
    X
    y
    H
    v
    M
    A
    E
    e
    b
    w
    M
    B
    p
    4
    3
    Q
    A
    A
    1
    c
    1
    2
    L
    p
    b
    1
    e
    1
    detail X  
    0
    1
    2 mm  
    scale  
    DIMENSIONS (mm are the original dimensions)  
    A
    1
    max  
    UNIT  
    A
    b
    b
    c
    D
    E
    e
    e
    H
    L
    p
    Q
    v
    w
    y
    p
    1
    1
    E
    1.1  
    0.9  
    0.48  
    0.38  
    0.88  
    0.78  
    0.15  
    0.09  
    3.0  
    2.8  
    1.4  
    1.2  
    2.5  
    2.1  
    0.45  
    0.15  
    0.55  
    0.45  
    0.1  
    mm  
    1.9  
    1.7  
    0.2  
    0.1  
    0.1  
    REFERENCES  
    JEDEC JEITA  
    EUROPEAN  
    PROJECTION  
    OUTLINE  
    VERSION  
    ISSUE DATE  
    IEC  
    04-11-16  
    06-03-16  
    SOT143B  
    2010 Sep 16  
    10  
    NXP Semiconductors  
    Product specification  
    N-channel dual-gate PoLo MOS-FETs  
    BF1202; BF1202R; BF1202WR  
    Plastic surface-mounted package; reverse pinning; 4 leads  
    SOT143R  
    D
    B
    E
    A
    X
    y
    H
    v
    M
    A
    E
    e
    b
    w
    M
    B
    p
    3
    4
    Q
    A
    A
    1
    c
    2
    1
    L
    p
    b
    1
    e
    1
    detail X  
    0
    1
    2 mm  
    scale  
    DIMENSIONS (mm are the original dimensions)  
    A
    1
    max  
    UNIT  
    A
    b
    b
    c
    D
    E
    e
    e
    H
    L
    p
    Q
    v
    w
    y
    p
    1
    1
    E
    1.1  
    0.9  
    0.48  
    0.38  
    0.88  
    0.78  
    0.15  
    0.09  
    3.0  
    2.8  
    1.4  
    1.2  
    2.5  
    2.1  
    0.55  
    0.25  
    0.45  
    0.25  
    0.1  
    mm  
    1.9  
    1.7  
    0.2  
    0.1  
    0.1  
    REFERENCES  
    JEDEC JEITA  
    EUROPEAN  
    PROJECTION  
    OUTLINE  
    VERSION  
    ISSUE DATE  
    IEC  
    04-11-16  
    06-03-16  
    SOT143R  
    SC-61AA  
    2010 Sep 16  
    11  
    NXP Semiconductors  
    Product specification  
    N-channel dual-gate PoLo MOS-FETs  
    BF1202; BF1202R; BF1202WR  
    Plastic surface-mounted package; reverse pinning; 4 leads  
    SOT343R  
    D
    B
    E
    A
    X
    H
    v
    M
    A
    y
    E
    e
    3
    4
    Q
    A
    A
    1
    c
    2
    1
    L
    w
    M
    B
    b
    b
    1
    p
    p
    e
    1
    detail X  
    0
    1
    2 mm  
    scale  
    DIMENSIONS (mm are the original dimensions)  
    A
    1
    max  
    A
    UNIT  
    b
    b
    c
    D
    E
    e
    e
    H
    E
    L
    Q
    v
    w
    y
    p
    p
    1
    1
    0.4  
    0.3  
    1.1  
    0.8  
    0.7  
    0.5  
    0.25  
    0.10  
    2.2  
    1.8  
    1.35  
    1.15  
    2.2  
    2.0  
    0.45  
    0.15  
    0.23  
    0.13  
    mm  
    0.1  
    1.15  
    0.2  
    0.2  
    0.1  
    1.3  
    REFERENCES  
    JEDEC  
    EUROPEAN  
    PROJECTION  
    OUTLINE  
    VERSION  
    ISSUE DATE  
    IEC  
    EIAJ  
    97-05-21  
    06-03-16  
    SOT343R  
    2010 Sep 16  
    12  
    NXP Semiconductors  
    Product specification  
    N-channel dual-gate PoLo MOS-FETs  
    BF1202; BF1202R; BF1202WR  
    DATA SHEET STATUS  
    DOCUMENT  
    STATUS(1)  
    PRODUCT  
    STATUS(2)  
    DEFINITION  
    Objective data sheet  
    Development  
    This document contains data from the objective specification for product  
    development.  
    Preliminary data sheet  
    Product data sheet  
    Qualification  
    Production  
    This document contains data from the preliminary specification.  
    This document contains the product specification.  
    Notes  
    1. Please consult the most recently issued document before initiating or completing a design.  
    2. The product status of device(s) described in this document may have changed since this document was published  
    and may differ in case of multiple devices. The latest product status information is available on the Internet at  
    URL http://www.nxp.com.  
    DISCLAIMERS  
    property or environmental damage. NXP Semiconductors  
    accepts no liability for inclusion and/or use of NXP  
    Semiconductors products in such equipment or  
    applications and therefore such inclusion and/or use is at  
    the customer’s own risk.  
    Limited warranty and liability Information in this  
    document is believed to be accurate and reliable.  
    However, NXP Semiconductors does not give any  
    representations or warranties, expressed or implied, as to  
    the accuracy or completeness of such information and  
    shall have no liability for the consequences of use of such  
    information.  
    Applications Applications that are described herein for  
    any of these products are for illustrative purposes only.  
    NXP Semiconductors makes no representation or  
    warranty that such applications will be suitable for the  
    specified use without further testing or modification.  
    In no event shall NXP Semiconductors be liable for any  
    indirect, incidental, punitive, special or consequential  
    damages (including - without limitation - lost profits, lost  
    savings, business interruption, costs related to the  
    removal or replacement of any products or rework  
    charges) whether or not such damages are based on tort  
    (including negligence), warranty, breach of contract or any  
    other legal theory.  
    Customers are responsible for the design and operation of  
    their applications and products using NXP  
    Semiconductors products, and NXP Semiconductors  
    accepts no liability for any assistance with applications or  
    customer product design. It is customer’s sole  
    responsibility to determine whether the NXP  
    Semiconductors product is suitable and fit for the  
    customer’s applications and products planned, as well as  
    for the planned application and use of customer’s third  
    party customer(s). Customers should provide appropriate  
    design and operating safeguards to minimize the risks  
    associated with their applications and products.  
    Notwithstanding any damages that customer might incur  
    for any reason whatsoever, NXP Semiconductors’  
    aggregate and cumulative liability towards customer for  
    the products described herein shall be limited in  
    accordance with the Terms and conditions of commercial  
    sale of NXP Semiconductors.  
    NXP Semiconductors does not accept any liability related  
    to any default, damage, costs or problem which is based  
    on any weakness or default in the customer’s applications  
    or products, or the application or use by customer’s third  
    party customer(s). Customer is responsible for doing all  
    necessary testing for the customer’s applications and  
    products using NXP Semiconductors products in order to  
    avoid a default of the applications and the products or of  
    the application or use by customer’s third party  
    customer(s). NXP does not accept any liability in this  
    respect.  
    Right to make changes NXP Semiconductors  
    reserves the right to make changes to information  
    published in this document, including without limitation  
    specifications and product descriptions, at any time and  
    without notice. This document supersedes and replaces all  
    information supplied prior to the publication hereof.  
    Suitability for use NXP Semiconductors products are  
    not designed, authorized or warranted to be suitable for  
    use in life support, life-critical or safety-critical systems or  
    equipment, nor in applications where failure or malfunction  
    of an NXP Semiconductors product can reasonably be  
    expected to result in personal injury, death or severe  
    2010 Sep 16  
    13  
     
     
    NXP Semiconductors  
    Product specification  
    N-channel dual-gate PoLo MOS-FETs  
    BF1202; BF1202R; BF1202WR  
    Limiting values Stress above one or more limiting  
    values (as defined in the Absolute Maximum Ratings  
    System of IEC 60134) will cause permanent damage to  
    the device. Limiting values are stress ratings only and  
    (proper) operation of the device at these or any other  
    conditions above those given in the Recommended  
    operating conditions section (if present) or the  
    Characteristics sections of this document is not warranted.  
    Constant or repeated exposure to limiting values will  
    permanently and irreversibly affect the quality and  
    reliability of the device.  
    Quick reference data The Quick reference data is an  
    extract of the product data given in the Limiting values and  
    Characteristics sections of this document, and as such is  
    not complete, exhaustive or legally binding.  
    Non-automotive qualified products Unless this data  
    sheet expressly states that this specific NXP  
    Semiconductors product is automotive qualified, the  
    product is not suitable for automotive use. It is neither  
    qualified nor tested in accordance with automotive testing  
    or application requirements. NXP Semiconductors accepts  
    no liability for inclusion and/or use of non-automotive  
    qualified products in automotive equipment or  
    applications.  
    Terms and conditions of commercial sale NXP  
    Semiconductors products are sold subject to the general  
    terms and conditions of commercial sale, as published at  
    http://www.nxp.com/profile/terms, unless otherwise  
    agreed in a valid written individual agreement. In case an  
    individual agreement is concluded only the terms and  
    conditions of the respective agreement shall apply. NXP  
    Semiconductors hereby expressly objects to applying the  
    customer’s general terms and conditions with regard to the  
    purchase of NXP Semiconductors products by customer.  
    In the event that customer uses the product for design-in  
    and use in automotive applications to automotive  
    specifications and standards, customer (a) shall use the  
    product without NXP Semiconductors’ warranty of the  
    product for such automotive applications, use and  
    specifications, and (b) whenever customer uses the  
    product for automotive applications beyond NXP  
    Semiconductors’ specifications such use shall be solely at  
    customer’s own risk, and (c) customer fully indemnifies  
    NXP Semiconductors for any liability, damages or failed  
    product claims resulting from customer design and use of  
    the product for automotive applications beyond NXP  
    Semiconductors’ standard warranty and NXP  
    No offer to sell or license Nothing in this document  
    may be interpreted or construed as an offer to sell products  
    that is open for acceptance or the grant, conveyance or  
    implication of any license under any copyrights, patents or  
    other industrial or intellectual property rights.  
    Semiconductors’ product specifications.  
    Export control This document as well as the item(s)  
    described herein may be subject to export control  
    regulations. Export might require a prior authorization from  
    national authorities.  
    2010 Sep 16  
    14  
    NXP Semiconductors  
    provides High Performance Mixed Signal and Standard Product  
    solutions that leverage its leading RF, Analog, Power Management,  
    Interface, Security and Digital Processing expertise  
    Customer notification  
    This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal  
    definitions and disclaimers. No changes were made to the technical content, except for the marking codes  
    and the package outline drawings which were updated to the latest version.  
    Contact information  
    For additional information please visit: http://www.nxp.com  
    For sales offices addresses send e-mail to: salesaddresses@nxp.com  
    © NXP B.V. 2010  
    All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
    The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
    without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
    under patent- or other industrial or intellectual property rights.  
    Printed in The Netherlands  
    R77/03/pp15  
    Date of release: 2010 Sep 16  
    配单直通车
    BF1202WR,135产品参数
    型号:BF1202WR,135
    Source Url Status Check Date：2013-06-14 00:00:00
    Brand Name：NXP Semiconductor
    生命周期：Active
    IHS 制造商：NXP SEMICONDUCTORS
    针数：4
    制造商包装代码：SOT343R
    Reach Compliance Code：unknown
    风险等级：5.69
    Is Samacsys：N
    Base Number Matches：1
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