Rugged Environment
DC-DC Converters >100Watt
K Series
V ACFAIL signal (VME)
Formula for the external input capacitor:
Available for units with Uo1 = 5.1 V.
This option defines an undervoltage monitoring circuit for
the input or input and main output voltage (Uo1 nom = 5.1 V
only) equivalent to option D and generates an ACFAIL sig-
nal (V signal) which conforms to the VME standard.
2 • Po • (th + 0.3 ms) • 100
Ci ext = –––––––––––––––––––––– – Ci min
2
h • (Uti 2 – Ui min
)
where as:
Ci min = internal input capacitance [mF]
Ci ext = external input capacitance [mF]
The low state level of the ACFAIL signal is specified at a
sink current of IV ≤ 48 mA to UV ≤ 0.6 V (open-collector out-
put of a NPN transistor). The pull-up resistor feeding the
open-collector output should be placed on the VME back
plane.
Po
h
= output power [W]
= efficiency [%]
= hold-up time [ms]
th
Ui min = minimum input voltage [V] 1
Uti = threshold level [V]
After the ACFAIL signal has gone low, the VME standard
requires a hold-up time th of at least 4 ms before the 5.1 V
output drops to 4.875 V when the output is fully loaded.
This hold-up time th is provided by the internal input capaci-
tance. Consequently the working input voltage and the
threshold level Uti should be adequately above the mini-
mum input voltage Ui min of the converter so that enough
energy is remaining in the input capacitance. If the input
voltage is below the required level, an external hold-up ca-
pacitor (Ci ext) should be added.
1 Min. input voltage according to Electrical Input Data. For output
voltages Uo > Uo nom, the minimum input voltage increases pro-
portionally to Uo/Uo nom
.
Remarks:
Option V2 and V3 can be adjusted by potentiometer to a
threshold level between Ui min and Ui max. A decoupling di-
ode should be connected in series with the input of AK...FK
converters to avoid the input capacitance discharging
through other loads connected to the same source voltage.
Formula for threshold level for desired value of th:
2 • Po • (th + 0.3 ms) • 100
2
Uti = ––––––––––––––––––––– + Ui min
Ci min • h
Table 19: Available internal input capacitance and factory potentiometer setting of Uti with resulting hold-up time
Types
Ci min
Ut i
AK
0.83
9.5
BK
0.3
FK
1.2
39
CK
0.66
39
DK
0.26
61
EK
0.21
97
Unit
mF
19.5
0.1
V DC
ms
th
0.1
3.4
1.1
1.1
2.7
voltage(s) exceed(s) Ut + Uh. The threshold level Uti is ei-
ther adjustable by potentiometer, accessible through a hole
in the front cover, or adjusted during manufacture to a de-
termined customer specified value.
Option V operates independently of the built-in input under-
voltage lock-out circuit. A logic "low" signal is generated at
pin 20 as soon as one of the monitored voltages drops be-
low the preselected threshold level Ut. The return for this
signal is Vo1–. The V output recovers when the monitored
Versions V0, V2 and V3 are available as shown below.
Table 20: Undervoltage monitor functions
V output
(VME compatible)
Monitoring
Minimum adjustment range
of threshold level Ut
Uti Uto
Typical hysteresis Uh [% of Ut]
for Ut min…Ut max
Ui
Uo1
no
Uhi
Uho
–
1
–
V2
V3
V0
yes
yes
yes
yes
Ui min...Ui max
Ui min...Ui max
3.4...0.4
3.4...0.4
3.4...0.4
3.4...0.4
1
2
2
yes
no
0.95...0.985 Uo1
–
"0"
–
3 4
Ui min...Ui max
Ui min...Ui max
3 4
yes
0.95...0.985 Uo1
"0"
1 Threshold level adjustable by potentiometer. 2 Fixed value between 95% and 98.5% of Uo1 (tracking). 3 Adjusted at Io nom
.
4 Fixed value, resistor-adjusted (±2% at 25°C) acc. to customer's specifications; individual type number is determined by Melcher.
11009
V output (V0, V2, V3):
Vo1+
Connector pin V is internally connected to the open collec-
tor of a NPN transistor. The emitter is connected to the
negative potential of output 1. UV ≤ 0.6 V (logic low) corre-
sponds to a monitored voltage level (Ui and/or Uo1) <Ut.
The current IV through the open collector should not exceed
50 mA. The NPN output is not protected against external
overvoltages. UV should not exceed 60 V.
R
p
I
V
V
U
V
Ui, Uo1 status
V output, UV
Vo1–
Ui or Uo1 < Ut
low, L, UV ≤ 0.6 V at IV = 50 mA
high, H, IV ≤ 25 µA at UV = 5.1 V
Fig. 34
Output configuration of options V0, V2 and V3
Ui and Uo1 > Ut + Uh
Edition 4/4.99
29/31
MELCHER
The Power Partners.