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产品型号BK2423QB的概述

BK2423QB芯片概述 BK2423QB是一款专用于无线通信的高集成度低功耗射频芯片,广泛应用于IoT(物联网)设备、智能家居、可穿戴设备及其他需要无线连接的消费电子产品。其设计目标是实现高效的数据传输,同时保持较低的功耗,以延长设备的使用寿命。 在众多射频芯片中,BK2423QB凭借其优良的性能和易于集成的特性,逐渐获得了厂商和开发者的青睐。其能够在较宽的频率范围内工作,同时支持多种调制方式,使得它在各种应用场合中都能展现出良好的适应性。 BK2423QB详细参数 BK2423QB的主要参数包括: - 工作频率范围:一般为2400MHz至2483.5MHz,符合2.4GHz ISM(工业、科学和医疗)频段的标准。 - 低功耗:典型工作电流为15mA,待机电流小于1μA,极大反映了其低功耗设计的优势。 - 调制方式:支持GFSK、FSK等多种调制方式,适配不同的通信需求。 - 传输距...

产品型号BK2425的Datasheet PDF文件预览

BK2425  
Low Power High Performance 2.4 GHz GFSK Transceiver  
Features  
Pin Assignments  
NC  
20  
CDVDD VDD  
VSS  
17  
VDD  
16  
2400-2483.5 MHz ISM band operation  
Support 250Kbps, 1Mbps and 2 Mbps air  
data rate  
Programmable output power  
Low power consumption  
Tolerate +/- 60ppm 16 MHz crystal  
Variable payload length from 1 to 32bytes  
Automatic packet processing  
6 data pipes for 1:6 star networks  
1.9V to 3.6V power supply  
4-pin SPI interface with maximum 8 MHz  
clock rate  
19  
18  
1
2
3
4
5
15  
14  
13  
12  
11  
CE  
VDD  
CSN  
SCK  
VSS  
RF  
BK2425  
MOSI  
MISO  
NC  
NC  
6
7
8
9
10  
XI  
IRQ  
NC  
NC  
XO  
20-pin 4x4mm QFN package  
Applications  
Wireless PC peripherals  
Wireless gamepads  
Wireless audio  
Remote controls  
Home automation  
Toys  
Block Diagram  
RFP  
RFN  
Rx FIFO  
Packet  
CSN  
SCK  
MOSI  
MISO  
FM  
Data Slicer  
Demodulator  
Integrated  
TDD RF  
Transceiver  
Power  
Management  
IRQ  
CE  
Processing &  
State Control  
Gaussian  
shaping  
FM Modulator  
Tx FIFO  
XTALP XTALN  
Revision 1.0  
Jan, 2013  
Copyright © 2013  
Beken Corporation  
Page 1 of 30  
BK2425  
Table of Contents  
1
2
3
4
General Description................................................................................................................. 3  
Abbreviations .......................................................................................................................... 4  
Pin Information ....................................................................................................................... 5  
State Control ........................................................................................................................... 6  
4.1 State Control Diagram............................................................................................................... 6  
4.2 Power Down Mode.................................................................................................................... 7  
4.3 Standby-I Mode......................................................................................................................... 7  
4.4 Standby-II Mode........................................................................................................................ 7  
4.5 TX Mode ................................................................................................................................... 7  
4.6 RX Mode................................................................................................................................... 8  
Packet Processing .................................................................................................................... 8  
5.1 Packet Format............................................................................................................................ 8  
5.1.1 Preamble........................................................................................................................... 9  
5.1.2 Address............................................................................................................................. 9  
5.1.3 Packet Control.................................................................................................................. 9  
5.1.4 Payload........................................................................................................................... 10  
5.1.5 CRC................................................................................................................................ 10  
5.2 Packet Handling ...................................................................................................................... 10  
Data and Control Interface.................................................................................................... 11  
6.1 TX/RX FIFO ........................................................................................................................... 11  
6.2 Interrupt................................................................................................................................... 11  
6.3 SPI Interface............................................................................................................................ 12  
6.3.1 SPI Command ................................................................................................................ 12  
6.3.2 SPI Timing ..................................................................................................................... 13  
Register Map ......................................................................................................................... 15  
7.1 Register Bank 0 ....................................................................................................................... 15  
7.2 Register Bank 1 ....................................................................................................................... 21  
Electrical Specifications ......................................................................................................... 22  
Typical Application Schematic............................................................................................... 23  
5
6
7
8
9
10 Package and Die Bonding Information................................................................................... 24  
10.1  
10.2  
10.3  
Package Information...........................................................................................................24  
Die Bonding Information.................................................................................................... 25  
PCB Bonding diagram........................................................................................................ 27  
11 Order Information................................................................................................................. 28  
12 Contact Information .............................................................................................................. 29  
13 Update History ...................................................................................................................... 30  
Revision 1.0  
Proprietary and Confidential  
Page 2 of 30  
BK2425  
1 General Description  
BK2425 is a GFSK transceiver operating in  
the world wide ISM frequency band at 2400-  
2483.5 MHz. Burst mode transmission and up  
to 2Mbps air data rate make them suitable for  
applications requiring ultra low power  
resolution of the RF channel frequency is  
1MHz.  
A
transmitter and a receiver must be  
programmed with the same RF channel  
frequency to be able to communicate with  
each other.  
consumption.  
The  
embedded  
packet  
processing engines enable their full operation  
with a very simple MCU as a radio system.  
Auto re-transmission and auto acknowledge  
give reliable link without any MCU  
interference.  
The output power of BK2425 is set by the  
RF_PWR bits in the RF_SETUP register.  
Demodulation is done with embedded data  
slicer and bit recovery logic. The air data rate  
can be programmed to 250Kbps, 1Mbps or  
2Mbps by RF_DR_HIGH and RF_DR_LOW  
register. A transmitter and a receiver must be  
programmed with the same setting.  
BK2425 operates in TDD mode, either as a  
transmitter or as a receiver.  
The RF channel frequency determines the  
center of the channel used by BK2425. The  
frequency is set by the RF_CH register in  
register bank 0 according to the following  
formula: F0= 2400 + RF_CH (MHz). The  
In the following chapters, all registers are in  
register bank 0 except with explicit claim.  
RFP  
Rx FIFO  
CSN  
SCK  
MOSI  
MISO  
FM  
Data Slicer  
RFN  
Demodulator  
Integrated  
Power  
Management  
Transceiver  
Packet  
Processing &  
State Control  
IRQ  
CE  
TDD RF  
Gaussian  
shaping  
FM Modulator  
Tx FIFO  
XTALP XTALN  
Figure 1 BK2425 Chip Block Diagram  
Revision 1.0  
Proprietary and Confidential  
Page 3 of 30  
BK2425  
2 Abbreviations  
ACK  
ARC  
ARD  
CD  
Acknowledgement  
Auto Retransmission Count  
Auto Retransmission Delay  
Carrier Detection  
Chip Enable  
CE  
CRC  
CSN  
Cyclic Redundancy Check  
Chip Select Not  
DPL  
Dynamic Payload Length  
First-In-First-Out  
Gaussian Frequency Shift Keying  
Gigahertz  
FIFO  
GFSK  
GHz  
LNA  
IRQ  
ISM  
Low Noise Amplifier  
Interrupt Request  
Industrial-Scientific-Medical  
Least Significant Bit  
Maximum Retransmit  
Megabit per second  
Microcontroller Unit  
Megahertz  
Master In Slave Out  
Master Out Slave In  
Most Significant Bit  
Power Amplifier  
LSB  
MAX_RT  
Mbps  
MCU  
MHz  
MISO  
MOSI  
MSB  
PA  
PID  
PLD  
Packet Identity Bits  
Payload  
PRX  
Primary RX  
PTX  
Primary TX  
PWD_DWN  
PWD_UP  
RF_CH  
RSSI  
RX  
Power Down  
Power Up  
Radio Frequency Channel  
Received Signal Strength Indicator  
Receive  
RX_DR  
SCK  
Receive Data Ready  
SPI Clock  
SPI  
TDD  
TX  
Serial Peripheral Interface  
Time Division Duplex  
Transmit  
TX_DS  
XTAL  
Transmit Data Sent  
Crystal  
Revision 1.0  
Proprietary and Confidential  
Page 4 of 30  
BK2425  
3 Pin Information  
NC  
20  
CDVDD VDD  
VSS  
17  
VDD  
16  
19  
18  
1
2
3
4
5
15  
14  
13  
12  
11  
CE  
VDD  
CSN  
SCK  
VSS  
RF  
BK2425  
MOSI  
MISO  
NC  
NC  
6
7
8
9
10  
XI  
IRQ  
NC  
NC  
XO  
Figure 2 BK2425 pin assignments (top view) for the QFN20 package  
PIN  
Name  
Pin Function  
Description  
CE  
Digital Input  
Digital Input  
Digital Input  
Digital Input  
Digital Output  
Digital Output  
Chip Enable Activates RX or TX mode  
SPI Chip Select, Active low  
SPI Clock  
1
2
3
4
5
6
7
8
CSN  
SCK  
MOSI  
MISO  
IRQ  
NC  
SPI Slave Data Input  
SPI Slave Data Output with tri-state option  
Maskable interrupt pin, Active low  
No Connection  
No Connection  
NC  
XO  
Analog Output  
Analog Input  
Crystal oscillator, node P (inverter output)  
9
XI  
Crystal oscillator, node N (inverter input)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
NC  
No Connection  
No Connection  
NC  
RFN  
VSS  
VDD  
VDD  
VSS  
VDD  
CDVDD  
NC  
RF port  
Ground  
Power  
RF output (PA) /Input (LNA), port N.  
Ground (0 V)  
Power Supply (1.9 V to 3.6 V DC)  
Power Supply (1.9 V to 3.6 V DC)  
Ground (0 V)  
Ground  
Power  
Power Supply (1.9 V to 3.6 V DC)  
Digital regulator output decoupling capacitor  
Analog Output  
No Connection  
Table 1 BK2425 QFN20 pin functions  
Revision 1.0  
Proprietary and Confidential  
Page 5 of 30  
BK2425  
4 State Control  
4.1 State Control Diagram  
Pin signal: VDD, CE  
BK2425 has built-in state machines that  
control the state transition between different  
modes.  
SPI register: PWR_UP, PRIM_RX,  
EN_AA, NO_ACK, ARC, ARD  
System information: Time out, ACK  
received, ARD elapsed, ARC_CNT, TX  
FIFO empty, ACK packet transmitted,  
Packet received  
When auto acknowledge feature is disabled,  
state transition will be fully controlled by  
MCU.  
Figure 3 PTX (PRIM_RX=0) state control diagram  
Revision 1.0  
Proprietary and Confidential  
Page 6 of 30  
BK2425  
Figure 4 PRX (PRIM_RX=1) state control diagram  
4.2 Power Down Mode  
4.4 Standby-II Mode  
In power down mode BK2425 is in sleep  
mode with minimal current consumption. SPI  
interface is still active in this mode, and all  
register values are available by SPI. Power  
down mode is entered by setting the PWR_UP  
bit in the CONFIG register to low.  
In standby-II mode more clock buffers are  
active than in standby-I mode and much more  
current is used. Standby-II occurs when CE is  
held high on a PTX device with empty TX  
FIFO. If a new packet is uploaded to the TX  
FIFO in this mode, the device will  
automatically enter TX mode and the packet is  
transmitted.  
4.3 Standby-I Mode  
4.5 TX Mode  
By setting the PWR_UP bit in the CONFIG  
register to 1 and de-asserting CE to 0, the  
device enters standby-I mode. Standby-I mode  
is used to minimize average current  
consumption while maintaining short start-up  
time. In this mode, part of the crystal oscillator  
is active. This is also the mode which the  
BK2425 returns to from TX or RX mode when  
CE is set low.  
PTX device (PRIM_RX=0)  
The TX mode is an active mode where the  
PTX device transmits a packet. To enter this  
mode from power down mode, the PTX device  
must have the PWR_UP bit set high,  
PRIM_RX bit set low, a payload in the TX  
FIFO, and a high pulse on the CE for more  
than 10µs.  
Revision 1.0  
Proprietary and Confidential  
Page 7 of 30  
BK2425  
The PTX device stays in TX mode until it  
finishes transmitting the current packet. If CE  
= 0 it returns to standby-I mode. If CE = 1, the  
next action is determined by the status of the  
TX FIFO. If the TX FIFO is not empty the  
PTX device remains in TX mode, transmitting  
the next packet. If the TX FIFO is empty the  
PTX device goes into standby-II mode. It is  
important to never stay in TX mode for more  
than 4ms at one time.  
high, PRIM_RX bit set high and the CE pin  
set high. Or PRX device can enter this mode  
from TX mode after transmitting an  
acknowledge packet when EN_AA=1 and  
NO_ACK=0 in received packet.  
In this mode the receiver demodulates the  
signals from the RF channel, constantly  
presenting the demodulated data to the packet  
processing engine. The packet processing  
engine continuously searches for a valid  
packet. If a valid packet is found (by a  
matching address and a valid CRC) the  
payload of the packet is presented in a vacant  
slot in the RX FIFO. If the RX FIFO is full,  
the received packet is discarded.  
If the auto retransmit is enabled (EN_AA=1)  
and  
auto  
acknowledge  
is  
required  
(NO_ACK=0), the PTX device will enter TX  
mode from standby-I mode when ARD  
elapsed and number of retried is less than  
ARC.  
The PRX device remains in RX mode until the  
MCU configures it to standby-I mode or  
power down mode.  
PRX device (PRIM_RX=1)  
The PRX device will enter TX mode from RX  
mode only when EN_AA=1 and NO_ACK=0  
in received packet to transmit acknowledge  
packet with pending payload in TX FIFO.  
In RX mode a carrier detection (CD) signal is  
available. The CD is set to high when a RF  
signal is detected inside the receiving  
frequency channel. The internal CD signal is  
filtered before presented to CD register. The  
RF signal must be present for at least 128 µs  
before the CD is set high.  
4.6 RX Mode  
PRX device (PRIM_RX=1)  
PTX device (PRIM_RX=0)  
The RX mode is an active mode where the  
BK2425 radio is configured to be a receiver.  
To enter this mode from standby-I mode, the  
PRX device must have the PWR_UP bit set  
The PTX device will enter RX mode from TX  
mode only when EN_AA=1 and NO_ACK=0  
to receive acknowledge packet.  
5 Packet Processing  
5.1 Packet Format  
The packet format has a preamble, address, packet control, payload and CRC field.  
Preamble 1 byte Address 3~5 byte Packet Control 9/0 bit  
Payload 0~32 byte CRC2/1 byte  
Payload Length 6 bit  
PID2 bit  
NO_ACK1 bit  
Figure 5 Packet Format  
Revision 1.0  
Proprietary and Confidential  
Page 8 of 30  
BK2425  
5.1.1 Preamble  
No other data pipe can receive data until a  
complete packet is received by a data pipe that  
has detected its address. When multiple PTX  
devices are transmitting to a PRX, the ARD  
can be used to skew the auto retransmission so  
that they only block each other once.  
The preamble is a bit sequence used to detect 0  
and 1 levels in the receiver. The preamble is  
one byte long and is either 01010101 or  
10101010. If the first bit in the address is 1 the  
preamble is automatically set to 10101010 and  
if the first bit is  
0 the preamble is  
5.1.3 Packet Control  
automatically set to 01010101. This is done to  
ensure there are enough transitions in the  
preamble to stabilize the receiver.  
When Dynamic Payload Length function is  
enabled, the packet control field contains a 6  
bit payload length field, a 2 bit PID (Packet  
Identity) field and, a 1 bit NO_ACK flag.  
5.1.2 Address  
Payload length  
This is the address for the receiver. An address  
ensures that the packet is detected by the target  
receiver. The address field can be configured  
to be 3, 4, or 5 bytes long by the AW register.  
The payload length field is only used if the  
Dynamic Payload Length function is enabled.  
PID  
The 2 bit PID field is used to detect whether  
the received packet is new or retransmitted.  
PID prevents the PRX device from presenting  
the same payload more than once to the MCU.  
The PID field is incremented at the TX side  
for each new packet received through the SPI.  
The PID and CRC fields are used by the PRX  
device to determine whether a packet is old or  
new. When several data packets are lost on the  
link, the PID fields may become equal to the  
last received PID. If a packet has the same PID  
as the previous packet, BK2425 compares the  
CRC sums from both packets. If the CRC  
sums are also equal, the last received packet is  
considered a copy of the previously received  
packet and discarded.  
The PRX device can open up to six data pipes  
to support up to six PTX devices with unique  
addresses. All six PTX device addresses are  
searched simultaneously. In PRX side, the data  
pipes are enabled with the bits in the  
EN_RXADDR register. By default only data  
pipe 0 and 1 are enabled.  
Each data pipe address is configured in the  
RX_ADDR_PX registers.  
Each pipe can have up to 5 bytes configurable  
address. Data pipe 0 has a unique 5 byte  
address. Data pipes 1-5 share the 4 most  
significant address bytes. The LSB byte must  
be unique for all 6 pipes.  
NO_ACK  
To ensure that the ACK packet from the PRX  
is transmitted to the correct PTX, the PRX  
takes the data pipe address where it received  
the packet and uses it as the TX address when  
transmitting the ACK packet.  
The NO_ACK flag is only used when the auto  
acknowledgement feature is used. Setting the  
flag high, tells the receiver that the packet is  
not to be auto acknowledged.  
The PTX can set the NO_ACK flag bit in the  
Packet Control Field with the command:  
W_TX_PAYLOAD_NOACK. However, the  
function must first be enabled in the  
On the PRX, the RX_ADDR_Pn, defined as  
the pipe address, must be unique. On the PTX  
the TX_ADDR must be the same as the  
RX_ADDR_P0 on the PTX, and as the pipe  
address for the designated pipe on the PRX.  
FEATURE  
register  
by  
setting  
the  
Revision 1.0  
Proprietary and Confidential  
Page 9 of 30  
BK2425  
EN_DYN_ACK bit. When you use this option,  
the PTX goes directly to standby-I mode after  
transmitting the packet and the PRX does not  
transmit an ACK packet when it receives the  
packet.  
5.1.5 CRC  
The CRC is the error detection mechanism in  
the packet. The number of bytes in the CRC is  
set by the CRCO bit in the CONFIG register.  
It may be either 1 or 2 bytes and is calculated  
over the address, Packet Control Field, and  
Payload.  
5.1.4 Payload  
The payload is the user defined content of the  
packet. It can be 0 to 32 bytes wide, and it is  
transmitted on-air as it is uploaded  
(unmodified) to the device.  
The polynomial for 1 byte CRC is X8 + X2 +  
X + 1. Initial value is 0xFF.  
The polynomial for 2 byte CRC is X16 + X12  
X5 + 1. Initial value is 0xFFFF.  
+
The BK2425 provides two alternatives for  
handling payload lengths, static and dynamic  
payload length. The static payload length of  
each of six data pipes can be individually set.  
No packet is accepted by receiver side if the  
CRC fails.  
The default alternative is static payload length.  
With static payload length all packets between  
a transmitter and a receiver have the same  
length. Static payload length is set by the  
RX_PW_Px registers. The payload length on  
the transmitter side is set by the number of  
bytes clocked into the TX_FIFO and must  
equal the value in the RX_PW_Px register on  
the receiver side. Each pipe has its own  
payload length.  
5.2 Packet Handling  
BK2425 uses burst mode for payload  
transmission and receive.  
The transmitter fetches payload from TX FIFO,  
automatically assembles it into packet and  
transmits the packet in a very short burst  
period with 1Mbps or 2Mbps air data rate.  
After transmission, if the PTX packet has the  
NO_ACK flag set, BK2425 sets TX_DS and  
gives an active low interrupt IRQ to MCU. If  
the PTX is ACK packet, the PTX needs  
receive ACK from the PRX and then asserts  
the TX_DS IRQ.  
Dynamic Payload Length (DPL) is an  
alternative to static payload length. DPL  
enables the transmitter to send packets with  
variable payload length to the receiver. This  
means for a system with different payload  
lengths it is not necessary to scale the packet  
length to the longest payload.  
The receiver automatically validates and  
disassembles received packet, if there is a  
valid packet within the new payload, it will  
write the payload into RX FIFO, set RX_DR  
and give an active low interrupt IRQ to MCU.  
With DPL feature the BK2425 can decode the  
payload length of the received packet  
automatically instead of using the RX_PW_Px  
registers. The MCU can read the length of the  
received payload by using the command:  
R_RX_PL_WID.  
When auto acknowledge is enabled  
(EN_AA=1),  
the  
PTX  
device  
will  
automatically wait for acknowledge packet  
after transmission, and re-transmit original  
packet with the delay of ARD until an  
acknowledge packet is received or the number  
of re-transmission exceeds a threshold ARC. If  
the later one happens, BK2425 will set  
MAX_RT and give an active low interrupt  
In order to enable DPL the EN_DPL bit in the  
FEATURE register must be set. In RX mode  
the DYNPD register has to be set. A PTX that  
transmits to a PRX with DPL enabled must  
have the DPL_P0 bit in DYNPD set.  
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BK2425  
IRQ to MCU. Two packet loss counters  
(ARC_CNT and PLOS_CNT) are incremented  
each time a packet is lost. The ARC_CNT  
counts the number of retransmissions for the  
current transaction. The PLOS_CNT counts  
the total number of retransmissions since the  
last channel change. ARC_CNT is reset by  
initiating a new transaction. PLOS_CNT is  
reset by writing to the RF_CH register. It is  
possible to use the information in the  
OBSERVE_TX register to make an overall  
assessment of the channel quality.  
accessible through the SPI by using dedicated  
SPI commands. A TX FIFO in PRX can store  
payload for ACK packets to three different  
PTX devices. If the TX FIFO contains more  
than one payload to a pipe, payloads are  
handled using the first in first out principle.  
The TX FIFO in a PRX is blocked if all  
pending payloads are addressed to pipes where  
the link to the PTX is lost. In this case, the  
MCU can flush the TX FIFO by using the  
FLUSH_TX command.  
The RX FIFO in PRX may contain payload  
from up to three different PTX devices.  
The PTX device will retransmit if its RX FIFO  
is full but received ACK frame has payload.  
A TX FIFO in PTX can have up to three  
payloads stored.  
As an alternative for PTX device to auto  
retransmit it is possible to manually set the  
BK2425 to retransmit a packet a number of  
times. This is done by the REUSE_TX_PL  
command.  
The TX FIFO can be written to by three  
commands,  
W_TX_PAYLOAD  
and  
W_TX_PAYLOAD_NO_ACK in PTX mode  
and W_ACK_PAYLOAD in PRX mode. All  
three commands give access to the TX_PLD  
register.  
When auto acknowledge is enabled, the PRX  
device will automatically check the NO_ACK  
field in received packet, and if NO_ACK=0, it  
will automatically send an acknowledge  
packet to PTX device. If EN_ACK_PAY is set,  
and the acknowledge packet can also include  
pending payload in TX FIFO.  
The RX FIFO can be read by the command  
R_RX_PAYLOAD in both PTX and PRX  
mode. This command gives access to the  
RX_PLD register.  
The payload in TX FIFO in a PTX is NOT  
removed if the MAX_RT IRQ is asserted.  
6 Data and Control Interface  
In the FIFO_STATUS register it is possible to  
read if the TX and RX FIFO are full or empty.  
The TX_REUSE bit is also available in the  
FIFO_STATUS register. TX_REUSE is set by  
the SPI command REUSE_TX_PL, and is  
6.1 TX/RX FIFO  
The data FIFOs are used to store payload that  
is to be transmitted (TX FIFO) or payload that  
is received and ready to be clocked out (RX  
FIFO). The FIFO is accessible in both PTX  
mode and PRX mode.  
reset  
by  
the  
SPI  
command:  
W_TX_PAYLOAD or FLUSH TX.  
6.2 Interrupt  
There are three levels 32 bytes FIFO for both  
TX and RX, supporting both acknowledge  
mode or no acknowledge mode with up to six  
pipes.  
In BK2425 there is an active low interrupt  
(IRQ) pin, which is activated when TX_DS  
IRQ, RX_DR IRQ or MAX_RT IRQ are set  
high by the state machine in the STATUS  
register. The IRQ pin resets when MCU writes  
'1' to the IRQ source bit in the STATUS  
register. The IRQ mask in the CONFIG  
TX three levels, 32 byte FIFO  
RX three levels, 32 byte FIFO  
Both FIFOs have  
a controller and are  
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BK2425  
register is used to select the IRQ sources that  
are allowed to assert the IRQ pin. By setting  
one of the MASK bits high, the corresponding  
IRQ source is disabled. By default all IRQ  
sources are enabled.  
to low transition on CSN.  
In parallel to the SPI command word applied  
on the MOSI pin, the STATUS register is  
shifted serially out on the MISO pin.  
The 3 bit pipe information in the STATUS  
register is updated during the IRQ pin high to  
low transition. If the STATUS register is read  
during an IRQ pin high to low transition, the  
pipe information is unreliable.  
The serial shifting SPI commands is in the  
following format:  
<Command word: MSB bit to LSB bit  
(one byte)>  
<Data bytes: LSB byte to MSB byte,  
MSB bit in each byte first> for all  
registers at bank 0 and register 9 to  
register 14 at bank 1  
6.3 SPI Interface  
6.3.1 SPI Command  
<Data bytes: MSB byte to LSB byte,  
MSB bit in each byte first> for register 0  
to register 8 at bank 1  
The SPI commands are shown in Table 3.  
Every new command must be started by a high  
Command  
# Data  
Command name  
word  
Operation  
bytes  
(binary)  
Read command and status registers. AAAAA =  
5 bit Register Map Address  
1 to 5  
LSB byte first  
R_REGISTER  
W_REGISTER  
000A AAAA  
001A AAAA  
Write command and status registers. AAAAA = 5  
bit Register Map Address  
Executable in power down or standby modes only.  
Read RX-payload: 1 – 32 bytes. A read operation  
always starts at byte 0. Payload is deleted from FIFO  
after it is read. Used in RX mode.  
1 to 5  
LSB byte first  
1 to 32  
LSB byte first  
R_RX_PAYLOAD  
0110 0001  
Write TX-payload: 1 – 32 bytes. A write operation  
always starts at byte 0 used in TX payload.  
1 to 32  
LSB byte first  
W_TX_PAYLOAD  
FLUSH_TX  
1010 0000  
1110 0001  
Flush TX FIFO, used in TX mode  
0
Flush RX FIFO, used in RX mode  
Should not be executed during transmission of  
acknowledge, that is, acknowledge package will not  
be completed.  
FLUSH_RX  
1110 0010  
0
Used for a PTX device  
Reuse last transmitted payload. Packets are repeatedly  
retransmitted as long as CE is high.  
TX payload reuse is active until  
REUSE_TX_PL  
1110 0011  
0
W_TX_PAYLOAD or FLUSH TX is executed. TX  
payload reuse must not be activated or deactivated  
during package transmission  
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BK2425  
This write command followed by data 0x73 activates  
the following features:  
• R_RX_PL_WID  
• W_ACK_PAYLOAD  
• W_TX_PAYLOAD_NOACK  
A new ACTIVATE command with the same data  
deactivates them again. This is executable in power  
down or stand by modes only.  
The R_RX_PL_WID, W_ACK_PAYLOAD, and  
W_TX_PAYLOAD_NOACK features registers are  
initially in a deactivated state; a write has no effect, a  
read only results in zeros on MISO. To activate these  
registers, use the ACTIVATE command followed by  
data 0x73. Then they can be accessed as any other  
register. Use the same command and data to  
deactivate the registers again.  
ACTIVATE  
0101 0000  
1
This write command followed by data 0x53 toggles  
the register bank, and the current register bank  
number can be read out from REG7 [7]  
Read RX-payload width for the top  
R_RX_PL_WID  
0110 0000  
1010 1PPP  
R_RX_PAYLOAD in the RX FIFO.  
Used in RX mode.  
Write Payload to be transmitted together with  
ACK packet on PIPE PPP. (PPP valid in the range  
from 000 to 101). Maximum three ACK packet  
payloads can be pending. Payloads with same PPP are  
handled using first in - first out principle. Write  
payload: 1– 32 bytes. A write operation always starts  
at byte 0.  
1 to 32  
LSB byte first  
W_ACK_PAYLOAD  
Used in TX mode. Disables AUTOACK on this  
specific packet.  
W_TX_PAYLOAD_NO  
ACK  
1 to 32  
LSB byte first  
1011 0000  
1111 1111  
No Operation. Might be used to read the STATUS  
register  
NOP  
0
Table 2 SPI command  
6.3.2 SPI Timing  
SCK  
CSN  
Write to SPI register:  
x
x
x
MOSI  
MISO  
C7  
C6  
C5  
C4  
C3  
C2  
C1  
S1  
C0  
S0  
D7  
D6  
0
D5  
0
D4  
0
D3  
0
D2  
0
D1  
0
D0  
0
HI-Z  
Hi-Z  
S7  
S6  
S5  
S4  
S3  
S2  
0
Read from SPI register:  
x
C7  
C6  
C5  
C4  
C3  
C2  
C1  
S1  
C0  
S0  
x
MOSI  
MISO  
x
x
S7  
S6  
S5  
S4  
S3  
S2  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Figure 6 SPI timing  
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BK2425  
Cn: SPI command bit  
Sn: STATUS register bit  
Dn: Data Bit (LSB byte to MSB byte, MSB bit in each byte first)  
Note: The SPI timing is for bank 0 and register 9 to 14 at bank 1. For register 0 to 8 at bank 1, the byte  
order is inversed that the MSB byte is R/W before LSB byte.  
Figure 7 SPI NOP timing diagram  
Symbol  
Tdc  
Parameters  
Min  
10  
Max  
Units  
ns  
ns  
Data to SCK Setup  
SCK to Data Hold  
CSN to Data Valid  
SCK to Data Valid  
SCK Low Time  
Tdh  
20  
Tcsd  
Tcd  
38  
55  
ns  
ns  
Tcl  
40  
40  
0
ns  
Tch  
SCK High Time  
ns  
MHz  
Fsck  
Tr,Tf  
Tcc  
SCK Frequency  
8
SCK Rise and Fall  
CSN to SCK Setup  
SCK to CSN Hold  
CSN Inactive time  
CSN to Output High Z  
100  
ns  
ns  
ns  
ns  
ns  
2
2
Tcch  
Tcwh  
Tcdz  
50  
38  
Table 3 SPI timing parameter  
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BK2425  
7 Register Map  
There are two register banks, which can be toggled by SPI command “ACTIVATE” followed with  
0x53 byte, and bank status can be read from Bank0_REG7 [7].  
7.1 Register Bank 0  
Address  
(Hex)  
Reset  
Value  
Mnemonic  
Bit  
Type  
Description  
00  
CONFIG  
Configuration Register  
Reserved  
7
6
0
0
R/W  
Only '0' allowed  
MASK_RX_DR  
MASK_TX_DS  
MASK_MAX_RT  
R/W  
R/W  
R/W  
Mask interrupt caused by RX_DR  
1: Interrupt not reflected on the IRQ pin  
0: Reflect RX_DR as active low interrupt  
on the IRQ pin  
Mask interrupt caused by TX_DS  
1: Interrupt not reflected on the IRQ pin  
0: Reflect TX_DS as active low interrupt  
on the IRQ pin  
Mask interrupt caused by MAX_RT  
1: Interrupt not reflected on the IRQ pin  
0: Reflect MAX_RT as active low  
interrupt on the IRQ pin  
5
4
0
0
Enable CRC. Forced high if one of the bits  
in the EN_AA is high  
CRC encoding scheme  
EN_CRC  
CRCO  
3
2
1
0
R/W  
R/W  
'0' - 1 byte  
'1' - 2 bytes  
PWR_UP  
PRIM_RX  
1
0
0
0
R/W  
R/W  
1: POWER UP, 0:POWER DOWN  
RX/TX control,  
1: PRX, 0: PTX  
01  
EN_AA  
Enable ‘Auto Acknowledgment’ Function  
Reserved  
7:6  
5
4
3
2
00  
1
1
1
1
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Only '00' allowed  
ENAA_P5  
ENAA_P4  
ENAA_P3  
ENAA_P2  
ENAA_P1  
ENAA_P0  
Enable auto acknowledgement data pipe 5  
Enable auto acknowledgement data pipe 4  
Enable auto acknowledgement data pipe 3  
Enable auto acknowledgement data pipe 2  
Enable auto acknowledgement data pipe 1  
Enable auto acknowledgement data pipe 0  
1
0
1
1
02  
EN_RXADDR  
Reserved  
ERX_P5  
ERX_P4  
ERX_P3  
ERX_P2  
ERX_P1  
ERX_P0  
Enabled RX Addresses  
Only '00' allowed  
7:6  
5
4
3
2
00  
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Enable data pipe 5.  
Enable data pipe 4.  
Enable data pipe 3.  
Enable data pipe 2.  
Enable data pipe 1.  
Enable data pipe 0.  
1
0
1
1
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Setup of Address Widths  
(common for all data pipes)  
Only '000000' allowed  
03  
SETUP_AW  
Reserved  
AW  
7:2  
1:0  
000000  
11  
R/W  
R/W  
RX/TX Address field width  
'00' - Illegal  
'01' - 3 bytes  
'10' - 4 bytes  
'11' - 5 bytes  
LSB bytes are used if address width is  
below 5 bytes  
04  
SETUP_RETR  
ARD  
Setup of Automatic Retransmission  
Auto Retransmission Delay  
‘0000’ – Wait 250 us  
7:4  
0000  
R/W  
‘0001’ – Wait 500 us  
‘0010’ – Wait 750 us  
……..  
‘1111’ – Wait 4000 us  
(Delay defined from end of transmission to  
start of next transmission)  
Auto Retransmission Count  
‘0000’ –Re-Transmit disabled  
‘0001’ – Up to 1 Re-Transmission on fail  
of AA  
ARC  
3:0  
0011  
R/W  
……  
‘1111’ – Up to 15 Re-Transmission on fail  
of AA  
05  
06  
RF_CH  
Reserved  
RF_CH  
RF Channel  
Only '0' allowed  
Sets the frequency channel  
7
6:0  
0
R/W  
R/W  
0000010  
RF_SETUP  
Reserved  
RF Setup Register  
Only '00' allowed  
Set Air Data Rate. See RF_DR_HIGH for  
encoding.  
Force PLL lock signal. Only used in test  
Set Air Data Rate.  
7:6  
5
0
0
0
R/W  
R/W  
R/W  
RF_DR_LOW  
PLL_LOCK  
4
Encoding: RF_DR_LOW, RF_DR_HIGH:  
‘00’ – 1Mbps  
RF_DR_HIGH  
3
1
R/W  
‘01’ – 2Mbps (default)  
‘10’ – 250Kbps  
‘11’ – 2Mbps  
Set RF output power in TX mode  
RF_PWR[1:0]  
RF_PWR[1:0]  
LNA_HCURR  
2:1  
0
11  
1
R/W  
R/W  
Setup LNA gain  
0:Low gain(20dB down)  
1:High gain  
Status Register (In parallel to the SPI  
command word applied on the MOSI pin,  
the STATUS register is shifted serially out  
on the MISO pin)  
Register bank selection states. Switch  
register bank is done by SPI command  
“ACTIVATE” followed by 0x53  
0: Register bank 0  
07  
STATUS  
RBANK  
7
0
R
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1: Register bank 1  
RX_DR  
TX_DS  
6
5
0
0
R/W  
R/W  
Data Ready RX FIFO interrupt  
Asserted when new data arrives RX FIFO  
Write 1 to clear bit.  
Data Sent TX FIFO interrupt  
Asserted when packet transmitted on TX.  
If AUTO_ACK is activated, this bit is set  
high only when ACK is received.  
Write 1 to clear bit.  
Maximum number of TX retransmits  
interrupt  
Write 1 to clear bit. If MAX_RT is  
asserted it must be cleared to enable  
further communication.  
Data pipe number for the payload  
available for reading from RX_FIFO  
000-101: Data Pipe Number  
110: Not used  
MAX_RT  
RX_P_NO  
4
0
R/W  
R
3:1  
111  
111: RX FIFO Empty  
TX_FULL  
0
0
R
R
R
TX FIFO full flag.  
1: TX FIFO full  
0: Available locations in TX FIFO  
08  
OBSERVE_TX  
PLOS_CNT  
Transmit observe register  
Count lost packets. The counter is  
overflow protected to 15, and discontinues  
at max until reset. The counter is reset by  
writing to RF_CH.  
7:4  
3:0  
0000  
0000  
Count retransmitted packets. The counter  
is reset when transmission of a new packet  
starts.  
ARC_CNT  
09  
CD  
Reserved  
CD  
7:1  
0
000000  
0
R
R
Carrier Detect  
Receive address data pipe 0. 5 Bytes  
maximum length. (LSB byte is written  
first. Write the number of bytes defined by  
SETUP_AW)  
Receive address data pipe 1. 5 Bytes  
maximum length. (LSB byte is written  
first. Write the number of bytes defined by  
SETUP_AW)  
0A  
0B  
RX_ADDR_P0  
RX_ADDR_P1  
39:0  
39:0  
0xE7E7E  
7E7E7  
R/W  
R/W  
0xC2C2C  
2C2C2  
Receive address data pipe 2. Only LSB  
MSB bytes is equal to  
RX_ADDR_P1[39:8]  
Receive address data pipe 3. Only LSB  
MSB bytes is equal to  
RX_ADDR_P1[39:8]  
0C  
0D  
0E  
RX_ADDR_P2  
RX_ADDR_P3  
RX_ADDR_P4  
7:0  
7:0  
7:0  
0xC3  
0xC4  
0xC5  
R/W  
R/W  
R/W  
Receive address data pipe 4. Only LSB.  
MSB bytes is equal to  
RX_ADDR_P1[39:8]  
Receive address data pipe 5. Only LSB.  
MSB bytes is equal to  
RX_ADDR_P1[39:8]  
Transmit address. Used for a PTX device  
only.  
0F  
10  
RX_ADDR_P5  
TX_ADDR  
7:0  
0xC6  
R/W  
R/W  
39:0  
0xE7E7E  
7E7E7  
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BK2425  
(LSB byte is written first)  
Set RX_ADDR_P0 equal to this address to  
handle automatic acknowledge if this is a  
PTX device  
11  
12  
13  
14  
15  
RX_PW_P0  
Reserved  
7:6  
5:0  
00  
R/W  
R/W  
Only '00' allowed  
Number of bytes in RX payload in data  
pipe 0 (1 to 32 bytes).  
0: not used  
1 = 1 byte  
RX_PW_P0  
000000  
32 = 32 bytes  
RX_PW_P1  
Reserved  
7:6  
5:0  
00  
R/W  
R/W  
Only '00' allowed  
Number of bytes in RX payload in data  
pipe 1 (1 to 32 bytes).  
0: not used  
1 = 1 byte  
RX_PW_P1  
000000  
32 = 32 bytes  
RX_PW_P2  
Reserved  
7:6  
5:0  
00  
R/W  
R/W  
Only '00' allowed  
Number of bytes in RX payload in data  
pipe 2 (1 to 32 bytes).  
0: not used  
1 = 1 byte  
RX_PW_P2  
000000  
32 = 32 bytes  
RX_PW_P3  
Reserved  
7:6  
5:0  
00  
R/W  
R/W  
Only '00' allowed  
Number of bytes in RX payload in data  
pipe 3 (1 to 32 bytes).  
0: not used  
1 = 1 byte  
000000  
RX_PW_P3  
32 = 32 bytes  
RX_PW_P4  
Reserved  
7:6  
5:0  
00  
R/W  
R/W  
Only '00' allowed  
Number of bytes in RX payload in data  
pipe 4 (1 to 32 bytes).  
0: not used  
1 = 1 byte  
RX_PW_P4  
000000  
32 = 32 bytes  
16  
RX_PW_P5  
Reserved  
7:6  
5:0  
00  
R/W  
R/W  
Only '00' allowed  
Number of bytes in RX payload in data  
pipe 5 (1 to 32 bytes).  
0: not used  
1 = 1 byte  
RX_PW_P5  
000000  
32 = 32 bytes  
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17  
FIFO_STATUS  
Reserved  
FIFO Status Register  
Only '0' allowed  
7
6
0
0
R/W  
R
Reuse last transmitted data packet if set  
high.  
TX_REUSE  
The packet is repeatedly retransmitted as  
long as CE is high. TX_REUSE is set by  
the SPI command REUSE_TX_PL, and is  
reset by the SPI command  
W_TX_PAYLOAD or FLUSH TX  
TX FIFO full flag  
TX_FULL  
5
0
R
1: TX FIFO full; 0: Available locations in  
TX FIFO  
TX FIFO empty flag.  
TX_EMPTY  
Reserved  
4
1
00  
0
R
1: TX FIFO empty  
0: Data in TX FIFO  
Only '00' allowed  
RX FIFO full flag  
3:2  
1
R/W  
R
RX_FULL  
1: RX FIFO full  
0: Available locations in RX FIFO  
RX FIFO empty flag  
RX_EMPTY  
ACK_PLD  
0
1
R
1: RX FIFO empty  
0: Data in RX FIFO  
Written by separate SPI command ACK  
packet payload to data pipe number PPP  
given in SPI command  
N/A  
255:0  
X
W
Used in RX mode only  
Maximum three ACK packet payloads can  
be pending. Payloads with same PPP are  
handled first in first out.  
Written by separate SPI command TX data  
pay-load register 1 - 32 bytes. This register  
is implemented as a FIFO with three  
levels.  
N/A  
N/A  
TX_PLD  
RX_PLD  
255:0  
255:0  
X
X
W
R
Used in TX mode only  
Read by separate SPI command  
RX data payload register. 1 - 32 bytes.  
This register is implemented as a FIFO  
with three levels.  
All RX channels share the same FIFO.  
1C  
DYNPD  
Reserved  
Enable dynamic payload length  
Only ‘00’ allowed  
Enable dynamic payload length data pipe  
5.  
(Requires EN_DPL and ENAA_P5)  
Enable dynamic payload length data pipe  
4.  
(Requires EN_DPL and ENAA_P4)  
Enable dynamic payload length data pipe  
3.  
(Requires EN_DPL and ENAA_P3)  
Enable dynamic payload length data pipe  
2.  
7:6  
5
0
0
R/W  
R/W  
DPL_P5  
DPL_P4  
DPL_P3  
DPL_P2  
4
3
2
0
0
0
R/W  
R/W  
R/W  
(Requires EN_DPL and ENAA_P2)  
Enable dynamic payload length data pipe  
1.  
(Requires EN_DPL and ENAA_P1)  
Enable dynamic payload length data pipe  
0.  
DPL_P1  
DPL_P0  
1
0
0
0
R/W  
R/W  
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BK2425  
(Requires EN_DPL and ENAA_P0)  
1D  
FEATURE  
Reserved  
EN_DPL  
R/W  
R/W  
R/W  
R/W  
Feature Register  
Only ‘00000’ allowed  
Enables Dynamic Payload Length  
Enables Payload with ACK  
Enables the W_TX_PAYLOAD_NOACK  
command  
7:3  
2
1
0
0
0
EN_ACK_PAY  
EN_DYN_ACK  
0
0
R/W  
Note: Don’t write reserved registers and registers at other addresses in register bank 0  
Table 4 Register Bank 0  
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BK2425  
7.2 Register Bank 1  
Address  
Reset  
(Hex)  
Mnemonic  
Bit  
31:0  
31:0  
31:0  
Value  
Type  
Description  
00  
01  
02  
0
W
Must write with 0x404B01E2  
Must write with 0xC04B0000  
Must write with 0xD0FC8C02  
0
0
0x  
W
W
03  
31:0  
03001200  
W
Must write with 0x99003921  
Must write with  
1Msps 0xF996821B  
2Msps: 0xF99682DB  
250ksps 0xF9968ADB  
For single carrier mode:0xF9968221  
Must write with  
04  
05  
31:0  
31:0  
0
0
W
W
1Msps 0x24060FA6(Disable RSSI)  
2Msps 0x 24060FB6(Disable RSSI)  
250ksps:0x24060FB6(Disable RSSI)  
RSSI measurement:  
0:Enable  
RSSI_EN  
18  
31:0  
31:0  
0
0
0
W
W
W
1:Disable  
Reserved  
Reserved  
06  
07  
Register bank selection states. Switch  
register bank is done by SPI command  
“ACTIVATE” followed by 0x53  
0: Register bank 0  
RBANK  
Chip ID  
7
R
R
1: Register bank 1  
BEKEN Chip ID:  
0x00000063(BK2425)  
Reserved  
Reserved  
Reserved  
08  
09  
0A  
0B  
31:0  
0
0
0
0
Please initialize with 0x05731200  
For 120us mode:0x00731200  
PLL Settling time:  
101:130us  
0C  
31:0  
26:24  
0
101  
W
000:120us  
9
1
Compatible mode:  
0:Static compatible  
1:Dynamic compatible  
Please initialize with 0x0080B436  
Ramp curve  
0D  
0E  
NEW_FEATURE 31:0  
RAMP 87:0  
0
NA  
W
Please write with  
0x FFFFFEF7CF208104082041  
Note: Don’t write reserved registers and no definition registers in register bank 1  
Table 5 Register Bank 1  
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BK2425  
8 Electrical Specifications  
Name  
Parameter (Condition)  
Min  
Typical  
Max  
Unit  
Comment  
Operating Condition  
VDD  
Voltage  
1.9  
3.0  
3.6  
V
TEMP  
Temperature  
-40  
+27  
+85  
ºC  
Digital input Pin  
VIH  
VIL  
High level  
Low level  
0.7VDD  
VSS  
VDD+0.7  
0.3VDD  
V
V
Digital output Pin  
High level (IOH=-0.25mA)  
Low level(IOL=0.25mA)  
Normal condition  
VOH  
VOL  
VDD- 0.3  
0
VDD  
0.3  
V
V
IVDD  
IVDD  
IVDD  
Power Down current  
Standby-I current  
Standby-II current  
3
50  
300  
uA  
uA  
uA  
Normal RF condition  
Operating frequency  
Crystal frequency  
FOP  
FXTAL  
RFSK  
2400  
250  
2527  
2000  
MHz  
MHz  
Kbps  
16  
Air data rate  
Transmitter  
PRF  
Output power  
4
dBm  
MHz  
MHz  
KHz  
mA  
PBW  
PBW  
PBW  
IVDD  
Modulation 20 dB bandwidth(2Mbps)  
Modulation 20 dB bandwidth (1Mbps)  
Modulation 20 dB bandwidth (250Kbps)  
Current at -25dBm output power  
TBD  
TBD  
TBD  
9.8  
IVDD  
IVDD  
IVDD  
IVDD  
IVDD  
10.2  
10.8  
11.6  
13.4  
18  
mA  
mA  
mA  
mA  
mA  
Current at -18dBm output power  
Current at -12dBm output power  
Current at -7dBm output power  
Current at -1dBm output power  
Current at 4 dBm output power  
Receiver  
IVDD  
IVDD  
IVDD  
Current (2Mbps)  
Current (1Mbps)  
Current (250Kbps)  
16.5  
16  
16  
mA  
mA  
mA  
Max Input 1 E-3 BER  
10  
dBm  
dBm  
dBm  
dBm  
RXSENS  
RXSENS  
RXSENS  
1 E-3 BER sensitivity (2Mbps)  
1 E-3 BER sensitivity (1Mbps)  
1 E-3 BER sensitivity (250Kbps)  
-88  
-91  
-96  
Table 6 Electrical Specifications  
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BK2425  
9 Typical Application Schematic  
Figure 8 BK2425 QFN20 typical application schematic  
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BK2425  
10 Package and Die Bonding Information  
10.1 Package Information  
QFN20 4x4 package and SSOP20 are available for BK2425, Detail information of the package  
follows:  
Figure 11 QFN20 4x4 package diagram  
Parameter  
Min  
0.70  
0.00  
Typ  
0.75  
Max  
0.80  
0.05  
Unit  
mm  
mm  
mm  
mm  
mm  
mm  
mm  
mm  
mm  
mm  
A
A1  
A3  
D
-
0.20 REF  
4.00  
3.95  
3.95  
0.18  
0.30  
2.55  
2.55  
4.05  
4.05  
0.30  
0.50  
2.80  
2.80  
E
4.00  
b
0.23  
L
0.40  
D2  
E2  
e
2.70  
2.70  
0.50 REF  
Table 7 QFN20 4x4 Package dimensions  
Package marking  
BK2425  
QYYWWXX  
W
Q
Y
Y
W
XX  
QFN  
Year number  
Week number  
Internal Code  
Table 8 QFN20 Package marking  
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BK2425  
10.2 Die Bonding Information  
BK2425 also provides the naked dice for bonding. The PAD diagram and PAD coordinates are as  
below:  
Figure 12 Bonding diagram  
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BK2425  
Package Number  
Pad Number Pad Name  
X-Coordinate  
(um)  
Y-Coordinate  
(um)  
1
2
3
4
5
6
1
CE  
1280.5250  
1280.5250  
1280.5250  
1280.5250  
1280.5250  
1280.5250  
975.0140  
907.0140  
839.0140  
56.5250  
441.9330  
526.9330  
611.9330  
696.9330  
781.9330  
866.9330  
1211.7770  
1211.7770  
1211.7770  
1197.5610  
861.4960  
481.3040  
413.3040  
345.3040  
260.3000  
175.3040  
107.3040  
39.3040  
2
CSN  
3
SCK  
4
MOSI  
5
MISO  
6
IRQ  
7
TSTENb  
XTALP  
XTALN  
RFP  
9
8
10  
13  
14  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
gndBalun  
VSSFE  
VSSVCO  
VSSR  
51.0890  
36.9750  
36.9750  
36.9750  
15  
16  
VCCRF  
VCCVCO  
VCCDIG  
CDVDD  
VSSIF  
36.9750  
36.9750  
36.9750  
36.9750  
17  
18  
19  
659.1070  
761.1070  
829.1070  
914.1110  
999.1070  
1092.9640  
1177.9640  
42.9250  
VSSDIG  
VCCIF  
VCCDIG  
CDVDD  
ATSTP  
ATSTN  
42.9250  
42.9250  
42.9250  
42.9250  
125.9150  
125.9150  
Table 9 QFN20 Chip pad coordinates  
Note: (x,y) is the center of the PAD.  
Pad Openings: 68umX60.35um.  
Red: No connection.  
PAD17 and PAD22 are connected on chip.  
PAD18 and PAD23 are connected on chip.  
Die size: 1343umX1275um  
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BK2425  
10.3 PCB Bonding diagram  
Figure 13 PCB Bonding diagram  
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Page 27 of 30  
BK2425  
11 Order Information  
Part number  
BK2425QB  
BK2425WD  
Package  
QFN  
Packing  
Tape Reel  
Wafer  
MPQ (ea)  
3K  
Die  
Table 10 BK2425 order information  
Remark:  
MPQ: Minimum Package Quantity  
Revision 1.0  
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BK2425  
12 Contact Information  
Beken Corporation Technical Support Center  
Shanghai office  
Suite 3A, 1278 Keyuan Road, Zhangjiang High-Tech Park,  
Pudong New District, Shanghai, P.R. China  
Phone:  
Fax:  
86-21-51086811, 60871276  
86-21-60871277  
Postal Code:  
Email:  
Website:  
201203  
info@bekencorp.com  
www.bekencorp.com  
Shenzhen office  
Room 718, Shenzhen High-Tech Industrial Estate,  
Nanshan, Shenzhen, P.R. China  
Phone:  
Postal Code:  
86-755-2655 1063  
518057  
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BK2425  
13 Update History  
Version  
1.0  
date  
2013-12-20  
2013-01-29  
Author  
RK  
RK  
Description  
Initial version  
1.1  
Updated Electrical parameters and bank1  
Registers value.  
1.2  
1.3  
2013-01-29  
2014-06-04  
RK  
RK  
Updated Application schematic.  
Added QFN20 bonding and die size  
information.  
Revision 1.0  
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Page 30 of 30  
配单直通车
BK2540-7P产品参数
型号:BK2540-7P
Brand Name:Power-One
是否无铅: 含铅
是否Rohs认证: 不符合
生命周期:Obsolete
IHS 制造商:POWER-ONE INC
零件包装代码:MODULE
包装说明:,
制造商包装代码:CASE K02
Reach Compliance Code:compliant
ECCN代码:EAR99
风险等级:5.79
其他特性:15V ADDITIONAL OUTPUT AVAILABLE
模拟集成电路 - 其他类型:DC-DC REGULATED POWER SUPPLY MODULE
最大输入电压:70 V
最小输入电压:14 V
标称输入电压:30 V
JESD-30 代码:R-MXMA-X
JESD-609代码:e0
功能数量:1
输出次数:2
最高工作温度:71 °C
最低工作温度:-25 °C
最大输出电压:15.09 V
最小输出电压:14.91 V
标称输出电压:15 V
封装主体材料:METAL
封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified
表面贴装:NO
技术:HYBRID
温度等级:COMMERCIAL EXTENDED
端子面层:TIN LEAD
端子形式:UNSPECIFIED
端子位置:UNSPECIFIED
处于峰值回流温度下的最长时间:NOT SPECIFIED
最大总功率输出:150 W
微调/可调输出:NO
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