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    产品型号BL0921的Datasheet PDF文件预览

    SinglePhaseEnergyMeterIC  
    with Integrated Oscillator  
    BL0921  
    ꢀ FEATURES  
    ꢀ DESCRIPTION  
    ꢁ
    High accuracy, less than 0.1% error over a  
    The BL0921 is a low cost, high accuracy, high  
    stability, simple peripheral circuit electrical energy  
    meter IC. The meter based on the BL0921 is intended  
    for using in single-phase, two-wire distribution  
    systems. It can exactly measure the real power in the  
    positive orientation and negative orientation and  
    calculate the energy in the same orientation.  
    dynamic range of 500: 1  
    ꢁ
    ꢁ
    On-chip oscillator as clock source  
    Exactly measure the real power in the positive  
    orientation and negative orientation, calculate the  
    energy in the same orientation  
    ꢁ
    Two current monitors continuously monitor the  
    phase and neutral currents in two-wire distribution  
    systems. Uses the larger of two currents to bill, even  
    during a Fault condition  
    The BL0921 incorporates a novel fault detection  
    scheme that both warns of fault conditions and allows  
    the BL0921 to continue accurate billing during a fault  
    event. The BL0921 does this by continuously  
    monitoring both the phase and neutral (return)  
    currents. PIN12 (FAULT) indicates Fault condition,  
    when these currents differ by more than 12.5%.  
    Billing is continued using the larger of the two  
    currents when the difference is greater than 14%.  
    The BL0921 supplies average real power  
    information on the low frequency outputs F1 (Pin16)  
    and F2 (Pin15). These logic outputs may be used to  
    directly drive an electromechanical counter and  
    two-phase stepper motors. The CF (Pin14) logic  
    output gives instantaneous real power information.  
    This output is intended to be used for calibration  
    purposes or interface to an MCU.  
    ꢁ
    A PGA in the current channel allows using small  
    value shunt and burden resistance  
    The low frequency outputs F1 and F2 can  
    ꢁ
    directly drive electromechanical counters and two  
    phase stepper motors and the high frequency output  
    CF, supplies instantaneous real power, is intended for  
    calibration and communications  
    ꢁ
    Two logic outputs REVP and FAULT can be used  
    to indicate a potential orientation or Fault condition  
    ꢁ
    ꢁ
    ꢁ
    ꢁ
    ꢁ
    On-Chip power supply detector  
    On-Chip anti-creep protection  
    On-Chip voltage reference of 2.5V±8%  
    Single 5V supply  
    Low static power (typical value of 25mW).  
    The technology of SLiM (Smart–Low–current–  
    Management) is used.  
    BL0921 thinks over the stability of reading  
    error in the process of calibration. Bulk test data  
    indicate that in the condition of small signal 5%Ib  
    (Ib=5A), the error of CF is less than 0.1%. An internal  
    no-load threshold ensures that the BL0921 does not  
    exhibit any creep when there is no load.  
    ꢁ
    Credible work, working time is more than twenty  
    years  
    Interrelated patents are pending  
    ꢀ
    BLOCK DIAGRAM  
    VREF  
    VDD  
    1
    2
    3
    4
    5
    16  
    F1  
    F2  
    VDD  
    input contron  
    internal  
    oscillator  
    power  
    detector  
    voltage  
    reference  
    15  
    14  
    13  
    V1A  
    V1B  
    V1A  
    V1B  
    V1N  
    BL0921  
    CF  
    analog  
    to  
    digital  
    high  
    pass  
    current  
    sampling  
    FAULT  
    REVP  
    CF  
    digital  
    to  
    frequency  
    and  
    V1N  
    V2N  
    REVP  
    filter  
    digital  
    multiplic  
    ation  
    low  
    pass  
    filter  
    BL0921  
    12FAULT  
    analog  
    to  
    digital  
    high  
    pass  
    V2P  
    V2N  
    F1  
    voltage  
    sampling  
    output  
    F2  
    11  
    6
    7
    8
    G
    filter  
    V2P  
    10  
    S0  
    VREF  
    GND  
    logic contron  
    9
    S1  
    G
    S0  
    S1  
    SOP 16  
    http://www.belling.com.cn  
    - 1 -  
    3/15/2007  
    Total 13 Pages  
    SinglePhaseEnergyMeterIC  
    with Integrated Oscillator  
    BL0921  
    ꢀ PIN DESCRIPTIONS  
    Pin  
    Symbol  
    DESCRIPTIONS  
    Power Supply (+5V). Provides the supply voltage for the digital circuitry. It should be  
    maintained at 5 V±5% for specified operation.  
    1
    VDD  
    Inputs for Current Channel. These inputs are fully differential voltage inputs with a  
    2,3  
    4
    V1A,V1B maximum signal level of ±660 mV with respect to pin6 (V1N) for specified  
    operation.  
    V1N  
    Negative Input Pin for Differential Voltage Inputs V1A and V1B.  
    Negative and Positive Inputs for Voltage Channel. These inputs provide a fully  
    5,6  
    V2N,V2P differential input pair. The maximum differential input voltage is ±660 mV for  
    specified operation.  
    On-Chip Voltage Reference. The on-chip reference has a nominal value of 2.5V ±  
    7
    8
    VREF  
    8% . An external reference source may also be connected at this pin.  
    AGND  
    S1,S0  
    Ground Reference. Provides the ground reference for the circuitry.  
    Output Frequency Select. These logic inputs are used to select one of four possible  
    frequencies for the digital-to-frequency conversion. This offers the designer greater  
    flexibility when designing the energy meter.  
    9,10  
    11  
    Gain Select. These logic inputs are used to select one of four possible gains for current  
    channel. The possible gains are 1 and 16.  
    G
    Fault Indication. Logic high indicates fault condition. Fault is defined as a condition  
    under which the signals on V1A and V1B differ by more than 12.5%. The logic output  
    will be reset to zero when fault condition is no longer detected.  
    12  
    FAULT  
    Negative Indication. Logic high indicates negative power, i.e., when the phase angle  
    between the voltage and current signals is greater that 90°. This output is not latched  
    and will be reset when positive power is once again detected.  
    13  
    REVP  
    Calibration Frequency. The CF logic output gives instantaneous real power  
    information. This output is intended to use for calibration purposes.  
    14  
    CF  
    Low-Frequency. F1 and F2 supply average real power information. The logic outputs  
    can be used to directly drive electromechanical counters and 2-phase stepper motors.  
    15,16  
    F1,F2  
    ꢀ ABSOLUTE MAXIMUM RATINGS  
    ( T = 25 ℃ )  
    Parameter  
    Symbol  
    Value  
    -0.3~+7(max)  
    Unit  
    V
    Power Voltage VDD  
    VDD  
    V (V)  
    V (I)  
    Topr  
    Tstr  
    Input Voltage of Channel 2 to GND  
    Input Voltage of Channel 1 to GND  
    Operating Temperature Range  
    Storage Temperature Range  
    Power Dissipation  
    VSS+0.5≤V(v)≤VDD-0.5  
    VSS+0.5≤V(i)≤VDD-0.5  
    -40~+75  
    V
    V
    ℃
    -55~+150  
    ℃
    400  
    mW  
    http://www.belling.com.cn  
    - 2 -  
    Total 13 Pages  
    3/15/2007  
    SinglePhaseEnergyMeterIC  
    with Integrated Oscillator  
    BL0921  
    ꢀ ELECTRONIC CHARACTERISTIC PARAMETER  
    (T=25℃, VDD=5V，On-Chip Oscillator，On-Chip voltage reference)  
    Measure  
    Pin  
    Min  
    Typica  
    Max  
    Parameter  
    Symbol  
    Test Condition  
    Unit  
    Value l Value  
    Value  
    1 Power Supply  
    IDD  
    Pin1  
    5
    mA  
    2 Logic Input Pins  
    S1, S0, G,  
    Pin 9,  
    10, 11  
    Input High Voltage  
    Input Low Voltage  
    Input Capacitance  
    3 Logic Output Pins F1,  
    F2, CF, REVP, FAULT  
    Output High Voltage  
    Output Low Voltage  
    4 On-chip Reference  
    Temperature coefficient  
    5 Analog Input Pins  
    V1A, V1B, V1N, V2N,  
    V2P  
    VIH  
    VIL  
    CIN  
    VDD=5V  
    2
    V
    V
    1
    10  
    pF  
    Pin16,15  
    ,14,13,12  
    VOH1  
    VOL1  
    Vref  
    IH=10mA  
    IL=10mA  
    VDD=5V  
    4.4  
    V
    V
    0.5  
    2.7  
    60  
    Pin7  
    2.3  
    2.5  
    30  
    V
    ppm/°C  
    Pin  
    2,3,4,5,,6  
    Maximum Input Voltage  
    DC Input Impedance  
    Input Capacitance  
    6 Accuracy  
    VAIN  
    V
    Kohm  
    pF  
    ±1  
    330  
    6
    10  
    Measurement Error on  
    Channel 1 and 2  
    Gain=1  
    ENL1  
    Both channels with  
    Full-Scale signal  
    Pin14  
    Pin14  
    0.1  
    0.1  
    %
    %
    Gain=16  
    ENL16  
    ±660mV over a  
    dynamic range 500 to 1  
    Phase Error between  
    Channels  
    Pin14  
    Pin14  
    0.1  
    0.1  
    °
    °
    Channel 1 Lead 37°  
    (PF=0.8 Capacitive)  
    Channel 1 Lags  
    (PF=0.5 Inductive)  
    7 Start Current  
    ISTART  
    ENP  
    Ib=5A, C=3200  
    Vv=±110mV,V(I)=2mV,  
    cosϕ=1  
    Pin14  
    Pin14  
    0.2%Ib  
    0.3  
    A
    8 Positive and Negative  
    Real Power Error (%)  
    0.1  
    %
    Vv=±110mV,V(I)=2mV,  
    cosϕ=-1  
    9 Gain Error  
    Gain error  
    Pin14  
    %
    ±5  
    http://www.belling.com.cn  
    - 3 -  
    3/15/2007  
    Total 13 Pages  
    SinglePhaseEnergyMeterIC  
    with Integrated Oscillator  
    BL0921  
    10 Gain Error Match  
    Pin14  
    0.2  
    1
    %
    ꢀ
    TERMINOLOGY  
    1) Measurement Error  
    The error associated with the energy measurement made by the BL0921 is defined by the  
    following formula:  
    Energy Re gisteredby the BL0921−True Energy  
    Pencebtage Error =  
    ×100%  
    True Energy  
    2) Nonlinear Error  
    The Nonlinear Error is defined by the following formula:  
    eNL%＝[(Error at X-Error at Ib) / (1+Error at Ib )]*100%  
    When V(v)= ±110mV, cosϕ=1, over the arrange of 5%Ib to 800%Ib, the nonlinear error should be  
    less than 0.1%.  
    3) Positive And Negative Real Power Error  
    When the positive real power and the negative real power is equal, and V(v) =±110mV, the test  
    current is Ib, then the positive and negative real power error can be achieved by the following  
    formula:  
    eNP%=|[(eN%-eP%)/(1+eP%)]*100%|  
    Where: eP% is the Positive Real Power Error, eN% is the Negative Real Power Error.  
    4) Phase Error Between Channels  
    The HPF (High Pass Filter) in Channel 1 has a phase lead response. To offset this phase response  
    and equalize the phase response between channels, a phase correction network is also placed in  
    Channel 1. The phase correction network matches the phase to within ±0.1°over a range of 45  
    Hz to 65 Hz and ±0.2°over a range 40Hz to 1KHz.  
    5) Gain Error  
    The gain error of the BL0921 is defined as the difference between the measured output frequency  
    (minus the offset) and the ideal output frequency. It is measured with a gain of 1 in channel V1.  
    The difference is expressed as a percentage of the ideal frequency. The ideal frequency is obtained  
    from the BL0921 transfer function.  
    6) Gain Error Match  
    The gain error match is defined as the gain error (minus the offset) obtained when switching  
    between a gain of 1 and a gain of 16. It is expressed as a percentage of the output frequency  
    obtained under a gain of 1. This gives the gain error observed when the gain selection is changed  
    from 1 to 16.  
    7) Power Supply Monitor  
    BL0921 has the on-chip Power Supply monitoring The BL0921 will remain in a reset  
    condition until the supply voltage on VDD reaches 4 V. If the supply falls below 4 V, the BL0921  
    will also be reset and no pulses will be issued on F1, F2 and CF.  
    http://www.belling.com.cn  
    - 4 -  
    3/15/2007  
    Total 13 Pages  
    SinglePhaseEnergyMeterIC  
    with Integrated Oscillator  
    BL0921  
    ꢀ TIMING CHARACTERISTIC  
    (VDD=5V, GND=0V, On-Chip Reference, Integrated Oscillator, Temperature range: -20~+70°C)  
    Parameter  
    Value  
    Comments  
    t1  
    144ms  
    F1 and F2 pulse-width (Logic Low). When the power is low,  
    the t1 is equal to 144ms; when the power is high, and the  
    output period falls below 550ms, t1 equals to half of the  
    output period.  
    t2  
    t3  
    t4  
    t5  
    F1 or F2 output pulse period.  
    ½ t2  
    Time between F1 falling edge and F2 falling edge.  
    CF Pulse Period. See Transfer Function section.  
    CF pulse-width (Logic high). When the power is low, the t5  
    is equal to 71ms; when the power is high, and the output  
    period falls below 180ms, t5 equals to half of the output  
    period.  
    71ms  
    t6  
    CLKIN/4 Minimum Time Between F1 and F2.  
    Notes:  
    1) CF is not synchronous to F1 or F2 frequency outputs.  
    2) Sample tested during initial release and after any redesign or process change that may affect this  
    parameter.  
    ꢀ THEORY OF OPERATION  
    ꢀ
    Principle of Energy Measure  
    In energy measure, the power information varying with time is calculated by a direct  
    multiplication of the voltage signal and the current signal. Assume that the current signal and the  
    voltage signal are cosine functions; V and I are the peak values of the voltage signal and the  
    current signal; ωis the angle frequency of the input signals; the phase difference between the  
    current signal and the voltage signal is expressed asФ. Then the power is given as follows:  
    p(t) = V cos(wt)× I cos(wt + Φ)  
    http://www.belling.com.cn  
    - 5 -  
    3/15/2007  
    Total 13 Pages  
    SinglePhaseEnergyMeterIC  
    with Integrated Oscillator  
    BL0921  
    Φ
    =0:  
    VI  
    p(t) =  
    (1+ cos(2wt)  
    2
    Φ ≠  
    0:  
    p(t) = V cos(wt)× I cos(wt + Φ)  
    = V cos(wt)×  
    [I cos(wt)cos(Φ) + sin(wt)sin(Φ)  
    ]
    VI  
    =
    =
    (1+ cos(2wt))cos(Φ) +VI cos(wt)sin(wt)sin(Φ)  
    2
    VI  
    VI  
    (1+ cos(2wt))cos(Φ) + sin(2wt)sin(Φ)  
    2
    2
    p(t) is called as the instantaneous power signal. The ideal p(t) consists of the dc component and ac  
    component whose frequency is 2ω. The dc component is called as the average active power, that  
    is:  
    VI  
    P = cos(  
    ϕ
    )
    2
    The average active power is related to the cosine value of the phase difference between the voltage  
    signal and the current signal. This cosine value is called as Power Factor (PF) of the two channel  
    signals.  
    Figure1.  
    The Effect of phase  
    When the signal phase difference between the voltage and current channels is more than 90°, the  
    average active power is negative. It indicates the user is using the electrical energy reversely.  
    ꢀ
    Operation Process  
    In BL0921, the two ADCs digitize the voltage signals from the current and voltage transducers.  
    These ADCs are 16-bit second order sigma-delta with an over sampling rate of 900 kHz. This  
    analog input structure greatly simplifies transducer interfacing by providing a wide dynamic range  
    for direct connection to the transducer and also simplifying the anti-alias filter design. A  
    programmable gain stage in the current channel further facilitates easy transducer interfacing. A  
    high pass filter in the current channel removes any dc component from the current signal. This  
    eliminates any inaccuracies in the real power calculation due to offsets in the voltage or current  
    signals.  
    The real power calculation is derived from the instantaneous power signal. The instantaneous  
    power signal is generated by a direct multiplication of the current and voltage signals. In order to  
    extract the real power component (i.e., the dc component), the instantaneous power signal is  
    low-pass filtered. Figure 2 illustrates the instantaneous real power signal and shows how the real  
    power information can be extracted by low-pass filtering the instantaneous power signal. This  
    http://www.belling.com.cn  
    - 6 -  
    3/15/2007  
    Total 13 Pages  
    SinglePhaseEnergyMeterIC  
    with Integrated Oscillator  
    BL0921  
    scheme correctly calculates real power for non-sinusoidal current and voltage waveforms at all  
    power factors. All signal processing is carried out in the digital domain for superior stability over  
    temperature and time.  
    current  
    sampling  
    analog to  
    digital  
    high pass  
    filter  
    I
    CF  
    F1  
    F2  
    digital  
    multipli-  
    cation  
    low pass  
    filter  
    digital to  
    frequency  
    integral  
    voltage  
    sampling  
    analog to  
    digital  
    high pass  
    filter  
    V
    instantaneous real  
    power signal  
    instantaneous  
    power signal p(t)  
    V*I  
    p(t)=i(t)*v(t)  
    v(t)=V*cos(wt)  
    i(t)=I*cos(wt)  
    V*I  
    2
    V*I  
    2
    V*I  
    p(t)=  
    [1+cos(2wt)]  
    2
    t
    t
    Figure 2.  
    Signal Processing Block Diagram  
    Accumulating this real power information generates the low frequency output of the BL0921. This  
    low frequency inherently means a long accumulation time between output pulses. The output  
    frequency is therefore proportional to the average real power. This average real power information  
    can, in turn, be accumulated (e.g., by a counter) to generate real energy information. Because of its  
    high output frequency and hence shorter integration time, the CF output is proportional to the  
    instantaneous real power. This is useful for system calibration purposes that would take place  
    under steady load conditions.  
    ꢀ
    Offset Effect  
    The dc offsets come from the input signals and the forepart analog circuitry.  
    Assume that the input dc offsets on the voltage channel and the current channel are Uoffset and Ioffset  
    and PF equals 1 (φ=0).  
    ,
    p(t) = [U cos(  
    ω
    t) + U offset ]× [I cos(  
    ω
    t + Φ ) + I offset ]  
    UI  
    UI  
    =
    + Ioffset U cos(  
    ω
    t) + U offset I cos(  
    ω
    t) +  
    cos( 2ωt)  
    2
    2
    Figure 3.  
    Effect of Offset  
    As can be seen, for each phase input, if there are simultaneous dc offsets on the voltage channel  
    and the current channel, these offsets contribute a dc component for the result of multiplication.  
    That is, the offsets bring the error of Uoffset  
    ×
    Ioffset to the final average real power. Additionally,  
    http://www.belling.com.cn  
    - 7 -  
    3/15/2007  
    Total 13 Pages  
    SinglePhaseEnergyMeterIC  
    with Integrated Oscillator  
    BL0921  
    there exists the component of Uoffset  
    ×
    I+  
    U
    ×
    Ioffset at the frequency of  
    ω
    . The dc error on the real  
    will also  
    power will result in measure error, and the component brought to the frequency of  
    ω
    affect the output of the average active power when the next low-pass filter cannot restrain the ac  
    component very completely.  
    When the offset on the one of the voltage and the current channels is filtered, for instance, the  
    offset on the current channel is removed; the result of multiplication is improved greatly. There is  
    no dc error, and the additional component at the frequency of  
    When the offsets on the voltage channel and the current channel are filtered respectively by two  
    high-pass filters, the component at the frequency of (50Hz) is subdued, and the stability of the  
    ω is also decreased.  
    ω
    output signal is advanced. Moreover, in this case, the phases of the voltage channel and the current  
    channel can be matched completely, and the performance when PF equal 0.5C or 0.5L is improved.  
    In BL0921, this structure is selected. Though it is given in the system specification that the ripple  
    of the output signal is less than 0.1%, in real measure of BL0921, the calibration output is very  
    stable, and the ripple of the typical output signal is less than 0.05%.  
    Additionally, this structure can ensure the frequency characteristic. When the input signal changes  
    from 45Hz to 65Hz, the complete machine error due to the frequency change is less than 0.1%. In  
    such, the meter designed for the 50Hz input signal can be used on the transmission-line system of  
    electric power whose frequency is 60Hz.  
    ꢀ
    Voltage Channel Input  
    The output of the line voltage transducer is connected to the BL0921 at this analog input. As  
    Figure4 shows that channel V2 is a fully differential voltage input. The maximum peak differential  
    signal on Channel 2 is  
    ±660mV. Figure4 illustrates the maximum signal levels that can be  
    connected to the BL0921 Voltage Channel.  
    V1  
    V1A  
    V1N  
    V1B  
    +660mV  
    +
    -
    GAIN  
    Maximun input differential voltage  
    V1  
    ±660mV  
    V2  
    -
    V2  
    V1  
    Maximun input common-mode voltage  
    ±100mV  
    -660mV  
    GAIN  
    +
    AGND  
    Figure 4.  
    Voltage Channels  
    Voltage Channel must be driven from a common-mode voltage, i.e., the differential voltage signal  
    on the input must be referenced to a common mode (usually GND). The analog inputs of the  
    BL0921 can be driven with common-mode voltages of up to 100 mV with respect to GND.  
    However, best results are achieved using a common mode equal to GND.  
    Figure5 shows two typical connections for Channel V2. The first option uses a PT (potential  
    transformer) to provide complete isolation from the mains voltage. In the second option, the  
    BL0921 is biased around the neutral wire and a resistor divider is used to provide a voltage signal  
    that is proportional to the line voltage. Adjusting the ratio of Ra and Rb is also a convenient way  
    of carrying out a gain calibration on the meter.  
    http://www.belling.com.cn  
    - 8 -  
    3/15/2007  
    Total 13 Pages  
    SinglePhaseEnergyMeterIC  
    with Integrated Oscillator  
    BL0921  
    RF  
    CT  
    VAP  
    VN  
    +
    -
    CF  
    ±660mV  
    RF  
    AGND  
    CF  
    AGND  
    AGND  
    Phase Neutral  
    CF  
    Ra  
    Rb  
    Rv  
    AGND  
    AGND  
    ±660mV  
    VAP  
    VN  
    +
    -
    Phase Neutral  
    RF  
    AGND  
    CF  
    Ra >> RF  
    Rb+Rv=RF  
    AGND  
    AGND  
    Figure 5.  
    Current Channel Input  
    Typical Connections for Voltage Channels  
    ꢀ
    The voltage outputs from the current transducers are connected to the BL0921 here. As Figure6  
    shows that channel V1 has two voltage inputs, namely V1A and V1B. These inputs are fully  
    differential with respect to V1N. However, at any one time, only one is selected to perform the  
    power calculation.  
    V1  
    V2P  
    +
    +660mV  
    Maximun input differential voltage  
    ±660mV  
    V1  
    V2  
    -
    V2N  
    V2  
    Maximun input common-mode voltage  
    ±100mV  
    AGND  
    -660mV  
    Figure 6.  
    Current Channels  
    The analog inputs V1A, V1B and V1N have same maximum signal level restrictions as V2P and  
    V2N. However, Channel 1 has a programmable gain amplifier (PGA) with user-selectable gains of  
    1 or 16. These gains facilitate easy transducer interfacing. Figure illustrates the maximum signal  
    levels on V1A, V1B, and V1N. The maximum differential voltage is  
    gain selection. Again, the differential voltage signal on the inputs must be referenced to a common  
    mode, e.g., GND. The maximum common-mode signal is 100 mV.  
    ±660 mV divided by the  
    ±
    Figure7 shows a typical connection diagram for Channel V1. Here the analog inputs are being  
    used to monitor both the phase and neutral currents. Because of the large potential difference  
    between the phase and neutral, two CTs (current transformers) must be used to provide the  
    isolation. The CT turns ratio and burden resistor (Rb) are selected to give a peak differential  
    voltage of  
    ±660 mV/gain.  
    http://www.belling.com.cn  
    - 9 -  
    3/15/2007  
    Total 13 Pages  
    SinglePhaseEnergyMeterIC  
    with Integrated Oscillator  
    BL0921  
    RF  
    CT  
    V1A  
    +
    ±660mV  
    GAIN  
    Rb  
    CF  
    -
    IP  
    V1N  
    IN  
    AGND  
    -
    ±660mV  
    GAIN  
    Rb  
    CF  
    +
    V1B  
    CT  
    RF  
    Phase Neutral  
    CF  
    Ra  
    Ra >> RF  
    Rb  
    Rb+Rv=RF  
    AGND  
    ±660mV  
    Rv  
    V1A  
    V1N  
    V1B  
    +
    -
    AGND  
    IP  
    IN  
    AGND  
    -
    ±660mV  
    GAIN  
    Rb  
    CF  
    +
    CT  
    RF  
    Phase Neutral  
    Figure 7.  
    Fault Detection  
    Typical Connections for Current Channels  
    ꢀ
    The BL0921 incorporates a novel fault detection scheme that warns of fault conditions and allows  
    the BL0921 to continue accurate billing during a fault event. The BL0921 does this by  
    continuously monitoring both the phase and neutral (return) currents. A fault is indicated when  
    these currents differ by more than 12.5%. However, even during a fault, the output pulse rate on  
    F1 and F2 is generated using the larger of the two currents. Because the BL0921 looks for a  
    difference between the signals on V1A and V1B, it is important that both current transducers are  
    closely matched. On power-up the output pulse rate of the BL0921 is proportional to the product  
    of the signals on Channel V1A and Voltage Channel. If there is a difference of greater than 12.5%  
    between V1A and V1B on power-up, the fault indicator (FAULT) will go active after about one  
    second. In addition, if V1B is greater than V1A the BL0921 will select V1B as the input. The fault  
    detection is automatically disabled when the voltage signal on Channel 1 is less than 0.5% of the  
    full-scale input range. This will eliminate false detection of a fault due to noise at light loads.  
    If V1A is the active current input (i.e., is being used for billing), and the signal on V1B (inactive  
    input) falls by more than 12.5% of V1A, the fault indicator will go active. Both analog inputs are  
    filtered and averaged to prevent false triggering of this logic output. As a consequence of the  
    filtering, there is a time delay of approximately one second on the logic output FAULT after the  
    fault event. The FAULT logic output is independent of any activity on outputs F1 or F2. Figure 8  
    illustrates one condition under which FAULT becomes active. Since V1A is the active input and it  
    is still greater than V1B, billing is maintained on VIA, i.e., no swap to the V1B input will occur.  
    V1A remains the active input.  
    http://www.belling.com.cn  
    - 10 -  
    3/15/2007  
    Total 13 Pages  
    SinglePhaseEnergyMeterIC  
    with Integrated Oscillator  
    BL0921  
    V1A  
    V1B  
    FAULT  
    to ADC  
    V1A  
    V1B  
    current  
    sampling  
    0V  
    V1N  
    V1B < 87.5% V1A  
    Figure 8. Fault Conditions for Inactive Input Less than Active Input  
    Figure 9 illustrates another fault condition. If V1A is the active input (i.e., is being used for billing)  
    and the voltage signal on V1B (inactive input) becomes greater than 114% of V1A, the FAULT  
    indicator goes active, and there is also a swap over to the V1B input. The analog input V1B has  
    now become the active input. Again there is a time delay of about 1.2 seconds associated with this  
    swap. V1A will not swap back to being the active channel until V1A becomes greater than 114%  
    of V1B. However, the FAULT indicator will become inactive as soon as V1A is within 12.5% of  
    V1B. This threshold eliminates potential chatter between V1A and V1B.  
    V1B  
    V1A  
    FAULT  
    to ADC  
    V1A  
    V1B  
    V1N  
    current  
    sampling  
    0V  
    V1A < 87.5% V1B  
    Figure 9. Fault Conditions for Inactive Input Greater than Active Input  
    ꢀ
    Power Supply Monitor  
    The BL0921 contains an on-chip power supply monitor. If the supply is less than 4V  
    ±5% then  
    the BL0921 will go in an inactive state, i.e., no energy will be accumulated when the supply  
    voltage is below 4V. This is useful to ensure correct device operation at power up and during  
    power down. The power supply monitor has built-in hysteresis and filtering. This gives a high  
    degree of immunity to false triggering due to noisy supplies.  
    The trigger level is nominally set at 4V, and the tolerance on this trigger level is about  
    ±5%. The  
    power supply and decoupling for the part should be such that the ripple at VDD does not exceed  
    5V  
    ±
    5% as specified for normal operation.  
    ꢀ
    SLiM Technology  
    The BL0921 adopts the technology of SLiM (Smart Low current Management) to decrease the  
    static power greatly. The static power of BL0921 is about 15mW. This technology also decreases  
    the request for power supply design.  
    BL65XX series products used 0.35um CMOS process. The reliability and consistency are  
    advanced.  
    ꢀ OPERATION MODE  
    ꢀ
    Transfer Function  
    The BL0921 calculates the product of two voltage signals (on Channel 1 and Channel 2) and then  
    http://www.belling.com.cn  
    - 11 -  
    3/15/2007  
    Total 13 Pages  
    SinglePhaseEnergyMeterIC  
    with Integrated Oscillator  
    BL0921  
    low-pass filters this product to extract real power information. This real power information is then  
    converted to a frequency. The frequency information is output on F1 and F2 in the form of active  
    low pulses. The pulse rate at these outputs is relatively low. It means that the frequency at these  
    outputs is generated from real power information accumulated over a relatively long period of  
    time. The result is an output frequency that is proportional to the average real power. The average  
    of the real power signal is implicit to the digital-to-frequency conversion. The output frequency or  
    pulse rate is related to the input voltage signals by the following equation.  
    3.5×V (v)×V (i)×Gain× Fz  
    Freq =  
    VR2EF  
    Freq——Output frequency on F1 and F2 (Hz)  
    V(v)——Differential rms voltage signal on Channel 1 (volts)  
    V(i)——Differential rms voltage signal on Channel 2 (volts)  
    Gain——1 , 16 depending on the PGA gain selection, using logic inputs G  
    Vref——The reference voltage (2.4 V  
    ±8%) (volts)  
    Fz——One of four possible frequencies selected by using the logic inputs S0 and S1.  
    S1  
    0
    S0  
    0
    Fz(Hz)  
    1.7  
    0
    1
    3.4  
    1
    0
    6.8  
    1
    1
    13.6  
    ꢀ
    Frequency Output CF  
    The pulse output CF (Calibration Frequency) is intended for use during calibration. The output  
    pulse rate on CF can be up to 128 times the pulse rate on F1 and F2. The following Table shows  
    how the two frequencies are related, depending on the states of the logic inputs S0, S1 and SCF.  
    Mode  
    S1  
    0
    S0  
    0
    CF/F1 (or F2)  
    1
    2
    3
    4
    64  
    32  
    16  
    8
    0
    1
    1
    0
    1
    1
    Because of its relatively high pulse rate, the frequency at this logic output is proportional to the  
    instantaneous real power. As is the case with F1 and F2, the frequency is derived from the output  
    of the low-pass filter after multiplication. However, because the output frequency is high, this real  
    power information is accumulated over a much shorter time. Hence less averaging is carried out in  
    the digital-to-frequency conversion. With much less averaging of the real power signal, the CF  
    output is much more responsive to power fluctuations.  
    ꢀ
    Gain Selection  
    By select the digital input G0 and G1 voltage (5V or 0V), we can adjust the gain of current  
    http://www.belling.com.cn  
    - 12 -  
    3/15/2007  
    Total 13 Pages  
    SinglePhaseEnergyMeterIC  
    with Integrated Oscillator  
    BL0921  
    channel. We can see that while increasing the gain, the input dynamic range is decreasing.  
    G
    Gain  
    Maximum  
    Differential Signal  
    ±660mV  
    1
    0
    1
    16  
    ±41mV  
    ꢀ
    Analog Input Range  
    The maximum peak differential signal on Voltage Channel is  
    voltage is up to 100 mV with respect to GND.  
    ± 660 mV, and the common-mode  
    The analog inputs V1A, V1B, and V1N have the same maximum signal level restrictions as V2P  
    and V2N. However, The Current Channel has a programmable gain amplifier (PGA) with  
    user-selectable gains of 1,16. These gains facilitate easy transducer interfacing. The maximum  
    differential voltage is  
    ±660 mV and the maximum common-mode signal is ±100 mV.The  
    corresponding Max Frequency of CF/F1/F2 is shown in the following table.  
    S1 S0  
    Fz  
    Max Frequency  
    of F1, F2 (Hz)  
    CF Max Frequency (Hz)  
    DC  
    0.45  
    AC  
    0.22  
    DC  
    AC  
    0
    0
    1
    0
    1
    1.7  
    3.4  
    6.8  
    64×F1,F2=28.8  
    32×F1,F2=28.8  
    16×F1,F2=28.8  
    8×F1,F2=28.8  
    64×F1,F2=14.4  
    32×F1,F2=14.4  
    16×F1,F2=14.4  
    8×F1,F2=14.4  
    0
    1
    1
    0.90  
    1.80  
    0.45  
    0.90  
    1.80  
    13.6 3.60  
    ꢀ
    Package Dimensions  
    SOP16  
    Notice： Sample tested during initial release and after any redesign or process change  
    that may affect parameter. Specification subjects to change without notice. Please ask  
    for the newest product specification at any moment.  
    http://www.belling.com.cn  
    - 13 -  
    3/15/2007  
    Total 13 Pages  
    配单直通车
    BL0930(16DIP)产品参数
    型号:BL0930(16DIP)
    生命周期：Contact Manufacturer
    包装说明：,
    Reach Compliance Code：unknown
    风险等级：5.6
    Base Number Matches：1
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