BQ24046DRC原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

bq24050

bq24052

bq24055

www.ti.com.................................................................................................................................... SLUS940A –SEPTEMBER 2009–REVISED SEPTEMBER 2009

800mA, Single Cell Li-Ion Battery Charger With Automatic Adaptor/USB Detection

Check for Samples: bq24050 bq24052 bq24055

1

FEATURES

•

SYSTEM

•

CHARGING

–

Auto Input Source Detection (D+,D– Pins)

–

1% Charge Voltage Accuracy

–

No Device Transceiver Required

USB Friendly

10% Charge Current Accuracy

Pin Selectable USB 100mA and 500mA

Maximum Input Current Limit

–

Automatic Termination and Timer Disable

Mode (TTDM) for Absent Battery Pack With

Thermistor

–

Programmable Termination and Precharge

Threshold

–

Status Indication – Charging/Done

•

PROTECTION

Available in Small 2×2mm²DFN-10 or

2×3mm²DFN-12 Packages

–

30V Input Rating; with 6.6V Input

Overvoltage Protection

APPLICATIONS

–

Input Voltage Dynamic Power Management

•

Smart Phones

PDAs

MP3 Players

Low-Power Handheld Devices

125°C Thermal Regulation; 150°C Thermal

Shutdown Protection

–

OUT Short-Circuit Protection and ISET

short detection

Operation over JEITA Range via Battery

NTC - ½ Fast-Charge-Current at Cold, 4.06V

at Hot

–

Fixed 10 Hour Safety Timer

DESCRIPTION

The bq2405x series of devices are highly integrated Li-ion linear chargers devices targeted at space-limited

portable applications. The devices operate from either a USB port or AC adapter. The high input voltage range

with input overvoltage protection supports low-cost unregulated adapters.

The bq2405x has a single power output that charges the battery. A system load can be placed in parallel with the

battery as long as the average system load does not keep the battery from charging fully during the 10 hour

safety timer.

The battery is charged in three phases: conditioning, constant current and constant voltage. In all charge phases,

an internal control loop monitors the IC junction temperature and reduces the charge current if an internal

temperature threshold is exceeded. (Description continued on next page)

bq24050/2

Adaptor

1

2

3

4

5

10

9

IN

System Load

DC+

GND

OUT

TS

1.5kW

Battery Pack

+

ISET

VSS

8

CHG

ISET2

D-

1mF

1kW

2kW

1mF

7

PRETERM

D+

OR

6

VDD

TTDM

USB Port

ISET/100/500 mA

VBUS

GND

D+

D-

Host

D-

Disconnect after Detection

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

bq24050

bq24052

bq24055

SLUS940A –SEPTEMBER 2009–REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION

The charger power stage and charge current sense functions are fully integrated. The charger function has high

accuracy current and voltage regulation loops, charge status display, and charge termination. The precharge

current and termination current threshold are programmed via an external resistor. The fast charge current value

is also programmable via an external resistor.

AVAILABLE OPTIONS

V_O(REG)

4.2 V

V_OVP

6.6 V

R_NTC

10 kΩ

100 kΩ

10 kΩ

PG

No

PACKAGE

DEVICES

bq24050

bq24052

bq24055

MARKING

CVC

10 PIN 2 × 2mm²DFN

10 PIN 2 × 2mm ²DFN

12 PIN 2 × 3mm ²DFN

4.2 V

No

CGT

4.2 V

Yes

CGU

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

IN (with respect to VSS)

–0.3 to 30

–0.3 to 7

V

OUT (with respect to VSS)

Input Voltage

PRE-TERM, ISET, ISET2, TS, CHG, PG, D+, D–,

(with respect to VSS)

Input Current

IN

1.25

15

A

Output Current (Continuous) OUT

Output Sink Current

CHG

mA

1µF between IN and GND,

1µF between TS and GND,

2µF between OUT and GND,

x5R Ceramic or equivalent

Electrostatic discharge

(IEC61000-4-2)⁽²⁾

8 contact

15 Air

ESD

IN, OUT, TS

kV

T_J

Junction temperature

Storage temperature

–40 to 150

–65 to 150

°C

T_STG

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage

values are with respect to the network ground terminal unless otherwise noted.

(2) The test was performed on IC pins that may potentially be exposed to the customer at the product level. The bq2405x IC requires a

minimum of the listed capacitance, external to the IC, to pass the ESD test. The D+ D- lines require clamp diodes such as

CM1213A-02SR from CMD to protect the IC for this testing.

PACKAGE DISSIPATION RATINGS^{(1) (2)}

T

_A≤ 25°C

DERATING FACTOR

T_A> 25°C

PACKAGE

R_θJA

R_θJC

POWER RATING

2 × 2 mm²

2 × 3 mm²

60°C/W

58°C/W

8.8°C/W

5.3°C/W

1.66W

16.6mW/°C

17.2mW/°C

1.72W

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a copper pad on the board. This is

connected to the ground plane by a 2×3 via matrix

2

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RECOMMENDED OPERATING CONDITIONS⁽¹⁾

MIN

3.5

NOM

28

UNIT

V

IN voltage range

V_IN

IN operating voltage range, Restricted by V_DPMand V_OVP

Input current, IN pin

4.45

6.45

0.8

V

I_IN

A

I_OUT

Current, OUT pin

0.8

A

T_J

Junction temperature

0

1

125

10

°C

kΩ

R_PRE-TERM

R_ISET

Programs precharge and termination current thresholds

Fast-charge current programming resistor

10k NTC thermistor range without entering TTDM, bq24050/55

100k NTC thermistor range without entering TTDM, bq24052

0.675

1.66

24

49.9

258

885

R_TS

(1) Operation with V_INless than 4.5V or in drop-out may result in reduced performance.

ELECTRICAL CHARACTERISTICS

Over junction temperature range 0°C ≤ T_J≤ 125°C and recommended supply voltage (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT

UVLO

Undervoltage lock-out Exit

V_IN: 0V → 4V Update based on sim/char

3.15

175

3.3

3.45

280

V

V_IN: 4V→0V,

V_{UVLO_FALL}= V_{UVLO_RISE}–V_HYS-UVLO

V_{HYS_UVLO}

Hysteresis on V_{UVLO_RISE}falling

230

mV

Input power good detection threshold (Input power good if V_IN> V_OUT+ V_IN-DT); V_OUT

=

V_IN-DT

30

80

31

45

145

mV

μs

is V_OUT+ V_IN-DT

3.6V, V_IN: 3.5V → 4V

V_HYS-INDT

t_{DGL(PG_PWR)}

Hysteresis on V_IN-DTfalling

V_OUT= 3.6V, V_IN: 4V → 3.5V

Time measured from V_IN: 0V → 5V 1μs rise-time to

PG = low, V_OUT= 3.6V

Deglitch time on exiting sleep.

t_{DGL(PG_NO-}

Deglitch time on V_HYS-INDTpower

down. Same as entering sleep.

Time measured from V_IN: 5V → 3.2V 1μs fall-time

to PG = High Z, V_OUT= 3.6V

29

ms

PWR)

V_OVP

Input over-voltage protection threshold V_IN: 5V → 7V (50/52/55)

6.5

6.65

113

95

6.8

V

t_DGL(OVP-SET)

V_HYS-OVP

Input over-voltage blanking time

Hysteresis on OVP

V_IN: 5V → 12V

V_IN: 11V → 5V

μs

mV

Time measured from V_IN: 12V → 5V 1μs fall-time

to PG = LO

t_DGL(OVP-REC)

Deglitch time exiting OVP

30

4.4

4.3

μs

Feature active in USB mode; Limit Input Source

Current to 50mA; V_OUT=3.5V; R_ISET= 825Ω

4.34

4.24

4.46

4.36

USB/Adaptor low input voltage

protection. Restricts lout at V_IN-DPM

V_IN-DPM

V

Feature active in Adaptor mode; Limit Input Source

Current to 50mA; V_OUT=3.5V; R_ISET= 825Ω

USB input I-Limit 100mA

USB input I-Limit 500mA

ISET2 = Float; R_ISET= 825Ω

ISET2 = High; R_ISET= 825Ω

85

92

100

500

I_IN-USB-CL

mA

430

462

ISET SHORT CIRCUIT TEST

Highest Resistor value considered a

fault (short). Monitored for Iout>90mA to Reset. USB100 mode.

Riset: 600Ω → 250Ω, Iout latches off. Cycle power

R_{ISET_SHORT}

t_{DGL_SHORT}

I_{OUT_CL}

280

500

Ω

ms

A

Deglitch time transition from ISET

short to Iout disable

Clear fault by cycling IN or TS

1

Maximum OUT current limit

Regulation (Clamp)

V_IN= 5V, V_OUT= 3.6V, V_ISET2=Low, Riset: 600Ω →

250Ω, Iout latches off after t_DGL-SHORT

1.05

0.75

1.4

BATTERY SHORT PROTECTION

OUT pin short-circuit detection

threshold/ precharge threshold

V_OUT(SC)

V_OUT:3V → 0.5V, no deglitch

0.8

77

15

0.85

V

Recovery ≥ V_OUT(SC)+ V_OUT(SC-HYS); Rising, no

Deglitch

V_OUT(SC-HYS)

I_OUT(SC)

OUT pin Short hysteresis

mV

mA

Source current to OUT pin during

short-circuit detection

10

20

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SLUS940A –SEPTEMBER 2009–REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

Over junction temperature range 0°C ≤ T_J≤ 125°C and recommended supply voltage (unless otherwise noted)

PARAMETER

QUIESCENT CURRENT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_OUT(PDWN)

I_OUT(DONE)

I_IN(STDBY)

Battery current into OUT pin

V_IN= 0V

1

6

μA

OUT pin current, charging terminated V_IN= 6V, V_OUT> V_OUT(REG)

Standby current into IN pin

Active supply current, IN pin

TS = LO, V_IN≤ 6V

125

μA

TS = open, V_IN= 6V, TTDM – no load on OUT pin,

V_OUT> V_OUT(REG), IC enabled

I_CC

0.8

1

mA

BATTERY CHARGER FAST-CHARGE

V_OUT(REG)

V_{O_HT(REG)}

Battery regulation voltage

V_IN=5.5V, I_OUT=25mA, V_TS-45°C≤ V_TS≤ V_TS-0°C

V_IN=5.5V, I_OUT=25mA, V_TS-60°C≤ V_TS≤ V_TS-45°C

4.16

4.02

4.20

4.06

4.23

4.1

V

Battery hot regulation Voltage

Programmed Output “fast charge”

current range

V_OUT(REG)> V_OUT> V_LOWV, V_IN= 5V, ISET2=Lo,

R_ISET= 675 to 10.8kΩ

I_OUT(RANGE)

10

800

500

mA

Adjust VIN down until I_OUT= 0.5A, V_OUT= 4.15V,

R_ISET= 675 , ISET2=Lo (Adaptor Mode); Tj ≤

100°C

V_DO(IN-OUT)

I_OUT

Drop-Out, VIN – VOUT

325

mV

A

Output “fast charge” formula

V_OUT(REG)> V_OUT> V_LOWV, V_IN= 5V, ISET2=Lo

R_ISET= K_ISET/I_OUT50 < I_OUT< 800 mA

R_ISET= K_ISET/I_OUT25 < I_OUT< 50 mA

R_ISET= K_ISET/I_OUT10 < I_OUT< 25 mA

K_ISET/R_ISET

540

510

480

350

570

600

680

K_ISET

Fast charge current factor

527

AΩ

520

PRECHARGE – SET BY PRETERM PIN

Pre-charge to fast-charge transition

threshold

V_LOWV

2.4

2.5

70

32

2.6

V

Deglitch time on pre-charge to

fast-charge transition

t_DGL1(LOWV)

μs

ms

Deglitch time on fast-charge to

pre-charge transition

t_DGL2(LOWV)

I_PRE-TERM

Refer to the Termination Section

Pre-Charge Current Level, Default

Setting

V_OUT< V_LOWV; R_PRE-TERM= High Z (≥13kΩ); R_ISET

= 1k

18

20

22

%I_OUT-CC

%

PRECHG

Pre-charge current formula

% Pre-charge Factor

R_PRE-TERM= K_PRE-CHG(Ω/%) × %_PRE-CHG(%)

R_PRE-TERM/K_PRE-CHG

V_OUT< V_LOWV, V_IN= 5V, R_PRE-TERM= 2k to 10kΩ;

R_ISET= 1080Ω , R_PRE-TERM= K_PRE-CHG

×

90

84

100

110

117

Ω/%

%I_FAST-CHG, where %I_FAST-CHGis 20 to 100%

K_PRE-CHG

V_OUT< V_LOWV, V_IN= 5V, R_PRE-TERM= 1k to 2kΩ;

R_ISET= 1080Ω, R_PRE-TERM= K_PRE-CHG

×

%I_FAST-CHG, where %I_FAST-CHGis 10% to 20%

TERMINATION – SET BY PRE-TERM PIN

Termination Current Threshold,

Default Setting

V_OUT> V_RCH; R_PRE-TERM= High Z (≥13kΩ); R_ISET=

1k

9

10

R_PRE-TERM/ K_TERM

11

%I_OUT-CC

%

TERM

Termination Current Threshold

Formula

R_PRE-TERM= K_TERM(Ω/%) × %TERM (%)

V_OUT> V_RCH, V_IN= 5V, R_PRE-TERM= 2k to 10kΩ ;

R_ISET= 750Ω; K_TERM× %I_FAST-CHG, where

%I_FAST-CHGis 10 to 50%

182

200

199

75

216

224

81

K_TERM

% Term Factor

Ω/%

μA

V_OUT> V_RCH, V_IN= 5V, R_PRE-TERM= 1k to 2kΩ ;

R_ISET= 750Ω; K_TERM× %I_FAST-CHG, where

%I_FAST-CHGis 5 to 10%

174

71

Current for programming the term.

and pre-chg with resistor. I_Term-Startis

the initial PRE-TERM curent.

I_PRE-TERM

R_PRE-TERM= 2k, V_OUT= 4.15V

%TERM

Termination current formula

R_TERM/ K_TERM

29

%

t_DGL(TERM)

Deglitch time, termination detected

ms

Elevated PRE-TERM current for,

t_Term-Start, during start of charge to

prevent recharge of full battery,

I_Term-Start

80

85

92

μA

Elevated termination threshold initially

active for t_Term-Start

t_Term-Start

1.25

min

4

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www.ti.com.................................................................................................................................... SLUS940A –SEPTEMBER 2009–REVISED SEPTEMBER 2009

ELECTRICAL CHARACTERISTICS (continued)

Over junction temperature range 0°C ≤ T_J≤ 125°C and recommended supply voltage (unless otherwise noted)

PARAMETER

RECHARGE OR REFRESH

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Recharge detection threshold –

Normal Temp

V_O(REG)

0.120

-

V_O(REG

-0.095

V_O(REG)

0.070

-

V_IN= 5V, V_TS= 0.5V, V_OUT: 4.25V → V_RCH

V_IN= 5V, V_TS= 0.2V, V_OUT: 4.15V → V_RCH

V

V_RCH

Recharge detection threshold – Hot

Temp

V_{O_HT(REG)}V_{O_HT(REG)}V_{O_HT(REG)}

-0.130

-0.105

-0.080

Deglitch time, recharge threshold

detected

V_IN= 5V, V_TS= 0.5V, V_OUT: 4.25V → 3.5V in 1μs;

t_DGL1(RCH)is time to ISET ramp

t_DGL1(RCH)

t_DGL2(RCH)

29

ms

Deglitch time, recharge threshold

detected in OUT-Detect Mode

V_IN= 5V, V_TS= 0.5V, V_OUT= 3.5V inserted;

t_DGL2(RCH)is time to ISET ramp

3.6

BATTERY DETECT ROUTINE (NOTE: In Hot Mode V_O(REG)becomes V_{O_HT(REG)}

)

VOUT Reduced regulation during

battery detect

V_O(REG)

0.450

-

V_O(REG

-0.400

V_O(REG)-

0.350

V_REG-BD

V

I_BD-SINK

Sink current during V_REG-BD

V_IN= 5V, V_TS= 0.5V, Battery Absent

7

10

mA

ms

t_DGL(HI/LOW

Regulation time at V_REGor V_REG-BD

25

REG)

V_O(REG)

0.150

-

V_O(REG)

0.100

-

V_O(REG)-

0.050

V_BD-HI

V_BD-LO

High battery detection threshold

Low battery detection threshold

V_IN= 5V, V_TS= 0.5V, Battery Absent

V

V_REG-BD

+0.050

V_REG-BD

+0.100

V_REG-BD

+0.150

BATTERY CHARGING TIMERS AND FAULT TIMERS

Restarts when entering Pre-charge; Always

enabled when in pre-charge.

t_PRECHG

t_MAXCH

Pre-charge safety timer value

Charge safety timer value

1700

1940

2250

s

Clears fault or resets at UVLO, TS ("CE") disable,

OUT Short, exiting LOWV and Refresh

34000

38800

45000

BATTERY-PACK NTC MONITOR (Note 1); TS pin: bq24050/5: 10k NTC; bq24052: 100k NTC; See TS section for thermistor information

NTC bias current; 10k NTC

thermsistor, bq24050/5

I_NTC-10k

V_TS= 0.3V

V_TS= 0V

48

4.8

27

50

5

52

5.2

34

μA

NTC bias current; 100k NTC

thermsistor, bq24052

I_NTC-100k

bq24050/5 bias current when

Charging is disabled.

I_NTC-DIS-10k

I_NTC-DIS-100k

30

5

bq24052 bias current when Charging

is disabled.

V_TS= 0V

4.4

5.8

INTC is reduced prior to entering

TTDM to keep cold thermistor from

entering TTDM, bq24050/5

I_{NTC-FLDBK-10k}

V_TS: Set to 1.525V

4

5

6.5

μA

INTC is reduced prior to entering

I_{NTC-FLDBK-100k}TTDM to keep cold thermistor from

entering TTDM, bq24052

V_TS: Set to 1.525V

1.1

1.5

1.9

μA

Termination and timer disable mode

Threshold – Enter

V_TTDM(TS)

V_TS: 0.5V → 1.7V; Timer Held in Reset

1550

1600

1650

mV

V_HYS-TTDM(TS)Hysteresis exiting TTDM

V_TS: 1.7V → 0.5V; Timer Enabled

100

1950

57

mV

ms

μs

V_CLAMP(TS)

TS maximum voltage clamp

V_TS= Open (Float)

1800

2000

Deglitch exit TTDM between states

Deglitch enter TTDM between states

t_DGL(TTDM)

8

INTC adjustment (90 to 10%; 45 to 6.6uA) takes

place near this spec threshold.

V_TS: 1.425V → 1.525V

TS voltage where INTC is reduce to

keep thermistor from entering TTDM

V_{TS_I-FLDBK}

1475

mV

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SLUS940A –SEPTEMBER 2009–REVISED SEPTEMBER 2009.................................................................................................................................... www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

Over junction temperature range 0°C ≤ T_J≤ 125°C and recommended supply voltage (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

C_TS

Optional Capacitance – ESD

0.22

μF

bq24050/2/5 Low temperature CHG

Pending

Low Temp Charging to Pending;

V_TS: 1V → 1.5V

V_TS-0°C

1205

1230

86

1255

mV

Charge pending to low temp charging; V_TS: 1.5V →

1V

V_HYS-0°C

V_TS-10°C

V_HYS-10°C

V_TS-45°C

V_HYS-45°C

V_TS-60°C

V_HYS-60°C

Hysteresis at 0°C

Normal charging to low temp charging; V_TS: 0.5V

→ 1V

Low temperature, half charge

Hysteresis at 10°C

765

263

170

790

35

815

293

186

Low temp charging to normal CHG;

V_TS: 1V → 0.5V

Normal charging to high temp CHG;

V_TS: 0.5V → 0.2V

High temperature at 4.1V

Hysteresis at 45°C

278

10.7

178

11.5

High temp charging to normal CHG;

V_TS: 0.2V → 0.5V

High temp charge to pending;

V_TS: 0.2V → 0.1V

High temperature Disable

Hysteresis at 60°C

Charge pending to high temp CHG;

V_TS: 0.1V → 0.2V

Normal to Cold Operation: V_TS: 0.6V → 1V

Cold to Normal Operation: V_TS: 1.0V → 0.6V

Battery charging

50

12

30

88

t_{DGL(TS_10C)}

Deglitch for TS thresholds: 10C.

ms

t_DGL(TS)

Deglitch for TS thresholds: 0/45/60C.

ms

V_TS-EN-10k

Charge Enable Threshold, (10k NTC) V_TS: 0V → 0.175V;

80

96

mV

HYS below V_TS-EN-10kto Disable, (10k

V_TS: 0.125V → 0V;

NTC)

V_{TS-DIS_HYS-10k}

12

150

50

mV

Charge Enable Threshold, (100k

V_TS: 0V → 0.175V

NTC)

V_TS-EN-100k

140

160

V_{TS-DIS_HYS-}

HYS below V_TS-EN-100kto Disable,

V_TS: 0.125V → 0V;

(100k NTC)

100k

THERMAL REGULATION

T_J(REG)

Temperature regulation limit

125

155

20

°C

T_J(OFF)

Thermal shutdown temperature

Thermal shutdown hysteresis

T_J(OFF-HYS)

LOGIC LEVELS ON ISET2

V_IL

V_IH

I_IL

Logic LOW input voltage

Sink more than 8μA

0.4

V

Logic HIGH input voltage

Sink current required for LO

Source current required for HI

ISET2 Float Voltage

Source more than 8μA

1.4

2

9

8

μA

mV

I_IH

1.1

650

V_FLT

900

1200

6

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ELECTRICAL CHARACTERISTICS (continued)

Over junction temperature range 0°C ≤ T_J≤ 125°C and recommended supply voltage (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

D+/D– DETECTION – bq24050/2/5

DetectionTime from start of D+/D-

detection to latched output

t=0 at D– pulled-up > 0.5V or D+ pulled up

externally, >0.8V

t_DPDM

V_D+

I_D+

65

ms

V

Bias at D+, during detection routine

Can source at least 200μA

0.475

50

0.6

0.7

1.5

Current Limit at D+ pin, during

detection routine

V_D+= 0V

mA

Current Sink at D- pin, during

detection routine

I_D–

V_D-= 0.5V

V_D+= 5V

V_D-= 5V

100

150

1

μA

D+ leakage when not in detection

mode

I_{D+_LEAK}

D– leakage when not in detection

mode

I_{D–_LEAK}

1

μA

V

V_{DPDM_0.4V}

D– Comparator Threshold Rising

D– Comparator Hysteresis

0.35

0.75

0.45

V_{DPDM_HYS_0.4}

42

mV

V

V_{DPDM_0.8V}

D+/D– Comparator Threshold Rising

D+/D– Comparator Hysteresis

0.875

V_{DPDM_HYS_0.8}

mV

V

LOGIC LEVELS ON CHG AND PG

V_OL

I_lkg

Output LOW voltage

I_SINK= 5mA

0.4

1

V

Leakage current into IC

V _CHG= 5V, V _PG= 5V

μA

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PIN CONFIGURATION

bq24050/2

bq24055

1

2

3

4

5

10

9

1

2

3

4

5

6

12

11

10

9

IN

OUT

TS

OUT

TS

ISET

VSS

ISET

VSS

8

CHG

ISET2

D-

CHG

ISET2

D-

7

PRETERM

D+

PRETERM

D+

6

8

7

PG

NC

PIN FUNCTIONS

NAME

bq24050/2

bq24055

I/O DESCRIPTION

Input power, connected to external DC supply (AC adapter or USB port). Expected range

of bypass capacitors 1μF to 10μF, connect from IN to V_SS

IN

1

I

.

Battery Connection. System Load may be connected. Average load should not be

excessive, allowing battery to charge within the 10 hour safety timer window. Expected

range of bypass capacitors 1μF to 10μF.

OUT

10

12

4

O

Programs the Current Termination Threshold (5 to 50% of Iout which is set by ISET) and

Sets the Pre-Charge Current to twice the Termination Current Level.

PRE-TERM

4

I

Expected range of programming resistor is 1k to 10kΩ (2k: I_OUT/10 for term; I_OUT/5 for

precharge)

Programs the Fast-charge current setting. External resistor from ISET to VSS defines fast

charge current value. Range is 10.8k (50mA) to 675 Ω (800mA).

ISET

2

7

2

9

I

Programming the Input/Output Current Limit for the USB or Adaptor source: High =

500mAmax, Low = ISET, FLOAT = 100mA max. D+D– Detection initially sets the charge

threshold and requires ISET2 to change states to take control.

ISET2

Temperature sense pin connected to ‘50/55 –10k at 25C NTC thermistor, ’52 – 100k NTC

at 25°C, in the battery pack. Floating TS Pin or pulling High puts part in TTDM and disable

TS monitoring, Timers and Termination. Pulling pin Low disables the IC ( CE function). If

NTC sensing is not needed, connect this pin to VSS through an external ‘50/55-10kΩ

/’52-100kΩ resistor. A ‘50/55-250kΩ/’52-880kΩ from TS to ground will prevent IC entering

TTDM when battery with thermistor is removed.

(1)

TS

9

11

I

VSS

3

8

3

–

Ground terminal

Low (FET on) indicates charging and Open Drain (FET off) indicates no Charging or

Charge complete.

CHG

10

O

Low (FET on) indicates the input voltage is above UVLO and the OUT (battery) voltage

and less than V_OVP

PG

–

6

O

D+

D–

NC

5

6

–

5

8

7

I

USB port D+ input connection

USB port D– input connection

NA Do not make connection to this pin (internal use) – Do not route through this pin

There is an internal electrical connection between the exposed thermal pad and the VSS

Thermal

PAD and

Package

Pad

pin of the device. The thermal pad must be connected to the same potential as the VSS

pin on the printed circuit board. Do not use the thermal pad as the primary ground input

for the device. VSS pin must be connected to ground at all times.

Pad 2x2mm²

–

2x3mm²

(1) Spins have different pin definitions

8

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Typical Application Circuit: bq24050/2

I_{OUT_FAST_CHG}= 540mA; I_{OUT_PRE_CHG}= 108mA; I_{OUT_TERM}= 54mA

bq24050/2

Adaptor

1

2

3

4

5

10

9

System Load

IN

DC+

GND

OUT

TS

Battery Pack

+

1.5kW

ISET

VSS

8

CHG

ISET 2

D-

1kW

1mF

7

PRETERM

D+

OR

6

VDD

2kW

TTDM

USB Port

ISET/100/500mA

VBUS

GND

D+

D-

Host

D-

Disconnected after Detection

Typical Application Circuit: bq24055

I_{OUT_FAST_CHG}= 540mA; I_{OUT_PRE_CHG}= 108mA; I_{OUT_TERM}= 54mA

bq24055

Adaptor

1

2

3

4

5

6

12

11

10

9

System Load

DC+

GND

IN

OUT

TS

1.5kW

Battery Pack

+

ISET

VSS

1kW

2kW

CHG

ISET2

D-

1mF

PRETERM

D+

OR

8

VDD

TTDM

USB Port

7

PG

NC

ISET/100/500 mA

VBUS

GND

D+

D-

Host

D-

Disconnected after Detection

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FUNCTIONAL BLOCK DIAGRAM

Internal Charge

Current Sense

w/Multiple Outputs

IN

OUT

+

80

mV

Input

Power

Detect

-

IN

OUT

+

_

+

OUT

+

_

OUTREG

IN-DPM

REF

I

x 1.5 V

Charge

Pump

OUT

540 AW

T_J°C

_

+

125°C

REF

FAST CHARGE

PRE-CHARGE

Thermal Regulation

ISET

IN

_

+

1.5 V

Pre-CHG Reference

_

+

USB Sense

Resistor

USB100/500

REF

T

^oC

J

_

+

_

o

150 C

Term Reference

REF

Thermal Shutdown

Charge

Pump

75mA⁺

X2 Gain (1:2)

Term:Pre-CHG

PRE-TERM

IN

⁺Increased from 75mA to 85mA for

_

+

1^stminute of charge.

OVP

REF

CHG

+

_

On During

1st Charge Only

OUT

TERM_EN

+

_

V

ON:

OFF:

ISET2 (LOW = ISET, HI = USB500,

FLOAT = USB100)

0.9 V Float

CHARGE

CONTROL

PG

bq24055 Only

V

COLD-10C

_

+

HI = Half CHG (JEITA)

HI = 4.06Vreg (JEITA)

_

+

V

HOT-45C

0.6 V(200 mA)

V

COLD-FLT

_

+

D+

D-

D+ / D-

DETECTION

CONTROL

- On Initial

_

+

V

HOT-FLT

LO = TTDM MODE

HI = Suspend CHG

Supply Power

Connection

TS

V

TTDM

(100 mA)

+

_

HI = CHIP DISABLE

+

_

V

DISABLE

Cold Temperature

Sink Current

= 45mA

Disable

Sink Current

= 20mA

V_CLAMP=1.4 V

+

_

5mA

45mA

10

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TYPICAL OPERATIONAL CHARACTERISTICS

SETUP: bq24055 typical applications schematic; V_IN= 5V, V_BAT= 3.6V (unless otherwise indicated)

R_ISET= 1k; I_{OUT_FAST_CHG}= 540mA; R_{PAC_TERM}= 2k; I_{OUT_PRE_CHG}= 108mA; I_{OUT_TERM}= 54mA

Power UP, DOWN, OVP, Disable and Enable Waveforms

Vin

2V/div

D+

2V/div

D+

1V/div

2V/div

Vd-

1V/div

Viset

Vchg

5V/div

Viset

Vchg

2V/div

t - time - 100ms/div

t - time - 10ms/div

No signal detected on D+ or D-. After 500ms, the detection

routine is forced to run.

Detected D- line pulled to 0.6V and the detection routine is

started.

Figure 1. D+ D- Detection for Adaptor Hot Plug

Figure 2. D+ D- Detection for Unknown Source Hot Plug

Vin

2V/div

End of

Detection

Routine

D+

1V/div

D+

1V/div

Vd-

Detection Routine

Started

1V/div

Vd-

5V/div

Vchg

5V/div

USB Communication

Between Host and

Device Receiver

Vchg

Viset

2V/div

Viset

2V/div

t - time - 100ms/div

t - time - 50ms/div

(Device transceiver is "dead") After 500ms, the detection

routine is forced to run.

Figure 3. D+ D- Detection for USB Hot Plug no Pullup

Figure 4. D+ D- Detection for USB Hot Plug with Pullup

Vin

5V/div

Vchg

2V/div

Vchg

Vpg

2V/div

Vpg

2V/div

Viset

2V/div

t - time - 20ms/div

t - time - 100ms/div

Figure 5. OVP 8V Adaptor – Hot Plug

Figure 6. OVP from Normal Operation –

V_IN= 0V→5V→8V→5V

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TYPICAL OPERATIONAL CHARACTERISTICS (continued)

SETUP: bq24055 typical applications schematic; V_IN= 5V, V_BAT= 3.6V (unless otherwise indicated)

R_ISET= 1k; I_{OUT_FAST_CHG}= 540mA; R_{PAC_TERM}= 2k; I_{OUT_PRE_CHG}= 108mA; I_{OUT_TERM}= 54mA

Vpg

5V/div

Vpg

2V/div

Vchg

2V/div

Vout

500mV/div

Vts

2V/div

Viset

2V/div

Battery Detect Mode

Vin

t - time - 50ms/div

5V/div

10kΩ resistor from TS to GND. 10kΩ is shorted to disable the

IC.

t - time - 20ms/div

Fixed 10kΩ resistor, between TS and GND.

Figure 7. TS Enable and Disable

Figure 8. Hot Plug Source w/No Battery – Battery Detection

1 Battery Detect Cycle

1V/div

Vout

Vin

2V/div

Vchg

Vout

Viset

500mV/div

5V/div

1V/div

Viset

1V/div

Vts

1V/div

Vts

2V/div

Entered TTDM

t - time - 5ms/div

t - time - 10ms/div

Figure 9. Battery Removal – GND Removed 1st,

Figure 10. Battery Removal with OUT and

TS Disconnect 1st, With 100–Ω Load

42-Ω Load

Vout

1V/div

Vchg

Battery Declared Absent

5V/div

Viset

1V/div

V_0.1 W_OUT

100mV/div

t - time - 20ms/div

Continuous battery detection when not in TTDM.

Figure 11. Battery Removal With Fixed TS = 0.5V

12

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TYPICAL OPERATIONAL CHARACTERISTICS (continued)

SETUP: bq24055 typical applications schematic; V_IN= 5V, V_BAT= 3.6V (unless otherwise indicated)

R_ISET= 1k; I_{OUT_FAST_CHG}= 540mA; R_{PAC_TERM}= 2k; I_{OUT_PRE_CHG}= 108mA; I_{OUT_TERM}= 54mA

PROTECTION CIRCUITS WAVEFORMS

1V/div

5V/div

1V/div

Vout

Vchg

Vout

1V/div

Vchg 2V/div

Battery

Threshold

Reached

500mV/div

Viset

I

Clamped Current

OUT

V_0.1 W_OUT

100mV/div

I

Short Detected

SET

and Latched Off

t - time - 500ms/div

t - time - 200ms/div

CH4: Iout (1A/Div)Battery voltage swept from 0V to 4.25V to

3.9V.

CH4: Iout (1A/Div)

Figure 12. Battery Charge Profile

Figure 13. ISET Shorted During Normal Operation

Vchg

Vin

2V/div

Vchg

Vin

2V/div

500mV/div

Viset

Short Detected in 100mA

mode and Latched Off

V_0.1W_OUT

20mV/div

Viset

500mV/div

V_0.1 W_OUT

20mV/div

t - time - 1ms/div

t - time - 5ms/div

CH4: Iout (0.2A/Div)

Figure 14. ISET Shorted Prior to USB Power Up

Figure 15. DPM – Adaptor Current Limits – V_INRegulated to

4.3V

Vin

2V/div

Vchg

2V/div

Vout

1V/div

2V/div

Enters

Thermal

Regulation

Exits

Thermal

Regulation

Viset

1V/div

V_0.1W_OUT

Viset

V_0.1W_OUT

500mV/div

20mV/div

50mV/div

t - time - 500ms/div

t - time - 1s/div

The IC temperature rises to 125°C and enters thermal

regulation. Charge current is reduced to regulate the IC at

125°C. VIN is reduced, the IC temperature drops, the charge

current returns to the programmed value.

Figure 16. DPM – USB Current Limits – V_INRegulated to 4.4V

Figure 17. Thermal Reg. – V_INIncreases

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TYPICAL OPERATIONAL CHARACTERISTICS (continued)

SETUP: bq24055 typical applications schematic; V_IN= 5V, V_BAT= 3.6V (unless otherwise indicated)

R_ISET= 1k; I_{OUT_FAST_CHG}= 540mA; R_{PAC_TERM}= 2k; I_{OUT_PRE_CHG}= 108mA; I_{OUT_TERM}= 54mA

546

Kiset

544

Vin

1V/div

542

Low to High Currents

540

(may occur in recharge to fast charge transion)

Viset

1V/div

5V/div

538

536

534

Vchg

Vpg

High to Low Currents

(may occur in Voltage Regulation - Taper Current)

5V/div

t - time - 20ms/div

532

Vin swept from 5V to 3.9V to 5V, Vbat = 4V

530

528

.15

0

0.2

0.4

0.6

0.8

I

- Output Current - A

O

Figure 18. Entering and Exiting Sleep Mode

Figure 19. Kiset for Low and High Currents

4.212

4.2

V

@ 0°C

R

100 Ω

O

OUT =

4.199

4.21

4.208

4.206

4.204

4.202

4.2

V

@ 25°C

reg

4.198

4.197

V

@ 85°C

reg

V

@ 25°C

@ 85°C

O

4.196

4.195

4.194

4.193

4.192

V

O

V

@ 0°C

reg

4.198

4.196

4.5

5

5.5

- Input Voltage DC - V

6

6.5

0

0.2

0.4

0.6

0.8

1

V

I

- Output current - A

O

Figure 20. Line Regulation

Figure 21. Load Regulation Over Temperature

363.4

363.2

I

@ 25°C

O

363

362.8

I

@ 85°C

O

362.6

362.4

362.2

I

@ 0°C

O

362

361.8

2.5

3

3.5

4

4.5

V

- Output Voltage - V

O

Figure 22. Current Regulation Overtemperature

14

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FUNCTIONAL GENERAL DESCRIPTION

The bq2405x is a highly integrate family of 2×2 or 2×3mm single cell Li-Ion chargers. The charger can be used to

charge a battery, power a system or both. The charger has three phases of charging: Pre-charge to recover a

fully discharged battery, fast-charge constant current to supply the buck charge safely and voltage regulation to

safely reach full capacity. The charger is very flexible, allowing programming of the fast-charge current,

pre-charge current and termination. This charger is designed to work with a USB connection or Adaptor (DC out).

The charger also checks to see if a battery is present.

The charger also comes with a full set of safety features: JEITA Temperature Standard, Over-Voltage Protection,

DPM-IN, Safety Timers, and ISET short protection. All of these features and more are described in detail below.

The charger is designed for a single power path from the input to the output to charge a single cell Li-Ion battery

pack. Upon application of a 5VDC power source the D+/D– detection routine is run to determine if the source is

an Adaptor or a USB port. This feature is useful, when the battery is discharged (USB transceiver dead) or there

is no transceiver, by early detection of an adaptor, thus allowing initial charging at the adaptor level. ISET and

OUT short checks are performed in parallel with the detection routine to assure a proper charge cycle.

If the battery voltage is below the LOWV threshold, the battery is considered discharged and a preconditioning

cycle begins. The amount of precharge current can be programmed using the PRE-TERM pin which programs a

percent of fast charge current (10 to 100%) as the precharge current. This feature is useful when the system load

is connected across the battery “stealing” the battery current. The precharge current can be set higher to account

for the system loading while allowing the battery to be properly conditioned. The PRE-TERM pin is a dual

function pin which sets the precharge current level and the termination threshold level. The termination "current

threshold" is always half of the precharge programmed current level.

Once the battery voltage has charged to the VLOWV threshold, fast charge is initiated and the fast charge

current is applied. The fast charge constant current is programmed using the ISET pin. The constant current

provides the bulk of the charge. Power dissipation in the IC is greatest in fast charge with a lower battery voltage.

If the IC reaches 125°C the IC enters thermal regulation, slow the timer clock by half and reduce the charge

current as needed to keep the temperature from rising any further. Figure 23 shows the charging profile with

thermal regulation. Typically under normal operating conditions, the IC’s junction temperature is less than 125°C

and thermal regulation is not entered.

Once the cell has charged to the regulation voltage the voltage loop takes control and holds the battery at the

regulation voltage until the current tapers to the termination threshold. The charge termination can be disabled if

desired. The CHG pin is low (LED on) during the first charge cycle only and turns off once the charge termination

threshold is reached, regardless if termination is enabled or disabled.

The TS pin monitors the voltage across the pack thermistor and implements the JEITA standard. This allows for

reduced voltage regulation at hot temperatures and reduced charge currents at low temperatures. The TS pin

incorporates a chip disable feature when pulled low and an Termination and Timer Disable Mode (TTDM) feature

when left floating or pulled high.

Further details are mentioned in the Operating Modes section.

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Thermal

Regulation

Phase

Current

Regulation

Phase

Voltage Regulation and

Charge Termination

Phase

Pre-

Conditioning

Phase

DONE

V

O(REG)

I

O(OUT)

Battery Current,

I

FAST-CHARGE

CURRENT

(OUT)

Battery

Voltage,

V

(OUT)

Charge

Complete

Status,

Charger

Off

PRE-CHARGE

CURRENT AND

TERMINATION

THRESHOLD

V

O(LOWV)

I

(TERM)

I

O(PRECHG)

T

(THREG)

0A

Temperature, Tj

T

DONE

(CHG)

T

(PRECHG)

Figure 23. Charging Profile with Thermal Regulation

DETAILED FUNCTIONAL DESCRIPTION

Power-Down, or Undervoltage Lockout (UVLO):

The bq2405x family is in power down mode if the IN pin voltage is less than UVLO. The part is considered

“dead” and all the pins are high impedance. Once the IN voltage rises above the UVLO threshold the IC will

enter Sleep Mode or Active mode depending on the OUT pin (battery) voltage.

Power-up

The IC is alive after the IN voltage ramps above UVLO (see sleep mode), resets all logic and timers, and starts

to perform the D+D– detection along with many of the continuous monitoring routines. The D+/D– detection

typically take less than 100ms, but can take as long as 600ms if there is no activity on the D+ or D– lines which

indicates the device transceiver nor an adaptor is present. Typically the input voltage quickly rises through the

UVLO and sleep states where the IC declares power good, starts the qualification charge at 100mA, finishes the

USB detection routine, sets the input current limit threshold base on the source detected (ISET=adaptor or

100mA=USB), starts the safety timer and enables the CHG pin. See Figure 25

D+/D– Detection:

This detection is designed to give the charger advance notice that an adaptor or USB port is connect for the

cases where the battery is discharged and device transceiver is not able to communicate with a USB host or

there is not a device transceiver. If an adaptor is detected, then the charger can immediately start charging at the

programmed ISET level. Without this early detection, the charger would have to default to the 100mA input

current level to make sure it was not over-loading a low power USB port. The detection method monitors the

D+/D– communication lines looking for a short between the lines (Adaptor source connected) or pull down

resistors on D+/D– (USB source connected) to determine what source is connected (no USB communication

takes place). If an adaptor source is detected then the charger will transition from the 100mA startup level to the

ISET programmed current level. If a USB port is detected, the input current limit will stay at the100mA level. If a

different charge level is desired, than the one detected, the host has to change the state of the ISET2 pin

(signals the internal logic to start using the ISET2 as the program pin) and then set to the desired state.

The D+ and D– pin connections inside the charger are disconnected within 100ms of the D+ or D– lines being

16

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pulled high (start of detection), to minimize any interaction between the charger detection pins and the USB

normal communications. If the device transceiver is able to communicate with the USB host, communication

typically starts after 100ms after the device has pulled the D+ or D– line high indicating it is “on line”, and by then

the IC detection is complete and has been disconnected. The device host then may change the ISET2 level or

disable the IC by pulling the TS pin low.

Sleep Mode

If the IN pin voltage is between than V_OUT+V_DTand UVLO, the charge current is disabled, the safety timer

counting stops (not reset) and the PG and CHG pins are high impedance. As the input voltage rises and the

charger exits sleep mode, the PG pin goes low, the safety timer continues to count, charge is enabled and the

CHG pin returns to its previous state. See Figure 18

New Charge Cycle

A new charge cycle is started when a good power source is applied, performing a chip disable/enable (TS pin),

exiting Termination and Timer Disable Mode (TTDM), detecting a battery insertion or the OUT voltage dropping

below the VRCH threshold. The CHG pin is active low only during the first charge cycle, therefore exiting TTDM

or a dropping below VRCH will not turn on the CHG pin FET, if the CHG pin is already high impedance.

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Figure 24. TS Battery Temperature Bias Threshold and Deglitch Timers

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Apply Input

Power

No

Is Chip Enabled &Alive?

V_TS> V_EN

& V_IN>V_UVLO

Start Running USB

Detection Routine

Yes

Is power good?

No

V_BAT+V_DT< V_IN< V_OVP

& V_UVLO< V_IN

Yes

Turn on PG FET – PG pin LOW

Set Input Current Limit to 100mA

and Start Charge

Perform ISET & OUT short tests

Remember ISET2 State

Yes

No

Has ISET2 changed state since

Detection Routine was run?

Yes

Set charge current

based on ISET2 truth

table.

Set charge current

based Detection

Routine..

Return to

Charge

Figure 25. Power-up Flow Diagram

Overvoltage-Protection (OVP) – Continuously Monitored

If the input source applies an overvoltage, the pass FET, if previously on, turns off after a deglitch, t_BLK(OVP). The

timer ends and the CHG and PG pin goes to a high impedance state. Once the overvoltage returns to a normal

voltage, the PG pin goes low, timer continues, charge continues and the CHG pin goes low after a 25ms

deglitch.. PG pin is optional on some packages.

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Power Good Indication (PG)

After application of a 5V source, the input voltage rises above the UVLO and sleep thresholds (V_IN>V_OUT+V_DT),

but is less than OVP (V_IN<V_OVP), then the PG FET turns on and provides a low impedance path to ground. SEE

Figure 5, Figure 6, and Figure 18.

CHG Pin Indication

The charge pin has an internal open drain FET which is on (pulls down to V_SS) during the first charge only

(independent of TTDM) and is turned off once the battery reaches voltage regulation and the charge current

tapers to the termination threshold set by the PRE-TERM resistor.

The charge pin will be high impedance in sleep mode and OVP (if PG is high impedance) and return to its

previous state once the condition is removed.

Cycling input power, pulling the TS pin low and releasing or entering pre-charge mode will cause the CHG pin to

reset and is considered the start of a first charge.

CHG and PG LED Pull-up Source

For host monitoring, a pull-up resistor is used between the "STATUS" pin and the V_CCof the host and for a visual

indication a resistor in series with an LED is connected between the "STATUS" pin and a power source. If the

CHG or PG source is capable of exceeding 7V, a 6.2V zener should be used to clamp the voltage. If the source

is the OUT pin, note that as the battery changes voltage, the brightness of the LEDs vary.

Charging State

1st Charge

Refresh Charge

OVP

CHG FET/LED

ON

OFF

ON for 1st Charge

PG FET/LED

OFF

SLEEP

TEMP FAULT

V_INPower Good State

UVLO

SLEEP Mode

OVP Mode

Normal Input (V_OUT+ V_DT< V_IN

<

ON

V_OUP

)

PG is independent of chip disable (bq24055, V_TS= 0V)

Input DPM Mode (V_IN-DPM or IN-DPM)

The IN-DPM feature is used to detect an input source voltage that is folding back (voltage dropping), reaching its

current limit due to an excessive load. When the input voltage drops to the V_IN-DPMthreshold the internal pass

FET starts to reduce the current until there is no further drop in voltage at the input. This would prevent a source

with voltage less than V_IN-DPMto power the out pin. This works well with current limited adaptors and USB ports

as long as the nominal voltage is above 4.3V and 4.4V respectively. This is an added safety feature that helps

protect the source from excessive loads.

OUT

The Charger’s OUT pin provides current to the battery and to the system, if present. This IC can be used to

charge the battery plus power the system, charge just the battery or just power the system (TTDM) assuming the

loads do not exceed the available current. The OUT pin is a current limited source and is inherently protected

against shorts. If the system load ever exceeds the output programmed current threshold, the output will be

discharged unless there is sufficient capacitance or a charged battery present to supplement the excessive load.

20

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ISET

An external resistor is used to Program the Output Current (50 to 800mA) and can be used as a current monitor.

R_ISET= K_ISET÷ I_OUT

(0)

Where:

I_OUTis the desired fast charge current;

K_ISETis a gain factor found in the electrical specification

For greater accuracy at lower currents, part of the sense FET is disabled to give better resolution. Figure 19

shows the transition from low current to higher current. Going from higher currents to low currents, there is

hysteresis and the transition occurs around 0.15A.

The ISET resistor is short protected and will detect a resistance lower than 340Ω. The detection requires at

least 80mA of output current. If a “short” is detected, then the IC will latch off and can only be reset by cycling the

power. The OUT current is internally clamped to a maximum current between 1.1A and 1.35A and is independent

of the ISET short detection circuitry, as shown in Figure 27. Also, see Figure 13 and Figure 14.

4.5

For < 45^oC, 4.2V Regulation

No Operation

During Cold

Fault

4

3.5

3

60^oC to 45^oC

HOT TEMP

4.06V

V_OUT

Regulation

2.5

2

< 48^oC

0^oC

60^oC

10^oC

1.5

1

100% of Programmed

Current

50%

0.5

0

Cold

Fault

I_OUT

0.8

0

0.4

1

1.2

1.6

1.8

0.2

0.6

1.4

V_TS- Voltage - V

Figure 26. OPERATION OVER TS BIAS VOLTAGE

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1.8

1.6

1.4

I_OUTInternal Clamp Range

1.2

1

0.8

I_OUTProgrammed

max

0.6

I_SETShort

Fault

0.4

Range

Non Restricted

Operating Area

min

0.2

0

100

1000

10000

I_SET- W

Figure 27. PROGRAMMED / CLAMPED OUT CURRENT

PRE_TERM – Pre-Charge and Termination Programmable Threshold

Pre-Term is used to program both the pre-charge current and the termination current threshold, on the

bq24050/2/5. The pre-charge current level is a factor of two higher than the termination current level. The

termination can be set between 5 and 50% of the programmed output current level set by ISET. If left floating the

termination and pre-charge are set internally at 10/20% respectively. The pre-charge-to-fast-charge, V_lowv

threshold is set to 2.5V.

R_PRE-TERM= %Term × K_TERM= %Pre-CHG × K_PRE-CHG

(0)

Where:

%Term is the percent of fast charge current where termination occurs;

%Pre-CHG is the percent of fast charge current that is desired during precharge;

K_TERMand KPRE-CHG are gain factors found in the electrical specifications.

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ISET2

Is a 3-state input and programs the Input Current Limit/Regulation Threshold. A low will program a regulated fast

charge current via the ISET resistor and is the maximum allowed input/output current for any ISET2 setting, Float

will program a 100mA Current limit and High will program a 500mA Current limit. Note that initially the D+/D–

detection will latch the charge mode according to the source detected (dedicated charger: ISET; USB Host: at

100mA) until the ISET2 pin has changed states, indicating the processor or transceiver is controlling the pin.

The detection routine registers the input level (Low–High-Z–High) of the ISET2 pin ~532 μs after applying input

power (V_IN> 3.4 V – UVLO). After the detection routine is complete, which is ~100 ms after a pull-up on the D+

or D– line or after ~570 ms if no pull-up, the IC monitors the ISET2 pin for a change of state. If the state changes

(Low–High-Z–High) from the one registered, for more than 5 μs, then the "detected" latched charge mode is

released and is then controlled by the ISET2 pin. The completion of the detection routine varies due to the

mechanical-plugging action of the USB cable; therefore, it is best to wait ≥ 600 ms after V_IN> 3.4 V to take

control of the ISET2 pin.

The following illustration shows two configurations for driving the 3-state ISET2 pin:

V

CC

V

CC

R1

R1/R2 Divider

set to 0.9 V

Which is the

Float Voltage

Drive

Logic

To

ISET2

To ISET2

Q1

Q2

Drive

Logic

OR

R2

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TS

The TS pin is designed to follow the new JEITA temperature standard for Li-Ion batteries. There are now four

thresholds, 60°C, 45°C, 10°C, and 0°C. Normal operation occurs between 10°C and 45°C. If between 0°C and

10°C the charge current level is cut in half and if between 45°C and 60°C the regulation voltage is reduced to

4.1Vmax, see Figure 26. The TS feature is implemented using an internal 50μA current source to bias the

thermistor (bq24050/5 designed for use with a 10k NTC β = 3370 (SEMITEC 103AT-2 or Mitsubishi

TH05-3H103F), and bq24052 with a 100k NTC β = 3540 (Mitsubishi TH05-36104F) or equivalent) connected

from the TS pin to V_SS. If this feature is not needed, a fixed 10k can be placed between TS and V_SSto allow

normal operation. This may be done if the host is monitoring the thermistor and then the host would determine

when to pull the TS pin low to disable charge.

The TS pin has two additional features, when the TS pin is pulled low or floated/driven high. A low disables

charge (similar to a CE feature) and a high puts the charger in TTDM.

Above 60°C or below 0°C the charge is disable. Once the thermistor reaches –10°C the TS current folds back

to keep a cold thermistor (between –10°C and –50°C) from placing the IC in the TTDM mode. If the TS pin is

pulled low into disable mode, the current is reduce to 30μA, see Figure 24. Since the I_TScurrent is fixed along

with the temperature thresholds, it is not possible to use thermistor values other than the 10k and 100k.

Termination and Timer Disable Mode (TTDM) -TS pin high

The battery charger is in TTDM when the TS pin goes high from removing the thermistor (removing battery

pack/floating the TS pin) or by pulling the TS pin up to the TTDM threshold.

When entering TTDM, the 10 hour safety timer is held in reset and termination is disabled. A battery detect

routine is run to see if the battery was removed or not. If the battery was removed then the CHG pin will go to its

high impedance state if not already there. If a battery is detected the CHG pin does not change states until the

current tapers to the termination threshold, where the CHG pin goes to its high impedance state if not already

there (the regulated output will remain on).

The charging profile does not change (still has pre-charge, fast-charge constant current and constant voltage

modes). This implies the battery is still charged safely and the current is allowed to taper to zero.

When coming out of TTDM, the battery detect routine is run and if a battery is detected, then a new charge cycle

begins and the CHG LED turns on.

If TTDM is not desired upon removing the battery with the thermistor, one can add a 237k resistor between TS

and V_SSto disable TTDM. This keeps the current source from driving the TS pin into TTDM. This creates 0.1°C

error at hot and a 3°C error at cold.

Timers

The pre-charge timer is set to 30 minutes . The pre-charge current, can be programmed to off-set any system

load, making sure that the 30 minutes is adequate.

The fast charge timer is fixed at 10 hours and can be increased real time by going into thermal regulation,

IN-DPM or if in USB current limit. The timer clock slows by a factor of 2, resulting in a clock than counts half as

fast when in these modes. If either the 30 minute or ten hour timer times out, the charging is terminated and the

CHG pin goes high impedance if not already in that state. The timer is reset by disabling the IC, cycling power or

going into and out of TTDM.

Termination

Once the OUT pin goes above VRCH, (reaches voltage regulation) and the current tapers down to the

termination threshold, the CHG pin goes high impedance and a battery detect route is run to determine if the

battery was removed or the battery is full. If the battery is present the charge current will terminate. If the battery

was removed along with the thermistor, then the TS pin will be driven high and the charge will enter TTDM. If the

battery was removed and the TS pin is held in the active region, then the battery detect routine will continue until

a battery is inserted.

24

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Battery Detect Routine

The battery detect routine should check for a missing battery while keeping the OUT pin at a useable voltage.

Whenever the battery is missing the CHG pin should be high impedance.

The battery detect routine is run when entering and exiting TTDM to verify if battery is present, or run all the time

if battery is missing and not in TTDM. On power-up, if battery voltage is greater than V_RCHthreshold, a battery

detect routine is run to determine if a battery is present.

The battery detect routine will be disabled while the IC is in TTDM or has a TS fault. See Figure 28 for the

Battery Detect Flow Diagram.

Refresh Threshold

After termination, if the OUT pin voltage drops to VRCH (100mV below regulation) then a new charge is initiated,

but the CHG pin remains at a high impedance (off).

Starting a Charge on a Full Battery

The termination threshold is raised by 14%, for the first minute of a charge cycle so if a full battery is removed

and reinserted or a new charge cycle is initiated, that the new charge terminates (less than 1 minute). Batteries

that have relaxed many hours may take several minutes to taper to the termination threshold and terminate

charge.

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Start

BATT_DETECT

Start 25ms timer

No

Timer Expired?

Yes

Battery Present

Yes

Is VOUT<VREG-100mV?

Turn off Sink Current

Return to flow

No

Set OUT REG

to VREG-400mV

Enable sink current

Reset & Start 25ms timer

No

Timer Expired?

Yes

Battery Present

Turn off Sink Current

Return to flow

Is VOUT>VREG-300mV?

No

Battery Absent

Don’t Signal Charge

Turn off Sink Current

Return to Flow

Figure 28. Battery Detect Flow Diagram

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bq2405x CHARGER APPLICATION DESIGN EXAMPLE

bq24050/2

Adaptor

1

2

3

4

5

10

9

System Load

IN

DC+

GND

OUT

TS

Battery Pack

+

1.5kW

ISET

VSS

8

CHG

ISET2

D-

1kW

1mF

7

PRETERM

D+

OR

6

VDD

2kW

TTDM

USB Port

ISET/100/500mA

VBUS

GND

D+

D-

Host

D-

Disconnect after Detection

Requirements

•

Supply voltage = 5 V

Fast charge current: I_OUT-FC= 540 mA; ISET-pin 2

Termination Current Threshold: %_IOUT-FC= 10% of Fast Charge or 54mA

Pre-Charge Current by default is twice the termination Current or 108mA

TS – Battery Temperature Sense = 10k NTC (103AT)

Calculations

Program the Fast Charge Current, ISET:

R_ISET= [K_(ISET)/ I_(OUT)

]

from electrical characteristics table. . . K_(SET)= 540AΩ

R_ISET= [540AΩ/0.54A] = 1.0 kΩ

Selecting the closest standard value, use a 1kΩ resistor between ISET (pin 16) and V_SS

.

Program the Termination Current Threshold, ITERM:

R_PRE-TERM= K_(TERM)× %_IOUT-FC

R_PRE-TERM= 200Ω/% × 10% = 2kΩ

Selecting the closest standard value, use a 2kΩ resistor between ITERM (pin 15) and Vss.

One can arrive at the same value by using 20% for a pre-charge value (factor of 2 difference).

R_PRE-TERM= K_(PRE-CHG)× %_IOUT-FC

R_PRE-TERM= 100Ω/% × 20%= 2kΩ

TS Function

Use a 10k NTC thermistor in the battery pack (103AT).

To Disable the temp sense function, use a fixed 10k resistor between the TS (Pin 1) and V_SS

.

CHG and PG

LED Status: connect a 1.5k resistor in series with a LED between the OUT pin and the CHG pin. Connect a 1.5k

resistor in series with a LED between the OUT pin and the and PG pin.

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Processor Monitoring: Connect a pull-up resistor between the processor’s power rail and the CHG pin.

Connect a pull-up resistor between the processor’s power rail and the PG pin.

SELECTING IN AND OUT PIN CAPACITORS

In most applications, all that is needed is a high-frequency decoupling capacitor (ceramic) on the power pin, input

and output pins. Using the values shown on the application diagram, is recommended. After evaluation of these

voltage signals with real system operational conditions, one can determine if capacitance values can be adjusted

toward the minimum recommended values (DC load application) or higher values for fast high amplitude pulsed

load applications. Note if designed for high input voltage sources (bad adaptors or wrong adaptors), the capacitor

needs to be rated appropriately. Ceramic capacitors are tested to 2x their rated values so a 16V capacitor may

be adequate for a 30V transient (verify tested rating with capacitor manufacturer).

THERMAL PACKAGE

The bq2405x family is packaged in a thermally enhanced MLP package. The package includes a thermal pad to

provide an effective thermal contact between the IC and the printed circuit board (PCB). The power pad should

be directly connected to the VSS pin. Full PCB design guidelines for this package are provided in the QFN/SON

PCB Attachment Application Note application note (SLUA271). The most common measure of package thermal

performance is thermal impedance (θ_JA) measured (or modeled) from the chip junction to the air surrounding the

package surface (ambient). The mathematical expression for θ_JAis:

θ_JA= (T_J– T) / P

(0)

Where:

T_J= chip junction temperature

T = ambient temperature

P = device power dissipation

Factors that can influence the measurement and calculation of θ_JAinclude:

1. Whether or not the device is board mounted

2. Trace size, composition, thickness, and geometry

3. Orientation of the device (horizontal or vertical)

4. Volume of the ambient air surrounding the device under test and airflow

5. Whether other surfaces are in close proximity to the device being tested

Due to the charge profile of Li-Ion batteries the maximum power dissipation is typically seen at the beginning of

the charge cycle when the battery voltage is at its lowest. Typically after fast charge begins the pack voltage

increases to 3.4V within the first 2 minutes. The thermal time constant of the assembly typically takes a few

minutes to heat up so when doing maximum power dissipation calculations, 3.4V is a good minimum voltage to

use. This is verified, with the system and a fully discharged battery, by plotting temperature on the bottom of the

PCB under the IC (pad should have multiple vias), the charge current and the battery voltage as a function of

time. The fast charge current will start to taper off if the part goes into thermal regulation.

The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal

PowerFET. It can be calculated from the following equation when a battery pack is being charged :

P = [V_(IN)– V_(OUT)] × I_(OUT)+ [V_(OUT)– V_(OUT)] × I_(OUT)

(0)

The thermal loop feature reduces the charge current to limit excessive IC junction temperature. It is

recommended that the design not run in thermal regulation for typical operating conditions (nominal input voltage

and nominal ambient temperatures) and use the feature for non typical situations such as hot environments or

higher than normal input source voltage. With that said, the IC will still perform as described, if the thermal loop

is always active.

Leakage Current Effects on Battery Capacity

To determine how fast a leakage current on the battery discharges, the battery is used for the calculation. The

time from full to discharge can be calculated by dividing the Amp-Hour Capacity of the battery by the leakage

current. For a 0.75AHr battery and a 10μA leakage current (750mAHr/0.010mA = 75000 Hours), it would take

75k hours or 8.8 years to discharge. In reality, the self discharge of the cell is much faster, so the 10μA leakage

would be considered negligible.

28

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Layout Tips

To obtain optimal performance, the decoupling capacitor from IN to GND (thermal pad) and the output filter

capacitors from OUT to GND (thermal pad) should be placed as close as possible to the bq2405x, with short

trace runs to both IN, OUT and GND (thermal pad).

•

All low-current GND connections should be kept separate from the high-current charge or discharge paths

from the battery. Use a single-point ground technique incorporating both the small signal ground path and the

power ground path.

•

The high current charge paths into IN pin and from the OUT pin must be sized appropriately for the maximum

charge current in order to avoid voltage drops in these traces

The bq2405x family is packaged in a thermally enhanced MLP package. The package includes a thermal pad

to provide an effective thermal contact between the IC and the printed circuit board (PCB); this thermal pad is

also the main ground connection for the device. Connect the thermal pad to the PCB ground connection. It is

best to use multiple 10-mill vias in the power pad of the IC and in close proximity to conduct the heat to the

bottom ground plane. The bottom ground place should avoid traces that “cut off” the thermal path. The thinner

the PCB the less temperature rise. The EVM PCB has a thickness of 0.031 inches and uses 2 oz. (2.8-mill

thick) copper on top and bottom, and is a good example of optimal thermal performance.

SPACER

REVISION HISTORY

Changes from Original (August 2009) to Revision A ..................................................................................................... Page

Changed the status of the devices From: Product Preview To: Prodcution Data ................................................................ 1

•

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PACKAGE OPTION ADDENDUM

www.ti.com

15-Sep-2009

PACKAGING INFORMATION

Orderable Device

BQ24050DSQR

BQ24050DSQT

BQ24052DSQR

BQ24052DSQT

BQ24055DSSR

BQ24055DSST

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SON

DSQ

10

12

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SON

DSQ

DSS

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Sep-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ24050DSQR

BQ24050DSQT

BQ24052DSQR

BQ24052DSQT

BQ24055DSSR

BQ24055DSST

SON

DSQ

DSS

10

12

3000

250

179.0

8.4

2.2

2.3

2.2

3.2

1.2

1.0

4.0

8.0

Q2

Q1

3000

250

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Sep-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ24050DSQR

BQ24050DSQT

BQ24052DSQR

BQ24052DSQT

BQ24055DSSR

BQ24055DSST

SON

DSQ

DSS

10

12

3000

250

195.0

200.0

45.0

3000

250

3000

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IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Military

Optical Networking

Security

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

www.ti.com/audio

Data Converters

DLP® Products

DSP

Clocks and Timers

Interface

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/medical

www.ti.com/military

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Logic

Power Mgmt

Microcontrollers

RFID

Telephony

Video & Imaging

Wireless

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

型号:	BQ24050DSQR
Brand Name：	Texas Instruments
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	SON
包装说明：	HVSON, SOLCC10,.08,16
针数：	10
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
Factory Lead Time：	6 weeks
风险等级：	0.78
可调阈值：	YES
模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	S-PDSO-N10
JESD-609代码：	e4
长度：	2 mm
湿度敏感等级：	2
信道数量：	1
功能数量：	1
端子数量：	10
封装主体材料：	PLASTIC/EPOXY
封装代码：	HVSON
封装等效代码：	SOLCC10,.08,16
封装形状：	SQUARE
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260
电源：	3.5/28 V
认证状态：	Not Qualified
座面最大高度：	0.75 mm
子类别：	Power Management Circuits
最大供电电流 (Isup)：	1 mA
最大供电电压 (Vsup)：	28 V
最小供电电压 (Vsup)：	3.5 V
标称供电电压 (Vsup)：	5 V
表面贴装：	YES
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	NO LEAD
端子节距：	0.4 mm
端子位置：	DUAL
阈值电压标称：	6.65
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	2 mm
Base Number Matches：	1

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