BQ24071RHLRG4中文资料应用文章市场行情现货热卖使用介绍-中国IC网-芯三七

bq24070

bq24071

www.ti.com

SLUS694F –MARCH 2006–REVISED DECEMBER 2009

SINGLE-CHIP LI-ION CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC

Check for Samples: bq24070, bq24071

1

FEATURES

DESCRIPTION

•

Small 3,5 mm × 4,5 mm QFN Package

•

Designed for Single-Cell Li-Ion- or

Li-Polymer-Based Portable Applications

The bq24070 and bq24071 are highly integrated

Li-ion linear charger and system power-path

management devices targeted at space-limited

portable applications. The bq24070/1 offer DC supply

(AC adapter) power-path management with

autonomous power-source selection, power FETs

and current sensors, high-accuracy current and

voltage regulation, charge status, and charge

termination, in a single monolithic device.

•

Integrated Dynamic Power-Path Management

(DPPM) Feature Allowing the AC Adapter to

Simultaneously Power the System and Charge

the Battery

•

Power Supplement Mode Allows Battery to

Supplement the AC Input Current

Autonomous Power Source Selection (AC

Adapter or BAT)

The

bq24070/1

power

the

system

while

independently charging the battery. This feature

reduces the charge and discharge cycles on the

battery, allows for proper charge termination and

allows the system to run with an absent or defective

battery pack. This feature also allows for the system

to instantaneously turn on from an external power

source in the case of a deeply discharged battery

pack. The IC design is focused on supplying

continuous power to the system when available from

the AC adapter or battery sources.

•

Supports Up to 2 Amps Total Current

Thermal Regulation for Charge Control

Charge Status Outputs for LED or System

Interface Indicates Charge and Fault

Conditions

•

Reverse Current, Short-Circuit, and Thermal

Protection

•

Power Good Status Outputs

4.4-V and 6-V Options for System Output

Regulation Voltage

APPLICATIONS

•

Smart Phones and PDA

MP3 Players

Digital Cameras and Handheld Devices

Internet Appliances

POWER FLOW DIAGRAM

AC Adapter

VDC

(2)

IN

OUT

System

GND

Q1

PACK+

BAT

40 mΩ

+

PACK−

Q2

bq24070/1

UDG−04082

(1) See Figure 2 and functional block diagram for more detailed feature information.

(2) P-FET back gate body diodes are disconnected to prevent body diode conduction.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

bq24070

bq24071

SLUS694F –MARCH 2006–REVISED DECEMBER 2009

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION (CONTINUED)

The MODE pin selects the priority of the input sources. If an input source is not available, then the battery is

selected as the source. With the MODE pin high, the bq24070/1 attempts to charge from the input at the charge

rate set by ISET1 pin. With the MODE pin low, the bq24070/1 defaults to USB charging at the charge rate. This

feature allows the use of a single connector (mini-USB cable), where the host programs the MODE pin according

to the source that is connected (AC adaptor or USB port). Table 1 summarizes the MODE pin function.

Table 1. Power Source Selection Function Summary

MODE STATE

AC

ADAPTER

MAXIMUM

SYSTEM

POWER

SOURCE

USB BOOT-UP

FEATURE

CHARGE RATE⁽¹⁾

Low

Present

Absent

Present

Absent

ISET2

N/A

USB

Battery

AC

Enabled

Disabled

High

ISET1

N/A

Battery

(1) Battery charge rate is always set by ISET1, but may be reduced by a limited input source (ISET2 USB mode) and I_OUTsystem load.

ORDERING INFORMATION⁽¹⁾

BATTERY

VOLTAGE (V)

PART

PACKAGE

MARKING

T_A

OUT PIN

STATUS

NUMBER^{(2) (3)}

4.2

Regulated to 4.4 V⁽⁴⁾

Regulated to 6 V

bq24070RHLR

bq24070RHLT

bq24071RHLR

bq24071RHLT

Production

BRQ

BTR

–40°C to 125°C

Regulated to 6 V

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) The RHL package is available in the following options:

R - taped and reeled in quantities of 3,000 devices per reel.

T - taped and reeled in quantities of 250 devices per reel.

(3) This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for

use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including

bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(4) If AC < V_O(OUT-REG), the AC is connected to the OUT pin by a P-FET, (Q1).

2

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SLUS694F –MARCH 2006–REVISED DECEMBER 2009

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

bq24070/1

Input voltage

IN (DC voltage with respect to VSS)

–0.3 V to 18 V

BAT, CE, DPPM, PG, Mode, OUT, ISET1, ISET2, STAT1,

STAT2, TS, (all DC voltages wrt VSS)

–0.3 V to 7 V

V_REF(DC voltage wrt VSS)

TMR

–0.3 V to V_O(OUT)+ 0.3 V

–0.3 V to V_O+ 0.3 V

3.5 A

Input current

OUT

BAT⁽²⁾

4 A

Output current

–4 A to 3.5 A

Output source current (in

V_REF

30 mA

regulation at 3.3 V V_REF

)

Output sink current

PG, STAT1, STAT2,

15 mA

–65°C to 150°C

–40°C to 150°C

300°C

Storage temperature range, T_stg

Junction temperature range, T_J

Lead temperature (soldering, 10 seconds)

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage

values are with respect to the network ground terminal unless otherwise noted.

(2) Negative current is defined as current flowing into the BAT pin.

RECOMMENDED OPERATING CONDITIONS

MIN

MAX UNIT

(1)

V_CCSupply voltage (V_IN

)

4.35

16

2

V

A

I_AC

T_J

Input current

Operating junction temperature range

–40

125

°C

(1) Verify that power dissipation and junction temperatures are within limits at maximum V_CC

.

DISSIPATION RATINGS

T

_A≤ 40°C

DERATING FACTOR

PACKAGE

θ_JA

46.87 °C/W

POWER RATING

T_A> 40°C

20-pin RHL⁽¹⁾

1.81 W

21 mW/°C

(1) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is

connected to the ground plane by a 2×3 via matrix.

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SLUS694F –MARCH 2006–REVISED DECEMBER 2009

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ELECTRICAL CHARACTERISTICS

over junction temperature range (0°C ≤ T_J≤ 125°C) and the recommended supply voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT BIAS CURRENTS

I_CC(SPLY)

I_CC(SLP)

Active supply current, VCC

V_VCC> V_VCC(min)

1

2

5

mA

V_IN< V_(BAT)

2.6 V ≤ V_I(BAT)≤ V_O(BAT-REG)

Excludes load on OUT pin

Sleep current (current into BAT

pin)

,

V_I(AC)≤ 6V, Total current into IN pin with

I_CC(IN-STDBY)

Input standby current

chip disabled, Excludes all loads, CE=LOW,

after t_(CE-HOLDOFF)delay

200

μA

Total current into BAT pin with input present

and chip disabled;

I_{CC(BAT-STDBY)}

BAT standby current

Excludes all loads, CE=LOW,

after t_(CE-HOLDOFF)delay,

45

1

65

5

0°C ≤ T_J≤ 85°C⁽¹⁾

I_IB(BAT)

Charge done current, BAT

Charge DONE, input supplying the load

OUT PIN-VOLTAGE REGULATION

bq24070

bq24071

V

_I(AC)≥ 4.4 V + V_DO

_I(AC)≥ 6 V + V_DO

4.4

6.0

4.5

6.3

Output regulation

voltage

V_O(OUT-REG)

V

OUT PIN – DPPM REGULATION

V_(DPPM-SET)

I_(DPPM-SET)

SF

DPPM set point⁽²⁾

DPPM current source

DPPM scale factor

V_DPPM-SET< V_OUT

2.6

95

3.8

105

V

Input present

100

μA

V_(DPPM-REG)= V_(DPPM-SET)× SF

1.139

1.150

1.162

OUT PIN – FET (Q1, Q2) DROP-OUT VOLTAGE R_DS(on)

)

V

_I(AC)≥ V_CC(min), Mode = High,

V_(ACDO)

AC to OUT dropout voltage⁽³⁾

300

40

475

100

I_I(AC)= 1 A, (I_O(OUT)+ I_O(BAT)), or no input

mV

BAT to OUT dropout voltage

(discharging)

V_(BATDO)

V_{I (BAT)}≥ 3 V, I_I(BAT)= 1.0 A, V_CC< V_I(BAT)

OUT PIN - BATTERY SUPPLEMENT MODE

Enter battery supplement mode

(battery supplements OUT current V_I(BAT)> 2 V

in the presence of input source

V_I(OUT)

≤ V_I(BAT)

– 60 mV

V_BSUP1

V

V_I(OUT)

≥ V_I(BAT)

– 20 mV

V_BSUP2

Exit battery supplement mode

V_I(BAT)> 2 V

OUT PIN - SHORT CIRCUIT

Current source between BAT to OUT for

I_OSH1

BAT to OUT short-circuit recovery short-circuit recovery to

_I(OUT)≤ V_I(BAT)–200 mV

10

mA

V

R_SHAC

AC to OUT short-circuit limit

V_I(OUT)≤ 1 V

500

Ω

BAT PIN CHARGING – PRECHARGE

Precharge to fast-charge transition

threshold

V_(LOWV)

T_DGL(F)

I_O(PRECHG)

V_(PRECHG)

Voltage on BAT

2.9

3

3.1

V

De-glitch time for fast-charge to

precharge transition⁽⁴⁾

t_FALL= 100 ns, 10 mV overdrive,

V_I(BAT)decreasing below threshold

22.5

ms

1 V < V_I(BAT)< V_(LOWV), t < t_(PRECHG)

I_O(PRECHG)= (K_(SET)× V_(PRECHG))/ R_SET

,

Precharge range

10

150

275

mA

mV

Precharge set voltage

1 V < V_I(BAT)< V_(LOWV), t < t_(PRECHG)

225

250

BAT PIN CHARGING - CURRENT REGULATION

V_{I (BAT)}> V_(LOWV), Mode = High

I_OUT(BAT)= (K_(SET)× V_(SET)/ R_SET),

V_I(OUT) > V_O(OUT-REG) + V_(DO-MAX)

(5)

I_O(BAT)

R_PBAT

Battery charge current range

BAT to OUT pullup

100

1000

1500

mA

V_{I (BAT)}< 1 V

Ω

(1) This includes the quiescent current for the integrated LDO.

(2) V_(DPPM-SET)is scaled up by the scale factor for controlling the output voltage V_(DPPM-REG)

.

(3) V_DO(max), dropout voltage is a function of the FET, R_DS(on), and drain current. The dropout voltage increases proportionally to the

increase in current.

(4) All de-glitch periods are a function of the timer setting and is modified in DPPM or thermal regulation modes by the percentages that the

program current is reduced.

(5) When input current remains below 2 A, the battery charging current may be raised until the thermal regulation limits the charge current.

4

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SLUS694F –MARCH 2006–REVISED DECEMBER 2009

ELECTRICAL CHARACTERISTICS (continued)

over junction temperature range (0°C ≤ T_J≤ 125°C) and the recommended supply voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Voltage on ISET1, V_VCC≥ 4.35 V,

Battery charge current set

voltage⁽⁶⁾

V_(SET)

V_I(OUT)- V_I(BAT)> V_(DO-MAX)

,

2.47

2.50

2.53

V

V_I(BAT)> V_(LOWV)

100 mA ≤ I_O(BAT)≤ 1.5 A

10 mA ≤ I_O(BAT)≤ 100 mA⁽⁷⁾

375

300

425

450

600

K_(SET)

Charge current set factor, BAT

USB MODE INPUT CURRENT LIMIT

I_(USB)USB input port current range

ISET2 = Low

ISET2 = High

80

90

100

500

mA

V

400

BAT PIN CHARGING VOLTAGE REGULATION, V_{O (BAT-REG)}+ V _(DO-MAX)< V_CC, I_TERM< I_BAT(OUT)≤ 1 A

Battery charge voltage

4.2

V_O(BAT-REG)

T_A= 25°C

–0.5%

–1%

0.5%

1%

Battery charge voltage regulation

accuracy

CHARGE TERMINATION DETECTION

Charge termination detection

range

V_I(BAT)> V_(RCH),

I_(TERM)

10

150

mA

mV

I_(TERM)= (K_(SET)× V_(TERM))/ R_SET

V_I(BAT)> V_(RCH), Mode = High

V_I(BAT)> V_(RCH), Mode = Low

230

95

250

100

270

130

Charge termination set voltage,

measured on ISET1

V_(TERM)

t_FALL= 100 ns, 10 mV overdrive,

I_CHGincreasing above or decreasing below

threshold

De-glitch time for termination

detection

T_DGL(TERM)

22.5

ms

TEMPERATURE SENSE COMPARATORS

V_LTF

V_HTF

I_TS

High voltage threshold

Temp fault at V(TS) > V_LTF

Temp fault at V(TS) < V_HTF

2.465

0.485

94

2.500

0.500

100

2.535

0.515

106

V

Low voltage threshold

Temperature sense current source

μA

R_(TMR)= 50 kΩ, V_I(BAT)increasing or

decreasing above and below;

100-ns fall time, 10-mv overdrive

De-glitch time for temperature fault

detection⁽⁸⁾

T_DGL(TF)

22.5

ms

BATTERY RECHARGE THRESHOLD

V_O(BAT-

REG)

–0.075

V_O(BAT-REG)

–0.100

V_O(BAT-REG)

–0.125

V_RCH

Recharge threshold voltage

V

R_(TMR)= 50 kΩ, V_I(BAT)increasing

or decreasing below threshold,

100-ns fall time, 10-mv overdrive

De-glitch time for recharge

detection⁽⁸⁾

T_DGL(RCH)

22.5

ms

STAT1, STAT2, AND PG, OPEN DRAIN (OD) OUTPUTS⁽⁹⁾

I_OL= 5 mA, An external pullup

resistor ≥ 1 K required.

V_OL

Low-level output saturation voltage

Input leakage current

0.25

5

V

I_LKG

1

μA

ISET2, CE INPUTS

V_IL

Low-level input voltage

0

1.4

–1

0.4

1

V

V_IH

High-level input voltage

Low-level input current, CE

High-level input current, CE

Low-level input current, ISET2

High-level input current, ISET2

Holdoff time, CE

I_IL

I_IH

μA

I_IL

V_ISET2= 0.4 V

V_ISET2= V_CC

–20

3.3

I_IH

40

t_(CE-HLDOFF)

CE going low only

6.2

ms

(6) For half-charge rate, V_(SET)is 1.25 V ± 25 mV.

(7) Specification is for monitoring charge current via the ISET1 pin during voltage regulation mode, not for a reduced fast-charge level.

(8) All de-glitch periods are a function of the timer setting and is modified in DPPM or thermal regulation modes by the percentages that the

program current is reduced.

(9) See Charger Sleep mode for PG (V_CC= V_IN) specifications.

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SLUS694F –MARCH 2006–REVISED DECEMBER 2009

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ELECTRICAL CHARACTERISTICS (continued)

over junction temperature range (0°C ≤ T_J≤ 125°C) and the recommended supply voltage range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MODE INPUT

Falling Hi→Low; 280 K ± 10% applied when

low.

V_IL

Low-level input voltage

0.975

1

1.025

V

V_IH

High-level input voltage

Input R_Modesets external hysteresis

V_IL+ .01

–1

V_IL+ .024

V

I_IL

Low-level input current, Mode

μA

TIMERS

K_(TMR)

Timer set factor

t_(CHG)= K_(TMR)× R_(TMR)

0.313

30

0.360

0.414

100

s/Ω

kΩ

(10)

R_(TMR)

External resistor limits

0.09 ×

t_(CHG)

t_(PRECHG)

I_(FAULT)

Precharge timer

0.10 × t_(CHG)0.11 × t_(CHG)

1

s

Timer fault recovery pullup from

OUT to BAT

kΩ

CHARGER SLEEP THRESHOLDS (PG THRESHOLDS, LOW → POWER GOOD)

V_VCC

V_I(BAT)

+125 mV

≤

V

_(UVLO)≤ V_I(BAT)≤ V_O(BAT-REG)

,

(11)

V_(SLPENT)

V_(SLPEXIT)

t_(DEGL)

Sleep-mode entry threshold

Sleep-mode exit threshold

De-glitch time for sleep mode⁽¹²⁾

No t_(BOOT-UP)delay

V

V_VCC

V_I(BAT)

+190 mV

≥

V_(UVLO)≤ V_I(BAT)≤ V_O(BAT-REG)

(11)

No t_(BOOT-UP)delay

R_(TMR)= 50 kΩ,

V_(IN)decreasing below threshold, 100-ns fall

time, 10-mv overdrive

22.5

150

ms

START-UP CONTROL BOOT-UP

t_(BOOT-UP)Boot-up time

SWITCHING POWER SOURCE TIMING

On the first application of input with Mode

Low

120

180

50

When input applied. Measure from:

Switching power source from input [PG: Lo → Hi to I_(IN)> 5 mA],

t_SW-BAT

μs

to battery

I_(OUT)= 100 mA,

R_TRM= 50 K

THERMAL SHUTDOWN REGULATION⁽¹³⁾

T_(SHTDWN)

Temperature trip

T_J(Q1 and Q3 only)

T_J(Q2)

155

30

Thermal hysteresis

°C

T_J(REG)

UVLO

V_(UVLO)

Temperature regulation limit

115

135

Undervoltage lockout

Hysteresis

Decreasing V_CC

2.45

2.50

27

2.65

V

mV

V_REFOUTPUT

Active only if AC or USB is present,

V_O(VREF)

Output regulation voltage

3.3

V

V_I(OUT)≥ V_O(VREF)+ (I_O(VREF)× R_DS(on))

Regulation accuracy⁽¹⁴⁾

Output current

–5%

5%

20

50

1

I_O(VREF)

R_DS(on)

mA

Ω

On resistance

OUT to V_REF

(15)

C_(OUT)

Output capacitance

μF

(10) To disable the fast-charge safety timer and charge termination, tie TMR to the V_REFpin. Tying the TMR pin high changes the timing

resistor from the external value to an internal 50 kΩ ±25%, which can add an additional tolerance to any timed specification. The TMR

pin normally regulates to 2.5 V when the charge current is not restricted by the DPPM or thermal feedback loops. If these loops become

active, the TMR pin voltage will be reduced proportionally to the reduction in charge current and the clock frequency will be reduced by

the same percentage (timed durations will count down slower, extending their time). The TMR pin is clamped at 0.80 V, for a maximum

time extension of 2.5 V ÷ 0.8 V × 100 = 310%.

(11) The IC is considered in sleep mode when IN is absent (PG = OPEN DRAIN).

(12) Does not declare sleep mode until after the de-glitch time and implement the needed power transfer immediately according to the

switching specification.

(13) Reaching thermal regulation reduces the charging current. Battery supplement current is not restricted by either thermal regulation or

shutdown. Input power FETs turn off during thermal shutdown. The battery FET is only protected by a short-circuit limit which typically

does not cause a thermal shutdown (input FETs turning off) by itself.

(14) In standby mode (CE low) the accuracy is ±10%.

(15) V_REFoutput capacitor not required, but one with a value of 0.1 μF is recommended.

6

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SLUS694F –MARCH 2006–REVISED DECEMBER 2009

DEVICE INFORMATION

bq24070/1RHL

RHL PACKAGE

(TOP VIEW)

GND

STAT1

STAT2

IN

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

1

20

PG

OUT

TMR

DPPM

TS

BAT

ISET2

MODE

CE

10

11

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

IN

NO.

4

I

Charge input voltage

PG

18

5, 6

9

O

Power-good status output (open-drain)

BAT

CE

I/O Battery input and output.

I

Chip enable input (active high)

Dynamic power-path management set point (account for scale factor)

DPPM

ISET1

13

10

I/O Charge current set point and precharge and termination set point

Charge current set point for USB port. (High = 500 mA, Low = 100 mA) See half-charge current mode

using ISET2.

ISET2

7

I

OUT

15, 16, 17

O

I

Output terminal to the system

MODE

STAT1

STAT2

8

2

3

Power source selection input (Low for USB mode current limit)

Charge status output 1 (open-drain)

O

Charge status output 2 (open-drain)

Timer program input programmed by resistor. Disable fast-charge safety timer and termination by tying

TMR

14

I/O

TMR to V_REF

.

TS

12

19, 20

1

I/O Temperature sense input

GND

VREF

I

Ground input

O

Internal reference signal

Ground input (the thermal pad on the underside of the package) There is an internal electrical connection

between the exposed thermal pad and VSS pin of the device. The exposed thermal pad must be

connected to the same potential as the VSS pin on the printed-circuit board. Do not use the thermal pad as

the primary ground input for the device. VSS pin must be connected to ground at all times.

VSS

11

–

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FUNCTIONAL BLOCK DIAGRAM

Short−Circuit Recovery

500

Ω

BAT

Short−Circuit

Recovery

V

O(OUT)

OUT

100 mA /

Q1

IN

500 mA

V

1 k

Fault

Recovery

Ω

3.3 V

REF

10 mA

V

SET

+

I

(SNS)

V

IO(AC)

Charge

Enable

V

I(BAT)

AC

Q2

V

I (SNS)

+

BAT

V

O(OUT)

O(OUT−REG)

GND

V

I(ISET1)

ISET1

UVLO

V

O(BAT−REG)

TMR

Oscillator

V

I(BAT)

+

V

(BAT)

I

V

O(BAT−REG)

V

I(ISET1)

+

BAT

V

O(OUT)

Fast Precharge

Charge

Enable

DPPM

V

DPPM

SET

I

(DPPM)

Scaling

+

V

+

DPPM

60 mV

Disable−

Sleep

+

V

T

J

I(BAT)

+

1 V

V

T

O(OUT)

(HTF)

J(REG)

*

200 mV

I

(TS)

Suspend

Thermal

Shutdown

TS

1 V

*

V

(LTF)

280 k

Ω

Power Source Selection

MODE

CE

AC Charge Enable

BAT Charge Enable

500 mA/ 100 mA

V

O(BAT−REG)

Charge

Control

Timer

and

Display

Logic

Fast Precharge

Recharge

Precharge

V

BAT

*

1C − 500 mA

C/S − 100 mA

ISET2

V

BAT

*

PG

V

(SET)

V

GND

Term

I(ISET1)

*

STAT1

STAT2

Sleep

V

BAT

*

V

IN

VSS

*

Signal Deglitched

UDG−04084

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FUNCTIONAL DESCRIPTIONS

SIGMA

4.44

V_OUT, V_AC= 5.5 V

I_I= 100 A

+3 Sigma

4.42

4.4

Mean

4.38

4.36

4.34

4.32

-3 Sigma

-60

-40

-20

0

20

40

60

80

100

120

140

T - Temperatures - ^oC

Figure 1. Typical OUT Voltage Regulation, bq24070

CHARGE CONTROL

The bq24070/1 supports a precision Li-ion or Li-polymer charging system suitable for single-cell portable devices.

See a typical charge profile, application circuit, and an operational flow chart in Figure 2 through Figure 4,

respectively.

Pre-Conditioning

Phase

Current Regulation Phase

Voltage Regulation and Charge Termination Phase

Regulation

Voltage

Regulation

Current

Charge

Voltage

Minimum

Charge

Complete

Voltage

Charge

Current

Pre−

Conditioning

and Term

Detect

UDG−04087

Figure 2. Charge Profile

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bq24070/1

AC Adapter

VDC

GND

4

IN

1

V

REF

OUT 15

OUT 16

OUT 17

10 µF

System

10 µF

20 GND

14 TMR

Battery P ack

PACK+

BAT

5

6

+

1 µF

PACK−

R

TMR

7

ISET2

2

STAT1

STAT2

GND

PG

3

19

18

9

TEMP

TS 12

13

DPPM

R

SET

ISET1 10

VSS 11

R

DPPM

CE

8

MODE

Control and

Status Signals

UDG−04083

Figure 3. Typical Application Circuit

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POR

SLEEP MODE

Vcc > V

I(BAT)

checked at all

times?

Indicate SLEEP

MODE

No

Yes

Regulate

I

O(PRECHG)

Reset and Start

timer

V

< V

(LOWV)

I(BAT)

t

Yes

Indicate Charge−

In−Progress

(PRECHG)

?

No

Reset all timers,

Start t timer

(CHG)

Regulate Current

or Voltage

Indicate Charge−

In−Progress

No

V

<V

(LOWV)

I(BAT)

Yes

No

t

(PRECHG)

Expired?

t

(CHG)

Expired?

Yes

No

Yes

Fault Condition

Indicate Fault

Yes

V

<V

(LOWV)

I(BAT)

?

No

V

> V

(RCH)

I(BAT)

?

I

(TERM)

No

detection?

No

Enable I

(F AUL T)

current

Yes

No

Yes

V

> V

?

I(BAT)

(RCH)

T urn off charge

Indicate DONE

Yes

Disable I

(F AUL T)

current

No

V

< V

?

I(BAT)

(RCH)

Figure 4. Charge Control Operational Flow Chart

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Autonomous Power Source Selection, Mode Control Pin

With the MODE input low, the bq24070/1 defaults to USB-mode charging, and the supply current is limited by the

ISET2 pin (100 mA for ISET2 = Low, 500 mA for ISET2 = High). If an input source is not available, then the

battery is selected as the source.

Boot-Up Sequence

In order to facilitate the system start-up and USB enumeration, the bq24070/1 offers a proprietary boot-up

sequence. On the first application of power to the bq24070/1, this feature enables the 100-mA USB charge rate

for a period of approximately 150 ms, (t_(BOOT-UP)), ignoring the ISET2 and CE inputs setting. At the end of this

period, the bq24070/1 implement CE and ISET2 input settings. Table 1 indicates when this feature is enabled.

See Figure 9.

Power-Path Management

The bq24070/1 powers the system while independently charging the battery. This feature reduces the charge

and discharge cycles on the battery, allows for proper charge termination, and allows the system to run with an

absent or defective battery pack. This feature gives the system priority on input power, allowing the system to

power up with a deeply discharged battery pack. This feature works as follows:

AC Adapter

(2)

IN

OUT

VDC

GND

System

Q1

PACK+

PACK−

BAT

40 mΩ

+

Q2

bq24070/1

UDG−04082

Figure 5. Power-Path Management

Case 1: AC Mode (Mode = High)

System Power

In this case, the system load is powered directly from the AC adapter through the internal transistor Q1 (see

Figure 5). The output is regulated at 4.4 V (bq24070). If the system load exceeds the capacity of the supply, the

output voltage drops down to the battery's voltage.

Charge Control

When in AC mode the battery is charged through switch Q2 based on the charge rate set on the ISET1 input.

Dynamic Power-Path Management (DPPM)

This feature monitors the output voltage (system voltage) for input power loss due to brown outs, current limiting,

or removal of the input supply. If the voltage on the OUT pin drops to a preset value, V_(DPPM)× SF, due to a

limited amount of input current, then the battery charging current is reduced until the output voltage stops

dropping. The DPPM control tries to reach a steady-state condition where the system gets its needed current and

the battery is charged with the remaining current. No active control limits the current to the system; therefore, if

the system demands more current than the input can provide, the output voltage drops just below the battery

voltage and Q2 turns on which supplements the input current to the system. DPPM has three main advantages.

1. This feature allows the designer to select a lower power wall adapter, if the average system load is moderate

compared to its peak power. For example, if the peak system load is 1.75 A, average system load is 0.5 A

and battery fast-charge current is 1.25 A, the total peak demand could be 3 A. With DPPM, a 2-A adaptor

could be selected instead of a 3.25-A supply. During the system peak load of 1.75 A and charge load of 1.25

A, the smaller adaptor’s voltage drops until the output voltage reaches the DPPM regulation voltage

threshold. The charge current is reduced until there is no further drop on the output voltage. The system gets

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its 1.75-A charge and the battery charge current is reduced from 1.25 A to 0.25 A. When the peak system

load drops to 0.5 A, the charge current returns to 1 A and the output voltage returns to its normal value.

2. Using DPPM provides a power savings compared to configurations without DPPM. Without DPPM, if the

system current plus charge current exceed the supply’s current limit, then the output is pulled down to the

battery. Linear chargers dissipate the unused power (V_IN-V_OUT) × I_LOAD. The current remains high (at current

limit) and the voltage drop is large for maximum power dissipation. With DPPM, the voltage drop is less

(V_IN-V_(DPPM-REG)) to the system which means better efficiency. The efficiency for charging the battery is the

same for both cases. The advantages include less power dissipation, lower system temperature, and better

overall efficiency.

3. The DPPM sustains the system voltage no matter what causes it to drop, if at all possible. It does this by

reducing the noncritical charging load while maintaining the maximum power output of the adaptor.

Note that the DPPM voltage, V_(DPPM), is programmed as follows:

V

+ I

R

SF

(DPPM)

(DPPM−REG)

(DPPM)

(1)

where

R_(DPPM)is the external resistor connected between the DPPM and VSS pins.

I_(DPPM)is the internal current source.

SF is the scale factor as specified in the specification table.

The safety timer is dynamically adjusted while in DPPM mode. The voltage on the ISET1 pin is directly

proportional to the programmed charging current. When the programmed charging current is reduced, due to

DPPM, the ISET1 and TMR voltages are reduced and the timer’s clock is proportionally slowed, extending the

safety time. In normal operation V(TMR) = 2.5 V; and, when the clock is slowed, V(TMR) is reduced. When

V(TMR) = 1.25 V, the safety timer has a value close to 2 times the normal operation timer value. See Figure 6

through Figure 7.

Case 2: USB Mode (Mode = L)

System Power

In this case, the system load is powered from a USB port through the internal switch Q1 (see Figure 5). Note that

in this case, Q1 regulates the total current to the 100-mA or 500-mA level, as selected on the ISET2 input. The

output, V_OUT, is regulated to 4.4 V (bq24070). The system's power management is responsible for keeping its

system load below the USB current level selected (if the battery is critically low or missing). Otherwise, the output

drops to the battery voltage; therefore, the system should have a low-power mode for USB power application.

The DPPM feature keeps the output from dropping below its programmed threshold, due to the battery charging

current, by reducing the charging current.

Charge Control

When in USB mode, Q1 regulates the input current to the value selected by the ISET2 pin (0.1/0.5 A). The

charge current to the battery is set by the ISET1 resistor (typically > 0.5 A). Because the charge current typically

is programmed for more current than the USB current limit allows, the output voltage drops to the battery voltage

or DPPM voltage, whichever is higher. If the DPPM threshold is reached first, the charge current is reduced until

V_OUTstops dropping. If V_OUTdrops to the battery voltage, the battery is able to supplement the input current to

the system.

Dynamic Power-Path Management (DPPM)

The theory of operation is the same as described in CASE 1, except that Q1 is restricted to the USB current level

selected by the ISET2 pin.

Note that the DPPM voltage, V_(DPPM), is programmed as follows:

V

+ I

R

SF

(DPPM)

(DPPM−REG)

(DPPM)

(2)

where

R_(DPPM)is the external resistor connected between the DPPM and VSS pins.

I_(DPPM)is the internal current source.

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SF is the scale factor as specified in the specification table.

Feature Plots

Figure 6 illustrates DPPM and battery supplement modes as the output current (I_OUT) is increased; channel 1

(CH1) VAC = 5.4 V; channel 2 (CH2) V_OUT; channel 3 (CH3) I_OUT= 0 to 2.2 A to 0 A; channel 4 (CH4) V_BAT= 3.5

V; I_(PGM-CHG)= 1 A. In typical operation, bq24070/1 (V_OUT= 4.4 V_reg), through an AC adaptor overload condition

and recovery. The AC input is set for ~5.1 V (1.5 A current limit), I_(CHG)= 1 A, V_(DPPM-SET)= 3.7 V, V_(DPPM-OUT)

=

1.15 × V_(DPPM-SET)= 4.26 V, V_BAT= 3.5 V, Mode = H, and USB input is not connected. The output load is

increased from 0 A to ~2.2 A and back to 0 A as shown in the bottom waveform. As the I_OUTload reaches 0.5 A,

along with the 1-A charge current, the adaptor starts to current limit, the output voltage drops to the DPPM-OUT

threshold of 4.26 V. This is DPPM mode. The AC input tracks the output voltage by the dropout voltage of the

AC FET. The battery charge current is then adjusted back as necessary to keep the output voltage from falling

any further. Once the output load current exceeds the input current, the battery has to supplement the excess

current and the output voltage falls just below the battery voltage by the dropout voltage of the battery FET. This

is the battery supplement mode. When the output load current is reduced, the operation described is reversed as

shown. If the DPPM-OUT voltage was set below the battery voltage, during input current limiting, the output falls

directly to the battery's voltage.

Under USB operation, when the loads exceeds the programmed input current thresholds a similar pattern is

observed. If the output load exceeds the available USB current, the output instantly goes into the battery

supplement mode.

V

AC

V

OUT

V

Reg. @ 4.4 V (bq24070)

OUT

= 4.26 V, DPPM Mode

DPPM − OUT

V_OUT≈ V_OUT, ^{BAT Supplement Mode}

I

CHG

OUT

Figure 6. DPPM and Battery Supplement Modes

Figure 7 illustrates when Mode is toggled low for 500 μs. Power transfers from AC to USB to AC; channel 1

(CH1) VAC = 5.4 V; channel 2 (CH2) V_(USB)= 5 V; channel 3 (CH3) V_OUT; output current, I_OUT= 0.25 A; channel

4 (CH4) V_BAT= 3.5 V; and I_(PGM-CHG)= 1 A. When the Mode went low (1^stdiv), the AC FET opened, and the

output fell until the USB FET turned on. Turning off the active source before turning on the replacement source is

referred to as break-before-make switching. The rate of discharge on the output is a function of system

capacitance and load. Note the cable IR drop in the AC and USB inputs when they are under load. At the 4^th

division, the output has reached steady-state operation at the DPPM voltage level (charge current has been

reduced due to the limited USB input current). At the 6^thdivision, the Mode goes high and the USB FET turns off

followed by the AC FET turning on. The output returns to its regulated value, and the battery returns to its

programmed current level.

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Break Before Make

V

AC

V

USB

V

OUT

BAT

System Capacitance

Powering System

DPPM Mode

USB is Charging System Capacitance

Hi

PSEL

Low

Figure 7. Toggle Mode Low

Figure 8 illustrates when a battery is inserted for power up; channel 1 (CH1) VAC = 0 V; channel 2 (CH2) V_USB

0 V; channel 3 (CH3) V_OUT; output current, I_OUT= 0.25 A for V_OUT> 2 V; channel 4 (CH4) V_BAT= 3.5 V; C_(DPPM)

=

0 pF. When there are no power sources and the battery is inserted, the output tracks the battery voltage if there

is no load (<10 mA of load) on the output, as shown. If a load is present that keeps the output more than 200 mV

below the battery, a short-circuit condition is declared. At this time, the load has to be removed to recover. A

capacitor can be placed on the DPPM pin to delay implementing the short-circuit mode and get unrestricted (not

limited) current.

V

BAT

V

OUT

Figure 8. Insert Battery – Power-Up Output via BAT

Figure 9 illustrates USB boot up and power-up via USB; channel 1 (CH1) V_(USH)= 0 to 5 V; channel 2 (CH2) USB

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input current (0.2 A/div); Mode = Low; CE = High; ISET2 = High; V_BAT= 3.85 V; V_(DPPM)= 3.0 V (V_(DPPM)× 1.15 <

V_BAT, otherwise DPPM mode increases time duration). When a USB source is applied (if AC is not present), the

CE pin and ISET2 pin are ignored during the boot-up time and a maximum input current of 100 mA is made

available to the OUT or BAT pins. After the boot-up time, the IC implements the CE and ISET2 pins as

programmed.

V

AC

I

USB

Figure 9. USB Boot-Up Power-Up

Battery Temperature Monitoring

The bq24070/1 continuously monitors battery temperature by measuring the voltage between the TS and VSS

pins. An internal current source provides the bias for most-common 10 kΩ negative-temperature coefficient

thermistors (NTC) (see Figure 10). The device compares the voltage on the TS pin against the internal V_(LTF)and

V_(HTF)thresholds to determine if charging is allowed. Once a temperature outside the V_(LTF)and V_(HTF)thresholds

is detected, the device immediately suspends the charge. The device suspends charge by turning off the power

FET and holding the timer value (i.e., timers are not reset). Charge is resumed when the temperature returns to

the normal range. The allowed temperature range for 103AT-type thermistor is 0°C to 45°C. However, the user

may increase the range by adding two external resistors. See Figure 11.

PACK+

bq24070/1

+

PACK−

RT1

I

TS

PACK−

TS

I

TS

NTC

TEMP

NTC

12

LTF

BATTERY

PACK

V

LTF

BATTERY

PACK

V

LTF

RT2

V

HTF

V

HTF

UDG−04086

UDG−04085

Figure 10. TS Pin Configuration

Figure 11. TS Pin Thresholds

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Battery Pre-Conditioning

During a charge cycle, if the battery voltage is below the V_(LOWV)threshold, the bq24070/1 applies a precharge

current, I_O(PRECHG), to the battery. This feature revives deeply discharged cells. The R_SETresistor, connected

between the ISET1 and VSS pins, determines the precharge rate. The V_(PRECHG)and K_(SET)parameters are

specified in the specifications table. Note that this applies to both AC-mode and USB-mode charging.

V

K

(SET)

(PRECHG)

I

+

O (PRECHG)

R

SET

(3)

The bq24070/1 activates a safety timer, t_(PRECHG), during the conditioning phase. If V_(LOWV)threshold is not

reached within the timer period, the bq24070/1 turns off the charger and enunciates FAULT on the STAT1 and

STAT2 pins. The timeout is extended if the charge current is reduced by DPPM or thermal regulation. See the

Timer Fault Recovery section for additional details.

Battery Charge Current

The bq24070/1 offers on-chip current regulation with programmable set point. The R_SETresistor, connected

between the ISET1 and VSS pins, determines the charge level. The charge level may be reduced to give the

system priority on input current (see DPPM). The V_(SET)and K_(SET)parameters are specified in the specifications

table.

V

K

(SET)

I

+

O (OUT)

R

SET

(4)

When powered from a USB port, the input current available (0.1 A/0.5 A) is typically less than the programmed

(ISET1) charging current, and therefore, the DPPM feature attempts to keep the output from being pulled down

by reducing the charging current.

The charge level, during AC mode operation only (Mode = High), can be changed by a factor of 2 by setting the

ISET2 pin high (full charge) or low (half charge). The voltage on the ISET1 pin, VSET1, is divided by 2 when in

the half constant current charge mode. Note that with Mode low, the ISET2 pin controls only the 0.1 A/0.5 A USB

current level.

See the section titled Power-Path Management for additional details.

Battery Voltage Regulation

The voltage regulation feedback is through the BAT pin. This input is tied directly to the positive side of the

battery pack. The bq24070/1 monitors the battery-pack voltage between the BAT and VSS pins. When the

battery voltage rises to the V_O(REG)threshold, the voltage regulation phase begins and the charging current

begins to taper down.

If the battery is absent, the BAT pin cycles between charge done (V_O(REG)) and charging (battery recharge

threshold, ~4.1 V).

See Figure 8 for power up by battery insertion.

As a safety backup, the bq24070/1 also monitors the charge time in the charge mode. If charge is not terminated

within this time period, t_(CHG), the bq24070/1 turns off the charger and enunciates FAULT on the STAT1 and

STAT2 pins. See the DPPM operation under Case 1 for information on extending the safety timer during DPPM

operation. See theTimer Fault Recovery section for additional details.

Temperature Regulation and Thermal Protection

In order to maximize charge rate, the bq24070/1 features a junction temperature regulation loop. If the power

dissipation of the IC results in a junction temperature greater than the T_J(REG)threshold, the bq24070/1 throttles

back on the charge current in order to maintain a junction temperature around the T_J(REG)threshold. To avoid

false termination, the termination detect function is disabled while in this mode.

The bq24070/1 also monitors the junction temperature, T_J, of the die and disconnects the OUT pin from the IN

input if T_Jexceeds T_(SHTDWN). This operation continues until T_Jfalls below T_(SHTDWN)by the hysteresis level

specified in the specification table.

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The battery supplement mode has no thermal protection. The Q2 FET continues to connect the battery to the

output (system), if input power is not sufficient; however, a short-circuit protection circuit limits the battery

discharge current such that the maximum power dissipation of the part is not exceeded under typical design

conditions.

Charge Timer Operation

As a safety backup, the bq24070/1 monitors the charge time in the charge mode. If the termination threshold is

not detected within the time period, t_(CHG), the bq24070/1 turns off the charger and enunciates FAULT on the

STAT1 and STAT2 pins. The resistor connected between the TMR and VSS, R_TMR, determines the timer period.

The K_(TMR)parameter is specified in the specifications table. In order to disable the charge timer, eliminate R_TMR

,

connect the TMR pin directly to the V_REFpin. Note that this action eliminates the fast-charge safety timer (it does

not disable or reset the pre-charge safety timer), and also clears any timer fault. TMR pin should not be left

floating.

t

+ K

R

(TMR) (TMR)

(CHG)

(5)

While in the thermal regulation mode or DPPM mode, the bq24070/1 dynamically adjusts the timer period in

order to provide the additional time needed to fully charge the battery. This proprietary feature is designed to

prevent against early or false termination. The maximum charge time in this mode, t_(CHG-TREG), is calculated by

Equation 6.

t

V

(SET)

(CHG)

+

t

(CHG−TREG)

V

(SET*REG)

(6)

Note that because this adjustment is dynamic and changes as the ambient temperature changes and the charge

level changes, the timer clock is adjusted. It is difficult to estimate a total safety time without integrating the

above equation over the charge cycle. Therefore, understanding the theory that the safety time is adjusted

inversely proportionately with the charge current and the battery is a current-hour rating, the safety time

dynamically adjusts appropriately.

The V_(SET)parameter is specified in the specifications table. V_(SET-TREG)is the voltage on the ISET pin during the

thermal regulation or DPPM mode and is a function of charge current. (Note that charge current is dynamically

adjusted during the thermal regulation or DPPM mode.)

I

R

(OUT)

+

(SET)

V

(SET−TREG)

K

(SET)

(7)

All de-glitch times also adjusted proportionally to t_(CHG-TREG)

.

Charge Termination and Recharge

The bq24070/1 monitors the voltage on the ISET1 pin, during voltage regulation, to determine when termination

should occur. Termination occurs when the charge current tapers down to either 1/10^thof the programmed fast

charge rate (when the MODE pin is high) or 1/25^thof the programmed fast charge rate (when the MODE pin is

low). Once the termination threshold, I_(TERM), is detected the bq24070/1 terminates charge. The R_SETresistor,

connected between the ISET1 and VSS pins, programs the fast charge current level and thus the current

termination threshold level. The V_(TERM)and K_(SET)parameters are specified in the specifications table. Note that

this applies to both AC and USB charging.

V

K

(TERM)

(SET)

I

+

(TERM)

R

SET

(8)

After charge termination, the bq24070/1 re-starts the charge once the voltage on the BAT pin falls below the

V_(RCH)threshold. This feature keeps the battery at full capacity at all times.

Sleep and Standby Modes

The bq24070/1 charger circuitry enters the low-power sleep mode if the input is removed from the circuit. This

feature prevents draining the battery into the bq24070/1 during the absence of input supply. Note that in sleep

mode, Q2 remains on (i.e., battery connected to the OUT pin) in order for the battery to continue supplying power

to the system.

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The bq24070/1 enters the low-power standby mode if while input power is present, the CE input is low. In this

suspend mode, internal power FET Q1 (see Figure 5) is turned off, the BAT input is used to power the system

through the OUT pin. This feature is designed to limit the power drawn from the input supply (such as USB

suspend mode).

Charge Status Outputs

The open-drain (OD) STAT1 and STAT2 outputs indicate various charger operations as shown in Table 2. These

status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the

open-drain transistor is turned off. Note that this assumes CE = High.

Table 2. Status Pins Summary

CHARGE STATE

Precharge in progress

STAT1

ON

STAT2

ON

Fast charge in progress

ON

OFF

ON

Charge done

OFF

Charge suspend (temperature), timer fault, and sleep mode

OFF

PG, Outputs (Power Good)

The open-drain pin, PG, indicates when input power is present, and above the battery voltage. The

corresponding output turns ON (low) when exiting sleep mode (input voltage above battery voltage). This output

is turned off in the sleep mode (open drain). The PG pin can be used to drive an LED or communicate to the

host processor. Note that OFF indicates the open-drain transistor is turned off.

CE Input (Chip Enable)

The CE (chip enable) digital input is used to disable or enable the IC. A high-level signal on this pin enables the

chip, and a low-level signal disables the device and initiates the standby mode. The bq24070/1 enters the

low-power standby mode when the CE input is low with input present. In this suspend mode, internal power FET

Q1 (see block diagram) is turned off; the battery (BAT pin) is used to power the system via Q2 and the OUT pin.

This feature is designed to limit the power drawn from the input supply (such as USB suspend mode).

Charge Disable Functions

The DPPM input can be used to disable the charge process. This can be accomplished by floating the DPPM

pin.

Timer Fault Recovery

As shown in Figure 4, bq24070/1 provides a recovery method to deal with timer fault conditions. The following

summarizes this method:

Condition 1: Charge voltage above recharge threshold (V_(RCH)) and timeout fault occurs.

Recovery Method: bq24070/1 waits for the battery voltage to fall below the recharge threshold. This could

happen as a result of a load on the battery, self-discharge, or battery removal. Once the battery falls below the

recharge threshold, the bq24070/1 clears the fault and starts a new charge cycle. A POR or CE toggle also

clears the fault.

Condition 2: Charge voltage below recharge threshold (V_(RCH)) and timeout fault occurs.

Recovery Method: Under this scenario, the bq24070/1 applies the I_(FAULT)current. This small current is used to

detect a battery removal condition and remains on as long as the battery voltage stays below the recharge

threshold. If the battery voltage goes above the recharge threshold, then the bq24070/1 disables the I_(FAULT)

current and executes the recovery method described for condition 1. Once the battery falls below the recharge

threshold, the bq24070/1 clears the fault and starts a new charge cycle. A POR or CE toggle also clears the

fault.

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19

Product Folder Link(s): bq24070 bq24071

bq24070

bq24071

SLUS694F –MARCH 2006–REVISED DECEMBER 2009

www.ti.com

Short-Circuit Recovery

The output can experience two types of short-circuit protection, one associated with the input and one with the

battery.

If the output drops below ~1 V, an input short-circuit condition is declared and the input FET, Q1 is turned off. To

recover from this state, a 500-Ω pullup resistor from the input is applied (switched) to the output. To recover, the

load on the output has to be reduced {R_load> 1 V × 500 Ω/ (V_in–V_out)} such that the pullup resistor is able to lift

the output voltage above 1 V, for the input FET to be turned back on.

If the output drops 200 mV below the battery voltage, the battery FET, Q2 is considered in short circuit and the

battery FET turns off. To recover from this state, there is a 10-mA current source from the battery to the output.

Once the output load is reduced, such that the 10-mA current source can pick up the output within 200 mV of the

battery, the FET turns back on.

If the short is removed, and the minimum system load is still too large [R<(VBat-200 mV) / 10 mA], the

short-circuit protection can be temporarily defeated. The battery short-circuit protection can be disabled

(recommended only for a short time) if the voltage on the DPPM pin is less than 1 V. Pulsing this pin below 1 V,

for a few microseconds, should be enough to recover.

This short-circuit disable feature was implemented mainly for power up when inserting a battery. Because the

BAT input voltage rises much faster than the OUT voltage (V_out<V_bat-200 mV), with most any capacitive load on

the output, the part can get stuck in short-circuit mode. Placing a capacitor between the DPPM pin and ground

slows the V_DPPMrise time, during power up, and delays the short-circuit protection. Too large a capacitance on

this pin (too much of a delay) could allow too-high currents if the output was shorted to ground. The

recommended capacitance is 1 nF to 10 nF. The V_DPPMrise time is a function of the 100-μA DPPM current

source, the DPPM resistor, and the capacitor added.

V_REF

The V_REFis used for internal reference and compensation (3.3 V typ). Additionally, it can be used to disable the

safety timer and termination by connecting the TMR to the V_REFpin. For internal compensation, the V_REFpin

requires a minimum 0.1 μF ceramic capacitor. The V_REFcapacitor should not exceed 1 μF.

20

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Product Folder Link(s): bq24070 bq24071

bq24070

bq24071

www.ti.com

SLUS694F –MARCH 2006–REVISED DECEMBER 2009

APPLICATION INFORMATION

Selecting the Input and Output Capacitors

In most applications, all that is needed is a high-frequency decoupling capacitor on the input. A 0.1-μF ceramic

capacitor, placed in close proximity to IN to VSS pins, works well. In some applications depending on the power

supply characteristics and cable length, it may be necessary to add an additional 10-μF ceramic capacitor to the

input.

The bq24070/1 only requires a small output capacitor for loop stability. A 0.1-μF ceramic capacitor placed

between the OUT and VSS pin is typically sufficient.

It is recommended to install a minimum of 33-μF capacitor between the BAT pin and VSS (in parallel with the

battery). This ensures proper hot plug power up with a no-load condition (no system load or battery attached).

Thermal Considerations

The bq24070/1 is packaged in a thermally enhanced MLP package. The package includes a QFN thermal pad to

provide an effective thermal contact between the device and the printed-circuit board (PCB). Full PCB design

guidelines for this package are provided in the application note entitled QFN/SON PCB Attachment (SLUA271).

The power pad should be tied to the VSS plane. The most common measure of package thermal performance is

thermal impedance (θ_JA) measured (or modeled) from the chip junction to the air surrounding the package

surface (ambient).

The mathematical expression for θ_JAis:

T * T

J

A

q

+

JA

P

(9)

where

T_J= chip junction temperature

T_A= ambient temperature

P = device power dissipation

Factors that can greatly influence the measurement and calculation of θ_JAinclude:

•

whether or not the device is board mounted

trace size, composition, thickness, and geometry

orientation of the device (horizontal or vertical)

volume of the ambient air surrounding the device under test and airflow

whether other surfaces are in close proximity to the device being tested

The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal power

FET. It can be calculated from Equation 10:

_{P +}ƪǒ_V

Ǔ ǒ

I

_BATǓƫ₎ƪǒ_V

Ǔ ǒ _BATǓƫ

I

* V

) I

* V

IN

OUT

BAT

(10)

Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of

the charge cycle when the battery voltage is at its lowest. See Figure 2. Typically the Li-ion battery's voltage

quickly (< 2 V minutes) ramps to approximately 3.5 V, when entering fast charge (1-C charge rate and battery

above 3 V). Therefore, it is customary to perform the steady-state thermal design using 3.5 V as the minimum

battery voltage because the system board and charging device does not have time to reach a maximum

temperature due to the thermal mass of the assembly during the early stages of fast charge. This theory is easily

verified by performing a charge cycle on a discharged battery while monitoring the battery voltage and chargers

power pad temperature.

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Product Folder Link(s): bq24070 bq24071

bq24070

bq24071

SLUS694F –MARCH 2006–REVISED DECEMBER 2009

www.ti.com

PCB Layout Considerations

It is important to pay special attention to the PCB layout. The following provides some guidelines:

•

To obtain optimal performance, the decoupling capacitor from the input terminal to VSS and the output filter

capacitor from OUT to VSS should be placed as close as possible to the bq24070/1, with short trace runs to

both signal and VSS pins.

•

All low-current VSS connections should be kept separate from the high-current charge or discharge paths

from the battery. Use a single-point ground technique incorporating both the small signal ground path and the

power ground path.

•

The high-current charge paths into IN and from the BAT and OUT pins must be sized appropriately for the

maximum charge current in order to avoid voltage drops in these traces.

The bq24070/1 is packaged in a thermally enhanced MLP package. The package includes a QFN thermal

pad to provide an effective thermal contact between the device and the printed-circuit board. Full PCB design

guidelines for this package are provided in the application note entitled QFN/SON PCB Attachment

(SLUA271).

22

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Product Folder Link(s): bq24070 bq24071

bq24070

bq24071

www.ti.com

SLUS694F –MARCH 2006–REVISED DECEMBER 2009

Changes from Revision E (October 2009) to Revision F

Page

•

Changed Charge Termination and Recharge description .................................................................................................. 18

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23

Product Folder Link(s): bq24070 bq24071

PACKAGE MATERIALS INFORMATION

www.ti.com

27-Jul-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

BQ24070RHLR

BQ24070RHLT

BQ24071RHLR

BQ24071RHLT

VQFN

RHL

20

3000

250

330.0

180.0

330.0

180.0

12.4

3.8

4.8

1.6

1.3

1.6

8.0

12.0

Q1

250

3000

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

27-Jul-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

BQ24070RHLR

BQ24070RHLT

BQ24071RHLR

BQ24071RHLT

VQFN

RHL

20

3000

250

367.0

370.0

195.0

210.0

367.0

210.0

367.0

355.0

200.0

185.0

367.0

185.0

35.0

55.0

45.0

35.0

250

3000

250

Pack Materials-Page 2

IMPORTANT NOTICE

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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

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supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

型号:	BQ24071RHLRG4
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Obsolete
IHS 制造商：	TEXAS INSTRUMENTS INC
零件包装代码：	QFN
包装说明：	3.50 X 4.50 MM, GREEN, PLASTIC, QFN-20
针数：	20
Reach Compliance Code：	unknown
ECCN代码：	EAR99
HTS代码：	8542.39.00.01
风险等级：	5.18
Is Samacsys：	N
可调阈值：	YES
模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	R-PQCC-N20
JESD-609代码：	e4
长度：	4.5 mm
湿度敏感等级：	2
信道数量：	1
功能数量：	1
端子数量：	20
最高工作温度：	125 °C
最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN
封装等效代码：	LCC20/24,.14X.18,20
封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260
电源：	4.3/16 V
认证状态：	Not Qualified
座面最大高度：	1 mm
子类别：	Power Management Circuits
最大供电电流 (Isup)：	2 mA
最大供电电压 (Vsup)：	16 V
最小供电电压 (Vsup)：	4.35 V
表面贴装：	YES
温度等级：	AUTOMOTIVE
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	NO LEAD
端子节距：	0.5 mm
端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.5 mm
Base Number Matches：	1

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