This method of address mapping provides for a "mailbox" allo-
cation scheme for the storage of data words.The 12 address out-
puts may be used to map into 4K words of processor address
space. The SSRT Mark3's addressing scheme maps messages
in terms of broadcast/ownaddress, transmit/receive, subad-
dress, and word/count mode code. A 32-word message block is
allocated for each T/R-subaddress.
this, the burst mode and the non-burst mode. In burst mode, all
received data words are transferred from the SSRT Mark3 to the
subsystem in a contiguous burst, only following the reception of
the correct number of valid data words. In the non-burst mode,
single data words are written to the external subsystem immedi-
ately following the reception of each individual data word.
To initiate a DMA write cycle, the SSRT Mark3 asserts DTREQ
low. The subsystem must then respond with DTGRT low.
Assuming that DTGRT was asserted in time, the SSRT Mark3
will then assert DTACK low.The SSRT Mark3 will then assert the
appropriate value of L_BRO, T/R, SA4-0, and MC/CWC4-0,
MEMOE high, and MEMWR low. MEMWR will be asserted low
for one clock cycle. The subsystem may then use either the
falling or rising edge of MEMWR to latch the data. Similar to the
DMA read operation, the address outputs CWC4 through CWC0
are incremented after the completion of a DMA write operation.
For non-mode code messages, the Data Words to be transmit-
ted or received are accessed from (to) relative locations
0 through 31 within the respective message block. For the
MIL-STD-1553B Synchronize with data, Selected transmitter
shutdown, Override selected transmitter shutdown, and Transmit
vector word mode commands which involve a single data word
transfer, the address for the data word is offset from location 0
of the message block for subaddresses 0 and 31 by the value of
the mode code field of the received command word.
The data words transmitted in response to the Transmit last
command or Transmit BIT word mode commands are accessed
from a pair of internal registers.
HANDSHAKE FAIL
Following the assertion of DTREQ low by the SSRT Mark3, the
external subsystem has 10 µs to respond by asserting DTACK to
logic "0".
DMA INTERFACE
A 16-bit data bus, a 12-bit address bus, and six control signals
are provided to facilitate communication with the parallel sub-
system. The data bus D15-D0 consists of bi-directional tri-state
signals. The address bus L_BRO, T/R, SA4-SA0, and
WC/MC/CWC4-0; along with the data transfer control signals
MEMOE and MEMWR are two-state output signals.
If the SSRT Mark3 (SSRT Mark3) asserts DTREQ and the sub-
system does not respond with DTGRT in time for the SSRT
Mark3 to complete a data word transfer, the HSFAIL output will
be asserted low to inform the subsystem of the handshake fail-
ure, and bit 12 in the internal Built-In-Test (BIT) word will be set
to logic "1". If the handshake failure occurs on a data word read
transfer (for a transmit command), the SSRT Mark3 will abort the
current message transmission. In the case of a handshake fail-
ure on a write transfer (received command) the SSRT Mark3 will
set the handshake failure output and BIT word bit, and abort pro-
cessing the current message.
The control signals include the standard DMA handshake sig-
nals DTREQ, DTGRT, DTACK, as well as the transfer control
outputs MEMOE and MEMWR. HS_FAIL provides an indication
to the subsystem of a handshake failure condition.
Data transfers between the subsystem and the SSRT Mark3 are
performed by means of a DMA handshake, initiated by
the SSRT Mark3. A data read operation is defined to be the trans-
fer of data from the subsystem to the SSRT Mark3. Conversely, a
data write operation transfers data from the SSRT Mark3 to the
subsystem. Data is transferred as a single 16-bit word.
MESSAGE PROCESSING OPERATION
Following the receipt and transfer of a valid Command Word, the
SSRT Mark3 will attempt to perform one of the following opera-
tions: (1) transfer received 1553 data to the subsystem, (2) read
data from the subsystem for transmission on the 1553 bus, (3)
transmit status (and possibly the last command word or RT BIT
word) on the 1553 bus, and/or (4) set status word conditions.
DMA READ OPERATION
In response to a transmit command, the SSRT Mark3 needs to
read data words from the external subsystem. To initiate a data
word read transfer, the SSRT Mark3 asserts the signal DTREQ
low. Assuming that the subsystem asserts DTGRT in time, the
SSRT Mark3 will then assert the appropriate values of L_BRO
(logic "0"), T/R (high), SA4-0, and MC/CWC4-0; MEMWR high,
along with DTACK low and MEMOE low to enable data to be
read from the subsystem.
The SSRT Mark3 responds to all non-broadcast messages to its
RT address with a 1553 Status Word.
RT ADDRESS
RT Address 4-0 (RT_AD_4 = MSB) and RT Address Parity
(RT_AD_P) should be programmed for a unique RT address and
reflect an odd parity sum. The SSRT Mark3 will not respond to
any MIL-STD-1553 commands or transfer received data from
any non-broadcast messages if an odd parity sum is not pre-
sented by RT_AD_4-0 and RT_AD_P. An address parity error will
be indicated by a low output on the RT_AD_ERR pin. The input
signal RT_AD_LAT operates a transparent latch for RTAD4-
RTAD0 and RTADP. If RT_AD_LAT is low, the output of the latch
tracks the value presented on the input pins. If RT_AD_LAT is
high, the output of the internal latch becomes latched to the val-
After the transfer of each Data Word has been completed, the value
of the address bus outputs CWC4 through CWC0 is incremented.
DMA WRITE OPERATION
In response to a receive command, the SSRT Mark3 will need to
transfer data to the subsystem. There are two options for doing
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