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产品型号BU3071HFV-TR的Datasheet PDF文件预览

TECHNICAL NOTE  
High-performance Clock Generator Series  
Compact 1ch  
Clock Generators  
for Digital Cameras  
BU3071HFV, BU3072HFV, BU3073HFV, BU3076HFV  
BU7322HFV, BU7325HFV  
Description  
These Clock Generators incorporates compact package compared to oscillators, which provides the generation of  
high-frequency CCD, USB, VIDEO clocks necessary for digital still cameras and digital video cameras.  
Features  
1) SEL pin allowing for the selection of frequencies  
2) Selection of OE pin enabling Power-down function  
3) Crystal-oscillator-level clock precision with high C/N characteristics and low jitter  
4) Microminiature HVSOF6 Package incorporated  
5) Single power supply of 3.3 V  
Applications  
Digital Still Camera, Digital Video Camera, and others  
Lineup  
BU3071HFV  
3.0 V3.6V  
-5℃~70℃  
BU3072HFV  
3.0 V3.6V  
-5℃~70℃  
BU3073HFV  
BU3076HFV  
BU7322HFV  
BU7325HFV  
Supply voltage  
3.0 V3.6V 2.85 V3.6V 2.85 V3.6V 2.85 V3.6V  
Operating temperature range  
Reference input clock  
Output clock  
-5℃~70℃  
-5℃~75℃  
-5℃~75℃  
-30℃~85℃  
28.6363MHz 48.0000MHz 48.0000MHz  
54.0000MHz 27.0000MHz 24.3750MHz  
27.0000MHz  
27.0000MHz 27.0000MHz  
54.0000MHz 49.5000MHz 48.0000MHz  
67.5000MHz 36.0000MHz 78.0000MHz  
-
36.0000MHz 24.5454MHz  
Power-down function  
Operating current (TYP)  
Package  
Provided  
10mA  
Provided  
11mA  
Provided  
11mA  
Provided  
12mA  
Provided  
10mA  
Provided  
12mA  
HVSOF6  
HVSOF6  
HVSOF6  
HVSOF6  
HVSOF6  
HVSOF6  
Absolute Maximum RatingsTa=25℃)  
Symbol  
Limit  
-0.34.0  
Unit  
Supply voltage  
VDD  
VIN  
Tstg  
Pd  
V
V
Input voltage  
-0.3VDD+0.3  
-30125  
410  
Storage temperature range  
Power dissipation  
mW  
*1 Operating is not guaranteed.  
*2 In the case of exceeding Ta = 25, 4.1mW should be reduced per 1℃.  
*3 The radiation-resistance design is not carried out.  
*4 Power dissipation is measured when the IC is mounted to the printed circuit board.  
Sep. 2008  
Recommended Operating Range  
Parameter  
Symbol  
VDD  
VINH  
VINL  
Topr  
Limit  
3.03.6  
Unit  
Supply voltage  
Input H voltage  
Input L voltage  
Operating temperature  
Output load  
0.8VDDVDD  
0.00.2VDD  
-570  
CL  
15(MAX)  
pF  
Electrical characteristics  
BU3071HFVTa=25, VDD=3.3V,Crystal frequency=28.6363MHz, unless otherwise specified.)  
Parameter  
Output H voltage  
Symbol  
VOH  
Min.  
Typ.  
Max.  
-
Unit  
V
Conditions  
2.8  
-
IOH=-4.0mA  
IOL=4.0mA  
Output L voltage  
VOL  
-
-
-
-
-
10  
0.5  
15  
1.3  
-
V
Consumption current 1  
Consumption current 2  
Output frequency  
IDD1  
IDD2  
mA  
mA  
OE=H, at no load  
OE=L  
1
54.0000  
MHz IN*264/35/4  
The following parameters represent design guaranteed performance.  
Duty  
Duty  
45  
-
50  
50  
55  
-
%
Measured at a voltage of 1/2 of VDD  
Period-Jitter 1σ  
Period-Jitter MIN-MAX  
Rise time  
PJsSD  
PJsABS  
psec 1  
psec 2  
-
300  
-
Period of transition time required for the  
tr  
-
2.5  
-
nsec output to reach 80% from 20% of VDD.  
Provided with 15pF output load.  
Period of transition time required for the  
nsec output to reach 20% from 80% of VDD.  
Provided with 15pF output load.  
Fall time  
tf  
-
-
2.5  
-
-
Output Lock time  
tLOCK  
1
msec 3  
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.If the input  
frequency is set to 28.6363MHz, the output frequency will be as listed above.  
BU3072HFVTa=25, VDD=3.3V, Crystal frequency=48.0000MHz, unless otherwise specified.)  
Parameter  
Output H voltage  
Symbol  
VOH  
Min.  
Typ.  
Max.  
Unit  
V
Conditions  
2.8  
-
-
0.5  
16  
5
IOH=-4.0mA  
IOL=4.0mA  
Output L voltage  
VOL  
-
-
-
-
-
-
11  
V
Consumption current 1  
Consumption current 2  
Output frequency  
IDD1  
mA  
μA  
PD=H, at no load  
PD=L  
IDD2  
-
CLK_27  
CLK_36  
27.0000  
36.0000  
-
MHz SEL=L, IN*18/8/4  
MHz SEL=H, IN*24/8/4  
-
The following parameters represent design guaranteed performance.  
Duty  
Duty  
45  
-
50  
35  
55  
-
%
Measured at a voltage of 1/2 of VDD  
Period-Jitter 1σ  
Long-Term-Jitter  
MIN-MAX  
PJsSD  
psec 1  
MIN-MAX of long-term jitter (100 sec  
from trigger)  
LTJsABS  
-
0.9  
1.5  
nsec  
Period of transition time required for the  
Rise time  
tr  
-
2.5  
-
nsec output to reach 80% from 20% of VDD.  
Provided with 15pF output load.  
Period of transition time required for the  
Fall time  
tf  
-
-
2.5  
-
-
nsec  
output to reach 20% from 80% of VDD.  
Provided with 15pF output load.  
Output Lock time  
tLOCK  
1
msec 3  
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.If the input  
frequency is set to 48.0000MHz, the output frequency will be as listed above.  
2/20  
BU3073HFVTa=25, VDD=3.3V, Crystal frequency=48.0000MHz, unless otherwise specified.)  
Parameter  
Output H voltage  
Symbol  
VOH  
Min.  
Typ.  
Max.  
Unit  
V
Conditions  
2.8  
-
-
0.5  
16  
5
IOH=-4.0mA  
IOL=4.0mA  
Output L voltage  
VOL  
-
-
-
-
-
-
11  
V
Consumption current 1  
Consumption current 2  
Output frequency  
IDD1  
mA  
mA  
MHz  
MHz  
PD=H, at no load  
PD=L  
IDD2  
-
CLK_375  
CLK_545  
24.3750  
24.5454  
-
SEL=L, IN*65/16/8  
SEL=H, IN*45/11/8  
-
The following parameters represent design guaranteed performance.  
Duty  
Duty  
45  
-
50  
45  
55  
-
%
Measured at a voltage of 1/2 of VDD  
Period-Jitter 1σ  
Long-Term-Jitter  
MIN-MAX  
PJsSD  
psec 1  
MIN-MAX of long-term jitter (100 sec  
from trigger)  
LTJsABS  
tr  
-
-
0.9  
2.5  
1.5  
-
nsec  
nsec  
Period of transition time required for the  
output to reach 80% from 20% of VDD.  
Provided with 15pF output load.  
Period of transition time required for the  
output to reach 20% from 80% of VDD.  
Provided with 15pF output load.  
Rise time  
Fall time  
tf  
-
-
2.5  
-
-
nsec  
Output Lock time  
tLOCK  
1
msec 3  
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.  
If the input frequency is set to 48.0000MHz, the output frequency will be as listed above.  
BU3076HFVTa=25, VDD=3.3V, Crystal frequency=27.0000MHz, unless otherwise specified.)  
Parameter  
Output H voltage  
Symbol  
VOH  
VOL  
Min.  
Typ.  
Max.  
-
Unit  
V
Conditions  
2.8  
-
IOH=-4.0mA  
IOL=4.0mA  
Output L voltage  
-
25  
-
-
0.5  
100  
15  
18  
1
V
Pull-down resistance  
Consumption current 1  
Consumption current 2  
Standby current  
Rpd  
50  
10  
KΩ  
mA  
mA  
μA  
MHz  
MHz  
Pull-down resistance on input pin  
54MHz output, at no load  
67.5MHz output, at no load  
OE=L  
IDD1  
IDD2  
IDDst  
-
12  
-
-
Output frequency  
CLK_54  
-
54.0000  
67.5000  
-
SEL=L, IN*48/6/4  
CLK_67.5  
-
-
SEL=H, IN*60/6/4  
The following parameters represent design guaranteed performance.  
Duty  
Duty  
45  
-
50  
50  
55  
-
%
Measured at a voltage of 1/2 of VDD  
Period-Jitter 1σ  
Period-Jitter MIN-MAX  
Rise time  
PJsSD  
PJsABS  
psec  
psec  
1  
-
300  
-
2  
Period of transition time required for the  
output to reach 80% from 20% of VDD.  
Provided with 15pF output load.  
Period of transition time required for the  
output to reach 20% from 80% of VDD.  
Provided with 15pF output load.  
tr  
-
1.5  
-
nsec  
Fall time  
tf  
-
-
1.5  
-
-
nsec  
usec  
Output Lock time  
tLOCK  
200  
3  
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.  
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.  
3/20  
BU7322HFVTa=25, VDD=3.3V, Crystal frequency=27.0000MHz, unless otherwise specified.)  
Parameter  
Output H voltage  
Symbol  
VOH  
Min.  
Typ.  
-
Max.  
-
Unit  
V
Conditions  
2.8  
IOH=-4.0mA  
IOL=4.0mA  
VOL  
-
25  
-
-
0.5  
100  
13.5  
13.0  
1
V
Output L voltage  
Ω
Rpd  
50  
10  
9.5  
-
k
Pull-down resistance on input pin  
49.5MHz output, at no load  
36.0MHz output, at no load  
OE=L  
Pull-down resistance  
Consumption current 1  
Consumption current 2  
Standby current  
IDD  
mA  
mA  
IDD2  
-
μ
A
IDDst  
-
CLK_49.5  
CLK_36  
-
-
MHz  
MHz  
SEL=L, IN*66/6/6  
Output frequency  
49.5000  
36.0000  
-
-
SEL=H, IN*64/6/8  
The following parameters represent design guaranteed performance.  
Duty  
45  
-
50  
50  
55  
-
%
Duty  
Measured at a voltage of 1/2 of VDD  
PJsSD  
PJsABS  
psec  
psec  
Period-Jitter 1σ  
Period-Jitter MIN-MAX  
Rise time  
1  
-
300  
-
2  
Period of transition time required for the  
output to reach 80% from 20% of VDD.  
Provided with 15pF output load.  
Period of transition time required for the  
output to reach 20% from 80% of VDD.  
Provided with 15pF output load.  
tr  
-
2.5  
-
nsec  
Fall time  
tf  
-
-
2.5  
-
-
nsec  
usec  
tLOCK  
200  
Output Lock time  
3  
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.  
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.  
BU7325HFV Ta=25 , VDD=3.3V, Crystal frequency=27.0000MHz, unless otherwise specified.  
Parameter  
Output H voltage  
Symbol  
VOH  
Min.  
Typ.  
Max.  
-
Unit  
V
Conditions  
2.8  
-
IOH=-4.0mA  
IOL=4.0mA  
VOL  
-
25  
-
-
0.5  
100  
15  
16.5  
1
V
Output L voltage  
Ω
Rpd  
50  
11  
k
Pull-down resistance on input pin  
OE=H, SEL=L, at no load  
OE=H, SEL=H, at no load  
OE=L  
Pull-down resistance  
Consumption current 1  
Consumption current 2  
Standby current  
IDD1  
mA  
mA  
IDD2  
-
12  
μ
A
IDDst  
CLK_48  
CLK_78  
-
-
-
48.0000  
78.0000  
-
MHz  
MHz  
SEL=L, IN*96/9/6  
Output frequency  
-
-
SEL=H, IN*104/9/4  
The following parameters represent design guaranteed performance.  
Duty  
45  
-
50  
50  
55  
-
%
Measured at a voltage of 1/2 of VDD  
Duty  
PJsSD  
PJsABS  
psec  
psec  
Period-Jitter 1σ  
Period-Jitter MIN-MAX  
Rise time  
1  
-
300  
-
2  
Period of transition time required for the  
output to reach 80% from 20% of VDD.  
Provided with 15pF output load.  
Period of transition time required for the  
output to reach 20% from 80% of VDD.  
Provided with 15pF output load.  
tr  
-
1.5  
-
nsec  
Fall time  
tf  
-
-
1.5  
-
-
nsec  
usec  
tLOCK  
200  
Output Lock time  
3  
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.  
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.  
Common to BU3071HFV, BU3072HFV, BU3073HFV, BU3076HFV, BU7322HFV, BU7325HFV  
1  
Period-Jitter 1σ  
This parameter represents standard deviation (1σ) on cycle distribution data at the time when the output clock cycles are  
sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.  
2  
Period-Jitter MIN-MAX  
This parameter represents a maximum distribution width on cycle distribution data at the time when the output clock cycles are  
sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.  
3  
Output Lock Time  
This parameter represents elapsed time after power supply turns ON to reach a voltage of 3.0 V, after the system is switched from  
Power-Down state to normal operation state, or after the output frequency is switched, until it is stabilized at a specified frequency,  
respectively.  
4/20  
Reference data (BU3071HFV basic data)  
RBW:1kHz  
VBW:100Hz  
5nsec/div  
500psec/div  
10kHz/div  
Fig.1 54MHz output waveform  
Fig.3 54MHz spectrum  
Fig.2 54MHz Period-Jitter  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
Reference data (BU3072HFV basic data)  
RBW:1kHz  
VBW:100Hz  
10nsec/div  
500psec/div  
10kHz/div  
Fig.4 27MHz output waveform  
Fig.5 27MHz Period-Jitter  
Fig.6 27MHz spectrum  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
RBW:1kHz  
VBW:100Hz  
5nsec/div  
500psec/div  
10kHz/div  
Fig.7 36MHz output waveform  
Fig.8 36MHz Period-Jitter  
Fig.9 36MHz spectrum  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
5/20  
Reference data (BU3073HFV basic data)  
RBW:1kHz  
VBW:100Hz  
10nsec/div  
500psec/div  
10kHz/div  
Fig.10 24.375MHz output waveform  
Fig.11 24.375MHz Period-Jitter  
Fig.12 24.375MHz spectrum  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
RBW:1kHz  
VBW:100Hz  
10nsec/div  
500psec/div  
10kHz/div  
Fig.13 24.5454MHz output waveform  
Fig.14 24.5454MHz Period-Jitter  
Fig.15 24.5454MHz spectrum  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
Reference data (BU3076HFV basic data)  
RBW:1kHz  
VBW:100Hz  
5nsec/div  
500psec/div  
10kHz/div  
Fig.16 54MHz output waveform  
Fig.17 54MHz Period-Jitter  
Fig.18 54MHz spectrum  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
RBW:1kHz  
VBW:100Hz  
2nsec/div  
500psec/div  
10kHz/div  
Fig.19 67.5MHz output waveform  
Fig.20 67.5MHz Period-Jitter  
Fig.21 67.5MHz spectrum  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
6/20  
Reference data (BU7322HFV basic data)  
RBW:1kHz  
VBW:100Hz  
5nsec/div  
500psec/div  
10kHz/div  
Fig.22 49.5MHz output waveform  
Fig.23 49.5MHz Period-Jitter  
Fig.24 49.5MHz spectrum  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
RBW:1kHz  
VBW:100Hz  
10nsec/div  
500psec/div  
10kHz/div  
Fig.25 36MHz output waveform  
Fig.26 36MHz Period-Jitter  
Fig.27 36MHz spectrum  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
Reference data (BU7325HFV basic data)  
RBW:1kHz  
VBW:100Hz  
5nsec/div  
500psec/div  
10kHz/div  
Fig.30 48MHz spectrum  
(VDD=3.3V,CL=15pF,Ta=25)  
Fig.28 48MHz output waveform  
(VDD=3.3V,CL=15pF,Ta=25)  
Fig.29 48MHz Period-Jitter  
(VDD=3.3V,CL=15pF,Ta=25)  
RBW:1kHz  
VBW:100Hz  
10kHz/div  
10nsec/div  
500psec/div  
Fig.31 78MHz output waveform  
Fig.32 78MHz Period-Jitter  
Fig.33 78MHz spectrum  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
(VDD=3.3V,CL=15pF,Ta=25)  
7/20  
Reference data (BU3071HFV Temperature and Supply voltage variations data)  
5
4
3
2
1
0
5
4
3
2
1
0
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
VDD=3.7V  
VDD=2.9V  
VDD=3.3V  
VDD=3.7V  
VDD=2.9V  
VDD=3.7V  
VDD=3.3V  
VDD=3.3V  
VDD=2.9V  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75 100  
-25  
0
25  
50  
75  
100  
temperature:T [  
]
temperature:T [  
Fig.35 54MHz  
]
temperature:T[  
Fig.34 54MHz  
]
Fig.36 54MHz  
Duty temperature characteristics  
Rise-time temperature characteristics  
Fall-time temperature characteristics  
100  
80  
60  
40  
20  
0
600  
500  
400  
300  
200  
100  
0
VDD=3.7V  
VDD=3.7V  
VDD=3.3V  
VDD=2.9V  
VDD=3.3V  
VDD=2.9V  
-25  
0
25  
50  
75 100  
-25  
0
25  
50  
75 100  
temperature:T [  
Fig.37 54MHz  
Period-Jitter 1σ temperature characteristics  
]
temperature:T [  
Fig.38 54MHz  
Jitter-MinMax temperature characteristics  
]
8/20  
Reference data (BU3072HFV Temperature and Supply voltage variations data)  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
5
4
3
2
1
0
5
4
3
2
1
0
VDD=3.7V  
VDD=3.3V  
VDD=2.9V  
VDD=3.7V  
VDD=2.9V  
VDD=3.7V  
VDD=2.9V  
VDD=3.3V  
VDD=3.3V  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75  
100  
temperature:T []  
temperature:T [  
]
temperature:T [  
]
Fig.39 27MHz  
Duty temperature characteristics  
Fig.40 27MHz  
Rise-time temperature characteristics  
Fig.41 27MHz  
Fall-time temperature characteristics  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
600  
500  
400  
300  
200  
100  
0
VDD=3.7V  
VDD=3.7V  
VDD=2.9V  
VDD=3.3V  
VDD=2.9V  
VDD=3.3V  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75 100  
temperature:T [  
]
temperature:T [  
Fig.42 27MHz  
Period-Jitter 1σ temperature characteristics  
]
Fig.43 27MHz  
Jitter-MinMax temperature characteristics  
5
4
3
55  
54  
53  
52  
5
4
51  
3
VDD=3.7V  
50  
VDD=3.3V  
49  
2
2
VDD=3.3V  
VDD=2.9V  
VDD=2.9V  
VDD=2.9V  
48  
VDD=3.3V  
47  
1
1
VDD=3.7V  
VDD=3.7V  
46  
45  
0
0
-25  
0
25  
50  
75 100  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75  
100  
temperature:T [  
]
temperature:T [  
Fig.44 36MHz  
Duty temperature characteristics  
]
temperature:T [  
Fig.45 36MHz  
Rise-time temperature characteristics  
]
Fig.46 36MHz  
Fall-time temperature characteristics  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
600  
500  
400  
300  
200  
100  
0
VDD=2.9V  
VDD=2.9V  
VDD=3.3V  
VDD=3.7V  
VDD=3.3V  
VDD=3.7V  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75  
100  
temperature:T [  
Fig.47 36MHz  
]
temperature:T [  
Fig.48 36MHz  
]
Period-Jitter 1σtemperature characteristics  
Jitter-MinMax temperature characteristics  
9/20  
Reference data (BU3073HFV Temperature and Supply voltage variations data)  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
5
4
3
2
1
0
5
4
3
2
1
0
VDD=3.7V  
VDD=2.9V  
VDD=3.7V  
VDD=2.9V  
VDD=3.7V  
VDD=3.3V  
VDD=2.9V  
VDD=3.3V  
VDD=3.3V  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75 100  
-25  
0
25  
50  
75  
100  
temperature:T [  
]
temperature:T [  
]
temperature:T [  
]
Fig.49 24.375MHz  
Duty temperature characteristics  
Fig.50 24.375MHz  
Rise-time temperature characteristics  
Fig.51 24.375MHz  
Fall-time temperature characteristics  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
600  
500  
400  
300  
200  
100  
0
VDD=3.7V  
VDD=3.7V  
VDD=2.9V  
VDD=3.3V  
VDD=2.9V  
VDD=3.3V  
-25  
0
25  
50  
75 100  
-25  
0
25  
50  
75  
100  
temperature:T [  
]
temperature:T [  
]
Fig.52 24.375MHz  
Fig.53 24.375MHz  
Jitter-MinMax temperature characteristics  
Period-Jitter 1σ temperature characteristics  
55  
54  
53  
52  
51  
5
4
3
5
4
3
2
1
0
VDD=3.7V  
50  
2
VDD=2.9V  
49  
48  
VDD=2.9V  
VDD=3.3V  
VDD=2.9V  
1
47  
46  
45  
VDD=3.3V  
VDD=3.7V  
VDD=3.3V  
VDD=3.7V  
0
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75  
100  
temperature:T [  
]
temperature:T []  
temperature:T [  
]
Fig.55 24.5454MHz  
Rise-time temperature characteristics  
Fig.56 24.5454MHz  
Fall-time temperature characteristics  
Fig.54 24.5454MHz  
Duty temperature characteristics  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
600  
500  
400  
300  
200  
100  
0
VDD=3.7V  
VDD=3.7V  
VDD=3.3V  
VDD=2.9V  
VDD=2.9V  
VDD=3.3V  
-25  
0
25  
50  
75 100  
-25  
0
25  
50  
75  
100  
temperature:T [  
]
temperature:T [  
]
Fig.58 24.5454MHz  
Jitter-MinMax temperature characteristics  
Fig.57 24.5454MHz  
Period-Jitter 1σ temperature characteristics  
10/20  
Reference data (BU3076HFV Temperature and Supply voltage variations data)  
5
4
3
2
1
0
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
5
4
3
2
1
0
VDD=3.7V  
VDD=2.9V  
VDD=2.9V  
VDD=3.3V  
VDD=3.3V  
VDD=3.7V  
VDD=2.9V  
VDD=3.7V  
VDD=3.3V  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75 100  
temperature:T [  
]
temperature:T [  
]
temperature:T [  
Fig.59 54MHz  
Duty temperature characteristics  
]
Fig.61 54MHz  
Fall-time temperature characteristics  
Fig.60 54MHz  
Rise-time temperature characteristics  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
600  
500  
400  
300  
200  
100  
0
VDD=2.9V  
VDD=2.9V  
VDD=3.7V  
VDD=3.3V  
VDD=3.7V  
VDD=3.3V  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75  
100  
temperature:T [  
]
temperature:T [  
Fig.62 54MHz  
]
Fig.63 54MHz  
Period-Jitter 1σ temperature characteristics  
Jitter-MinMax temperature characteristics  
55  
54  
53  
52  
51  
5
4
3
5
4
3
VDD=2.9V  
VDD=3.3V  
50  
VDD=3.7V  
VDD=2.9V  
VDD=3.3V  
VDD=3.3V  
2
2
49  
VDD=3.7V  
48  
47  
46  
1
1
VDD=3.7V  
VDD=2.9V  
0
0
45  
-25  
0
25  
50  
75  
]
100  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75 100  
temperature:T [  
]
temperature:T [  
temperature:T [  
Fig.64 67.5MHz  
]
Fig.65 67.5MHz  
Fig.66 67.5MHz  
Fall-time temperature characteristics  
Rise-time temperature characteristics  
Duty temperature characteristics  
70  
60  
50  
40  
30  
20  
10  
0
600  
500  
400  
300  
200  
100  
0
VDD=2.9V  
VDD=3.7V  
VDD=2.9V  
VDD=3.7V  
VDD=3.3V  
VDD=3.3V  
-25  
0
25  
50  
75 100  
-25  
0
25  
50  
75  
100  
temperature:T [  
]
temperature:T [  
]
Fig.67 67.5MHz  
Period-Jitter 1σtemperature characteristics  
Fig.68 67.5MHz  
Jitter-MinMax temperature characteristics  
11/20  
Reference data (BU7322HFV Temperature and Supply voltage variations data)  
5
4
3
2
1
0
5
4
3
2
1
0
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
VDD=2.75V  
VDD=2.75V  
VDD=3.7V  
VDD=3.3V  
VDD=3.7V  
VDD=3.3V  
VDD=3.7V  
VDD=3.3V  
VDD=2.75V  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75  
100  
temperature:T [  
]
temperature:T [  
]
temperature:T [  
]
Fig.69 49.5MHz  
Duty temperature characteristics  
Fig.70 49.5MHz  
Rise-time temperature characteristics  
Fig.71 49.5MHz  
Fall-time temperature characteristics  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
600  
500  
400  
300  
200  
100  
0
VDD=3.7V  
VDD=2.75V  
VDD=3.7V  
VDD=2.75V  
VDD=3.3V  
VDD=3.3V  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75  
100  
temperature:T [  
]
temperature:T [  
]
Fig.72 49.5MHz  
Period-Jitter 1σ temperature characteristics  
Fig.73 49.5MHz  
Jitter-MinMax temperature characteristics  
5
55  
54  
53  
5
VDD=2.75V  
4
3
2
1
0
4
3
2
1
0
52  
VDD=2.75V  
VDD=3.7V  
25  
VDD=3.7V  
VDD=3.3V  
51  
50  
49  
VDD=3.3V  
VDD=3.7V  
VDD=3.3V  
48  
VDD=2.75V  
47  
46  
45  
-25  
0
25  
50  
75  
100  
-25  
0
50  
75  
100  
-25  
0
25  
50  
75 100  
temperature:T [  
]
temperature:T [  
Fig.75 36MHz  
]
temperature:T [  
Fig.74 36MHz  
Duty temperature characteristics  
]
Fig.76 36MHz  
Fall-time temperature characteristics  
Rise-time temperature characteristics  
70  
60  
50  
40  
30  
20  
10  
0
600  
500  
400  
300  
200  
100  
0
VDD=2.75V  
VDD=2.75V  
VDD=3.7V  
VDD=3.7V  
VDD=3.3V  
VDD=3.3V  
-25  
0
25  
50  
75 100  
]
-25  
0
25  
50  
75  
]
100  
temperature:T [  
temperature:T [  
Fig.77 36MHz  
Period-Jitter 1σ temperature characteristics  
Fig.78 36MHz  
Jitter-MinMax temperature characteristics  
12/20  
Reference data (BU7325HFV Temperature and Supply voltage variations data)  
5
5
4
3
2
1
0
55  
54  
4
3
2
1
0
53  
52  
51  
50  
49  
48  
47  
46  
45  
VDD=3.7V  
VDD=3.7V  
VDD=2.75V  
VDD=3.3V  
VDD=3.3V  
VDD=2.75V  
VDD=2.75V  
VDD=3.3V  
VDD=3.7V  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75 100  
-25  
0
25  
50  
75  
100  
temperature:T [  
]
temperature:T []  
temperature:T [  
Fig.79 48MHz  
Duty temperature characteristics  
]
Fig.80 48MHz  
Rise-time temperature characteristics  
Fig.81 48MHz  
Fall-time temperature characteristics  
100  
600  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
500  
400  
300  
200  
100  
0
VDD=2.75V  
VDD=3.3V  
VDD=2.75V  
VDD=3.7V  
VDD=3.7V  
VDD=3.3V  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75  
100  
temperature:T [  
]
temperature:T [  
]
Fig.82 48MHz  
Fig.83 48MHz  
Jitter-MinMax temperature characteristics  
5
Period-Jitter 1σ temperature characteristics  
55  
54  
53  
52  
51  
50  
5
4
3
4
3
VDD=2.75V  
VDD=3.7V  
VDD=2.75V  
2
1
2
49  
48  
47  
VDD=3.3V  
VDD=3.7V  
1
VDD=3.7V  
VDD=3.3V  
46  
VDD=3.3V  
VDD=2.75V  
0
0
45  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75  
100  
-25  
0
25  
50  
75 100  
temperature:T [  
]
temperature:T [  
]
temperature:T [  
]
Fig.84 78MHz  
Duty temperature characteristics  
Fig.85 78MHz  
Rise-time temperature characteristics  
Fig.86 78MHz  
Fall-time temperature characteristics  
600  
500  
400  
300  
70  
60  
50  
40  
30  
20  
10  
0
VDD=2.75V  
VDD=3.3V  
VDD=2.75V  
VDD=3.3V  
200  
100  
VDD=3.7V  
VDD=3.7V  
0
-25  
0
25  
50  
75 100  
-25  
0
25  
50  
75  
100  
temperature:T [  
]
temperature:T [  
Fig.88 78MHz  
]
Fig.87 78MHz  
Period-Jitter 1σ temperature characteristics  
Jitter-MinMax temperature characteristics  
13/20  
Block diagram, pin assignment/functions  
BU3071HFV)  
1 VDD  
IN  
ꢀ6:  
ꢀ5:  
ꢀ4:  
6pin:IN  
PLL  
3pin:OUT  
1/4  
2 VSS  
TEST  
OE  
3 OUT  
4pin:OE  
Fig.89  
Fig.90  
PIN NO.  
PIN name  
VDD  
VSS  
Function  
1
2
3
4
5
6
Power supply  
GND  
OUT  
OE  
Clock output terminal  
Output enable (L: disable, H: enable), equipped with Pull-down function, output fixed to L at disable  
TEST pin, equipped with Pull-down function  
TEST  
IN  
Clock input pin (28.6363 MHz input)  
BU3072HFV)  
PLL  
6pin:IN  
3pin:OUT  
1/4  
1 VDD  
IN  
ꢀ6:  
ꢀ5:  
DATA1  
DATA2  
2 VSS  
SEL  
3 OUT  
ꢀ4:PD  
5pin:SEL  
4pin:PD  
Fig.91  
Fig.92  
PIN NO.  
PIN name  
VDD  
VSS  
OUT  
PD  
Function  
1
2
3
4
5
6
Power supply  
GND  
Clock output terminal (L27.0000MHz, H36.0000MHz)  
Power-down (L: Hi-Z, H: enable), equipped with Pull-down function, output set to Hi-Z at disable  
Output selection (L: 27.0000 MHz, H: 36.0000 MHz)  
SEL  
IN  
Clock input pin (48.0000 MHz input)  
BU3073HFV)  
PLL  
1/8  
3pin:OUT  
6pin:IN  
1 VDD  
IN  
ꢀ6:  
ꢀ5:  
DATA1  
DATA2  
2 VSS  
SEL  
3 OUT  
ꢀ4:PD  
5pin:SEL  
4pin:PD  
Fig.93  
Fig.94  
PIN NO.  
PIN name  
VDD  
VSS  
OUT  
PD  
Function  
1
2
3
4
5
6
Power supply  
GND  
Clock output terminal (L24.3750MHz, H24.5454MHz)  
Power-down (L: disable, H: enable), equipped with Pull-down function, output set to L at disable  
Output selection (L24.3750MHz, H24.5454MHz)  
SEL  
IN  
Clock input pin (48.0000MHz input)  
14/20  
BU3076HFV)  
PLL  
1/4  
3pin:OUT  
6pin:IN  
DATA1  
DATA2  
1:VDD  
2:VSS  
3:OUT  
6:IN  
5
4
SEL  
OE  
5pin:SEL  
4pin:OE  
Fig.95  
Fig.96  
PIN NO.  
PIN name  
VDD  
VSS  
OUT  
OE  
Function  
1
2
3
4
5
6
Power supply  
GND  
Clock output terminal (L54.0000MHz, H67.5000MHz)  
Power-down (L: disable, H: enable), equipped with Pull-down function, output set to L at disable  
Output selection (L54.0000MHz, H67.5000MHz)  
SEL  
IN  
Clock input pin (27.0000MHz input)  
BU7322HFV)  
PLL  
1/6  
1/8  
6pin:IN  
3pin:OUT  
1:VDD  
2:VSS  
3:OUT  
6:IN  
DATA1  
DATA2  
5
4
SEL  
OE  
5pin:SEL  
4pin:OE  
Fig.97  
Fig.98  
PIN NO.  
PIN name  
VDD  
VSS  
OUT  
OE  
Function  
1
2
3
4
5
6
Power supply  
GND  
Clock output terminal (L49.5000MHz, H36.0000MHz)  
Power-down (Ldisable ,Henable) equipped with Pull-down function, disable output set to L at disable  
Output selection (L49.5000MHz, H36.0000MHz) equipped with Pull-down function  
Clock input pin (27.0000MHz input)  
SEL  
IN  
BU7325HFV)  
PLL  
1/6  
1/4  
6pin:IN  
3pin:OUT  
1:VDD  
2:VSS  
3:OUT  
6:IN  
DATA1  
DATA2  
5
4
SEL  
OE  
5pin:SEL  
4pin:OE  
Fig.99  
Fig.100  
PIN NO.  
PIN name  
VDD  
VSS  
OUT  
OE  
Function  
1
2
3
4
5
6
Power supply  
GND  
Clock output terminal (L48.0000MHz, H78.0000MHz)  
Power-down (Ldisable ,Henable) equipped with Pull-down function, disable output set to L at disable  
Output selection (L48.0000MHz, H78.0000MHz)  
SEL  
IN  
Clock input pin (27.0000MHz input)  
15/20  
Application circuit example  
BU3071HFV)  
BU3072HFV)  
48MHz  
1VDD  
2VSS  
6:IN  
28.6363MHz  
1
VDD  
6
IN  
5SEL  
PD  
H:36.0000MHz  
5:TEST  
2VSS  
OUT  
H:enable  
L:disable  
L:27.0000MHz  
H:enable  
H:36.0000MHz  
L:27.0000MHz  
3
OUT  
OE  
4:  
3
4
54.0000MHz  
L:Hi-Z  
Fig.101  
Fig.102  
BU3073HFV)  
BU3076HFV)  
27MHz  
48MHz  
1:VDD  
2: VSS  
3: OUT  
6: IN  
1
2
3
VDD  
VSS  
OUT  
6
5
4
IN  
H:67.5000MHz  
H:24.5454MHz  
5: SEL  
4: OE  
SEL  
PD  
L:54.0000MHz  
L:24.3750MHz  
H:enable  
H:67.5000MHz  
L:54.00000MHz  
H:24.5454MHz  
L:24.3750MHz  
H:enable  
L:disable  
L:disable  
Fig.104  
Fig.103  
BU7322HFV)  
BU7325HFV)  
27MHz  
27MHz  
1:VDD  
2: VSS  
6: IN  
1:VDD  
6: IN  
H:36.0000MHz  
H:78.0000MHz  
2: VSS  
3: OUT  
5: SEL  
4: OE  
5: SEL  
4: OE  
L:49.5000MHz  
L:48.0000MHz  
H:enable  
H:36.0000MHz  
L:49.5000MHz  
H:78.0000MHz  
L:48.0000MHz  
3: OUT  
H:enable  
L:disable  
L:disable  
Fig.106  
Fig.105  
For VDD and VSS, insert a bypass capacitor of approx. 0.1 F as close as possible to the pin.  
Bypass capacitors with good high-frequency characteristics are recommended.  
Even though we believe that the typical application circuit is worth of a recommendation, please be sure to thoroughly  
recheck the characteristics before use.  
16/20  
Equivalent circuit  
3-pin (Output pin)  
From the inside of IC  
From the inside of IC  
PD=L ; Hi-Z  
; enable  
Fig.107  
Fig.108  
BU3071HFV, BU3073HFV, BU3076HFV  
BU7322HFV, BU7325HFV  
BU3072HFV  
4-pin (Input pin)  
To the inside of IC  
Fig.109  
5-pin (Input pin)  
To the inside of IC  
To the inside of IC  
Fig.110  
Fig.111  
BU3072HFV, BU3073HFV, BU3076HFV  
BU7322HFV, BU7325HFV  
BU3071HFV  
6-pin (Input pin)  
From the inside of IC  
To the inside of IC  
To the inside  
of IC  
To the inside of IC  
To the inside  
of IC  
Fig.112  
Fig.113  
BU3072HFV, BU3073HFV, BU3076HFV  
BU7322HFV, BU7325HFV  
BU3071HFV  
17/20  
Appearance of Marker  
(Dimension including burr: Max. 1.8)  
1.6±0.1  
Marker  
○ ○  
(1.2)  
(1.4)  
LOT No.  
0.145±0.05  
0.5  
0.22±0.05  
(UNITmm)  
Fig.114  
List of markers  
Model name  
Marker  
AB  
BU3071HFV  
BU3072HFV  
BU3073HFV  
BU3076HFV  
BU7322HFV  
BU7325HFV  
AC  
AD  
AA  
AE  
AH  
18/20  
Cautions on use  
(1) Absolute Maximum Ratings  
An excess in the absolute maximum ratings, such as applied voltage (VDD or VIN), operating temperature range (Topr),  
etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit.  
If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take  
physical safety measures including the use of fuses, etc.  
(2) Recommended operating conditions  
These conditions represent a range within which characteristics can be provided approximately as expected. The  
electrical characteristics are guaranteed under the conditions of each parameter.  
(3) Reverse connection of power supply connector  
The reverse connection of power supply connector can break down ICs. Take protective measures against the  
breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC’s  
power supply terminal.  
(4) Power supply line  
Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.  
In this regard, for the digital block power supply and the analog block power supply, even though these power supplies  
has the same level of potential, separate the power supply pattern for the digital block from that for the analog block,  
thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to  
the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner.  
Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal.  
At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the  
capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus  
determining the constant.  
(5) GND voltage  
Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state.  
Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric  
transient.  
(6) Short circuit between terminals and erroneous mounting  
In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting  
can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or  
between the terminal and the power supply or the GND terminal, the ICs can break down.  
(7) Operation in strong electromagnetic field  
Be noted that using ICs in the strong electromagnetic field can malfunction them.  
(8) Inspection with set PCB  
On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress.  
Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set  
PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the  
jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In  
addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention  
to the transportation and the storage of the set PCB.  
(9) Input terminals  
In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the  
parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of  
the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input  
terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not  
apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power  
supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the  
guaranteed value of electrical characteristics.  
(10) Ground wiring pattern  
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND  
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that  
resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of  
the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.  
(11) External capacitor  
In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a  
degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc.  
19/20  
Product Designation  
-
B
U
3
0
7
1
H
F
V
T
R
Package and forming specification  
TR: Embossed tape and reel  
Part No.  
Package Type  
Type  
3071  
HFVHVSOF6  
3072  
3073  
3076  
7322  
7325  
HVSOF6  
<Dimension>  
<Tape and Reel information>  
Tape  
Embossed carrier tape  
(MAX 1.8 include BURR)  
1.6 0.1  
Quantity  
3000pcs  
6
5
4
TR  
Direction  
of feed  
(The direction is the 1pin of product is at the upper light when you hold  
reel on the left hand and you pull out the tape on the right hand)  
(1.2)  
(1.4)  
1
2
3
0.145 0.05  
S
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0.1 S  
0.22 0.05  
0.5  
Direction of feed  
1Pin  
Reel  
(Unit:mm)  
When you order , please order in times the amount of package quantity.  
Catalog No.08T800A '08.9 ROHM ©  
Appendix  
Notes  
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM  
CO.,LTD.  
The content specified herein is subject to change for improvement without notice.  
The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you  
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM  
upon request.  
Examples of application circuits, circuit constants and any other information contained herein illustrate the  
standard usage and operations of the Products. The peripheral conditions must be taken into account  
when designing circuits for mass production.  
Great care was taken in ensuring the accuracy of the information specified in this document. However, should  
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no re-  
sponsibility for such damage.  
The technical information specified herein is intended only to show the typical functions of and examples  
of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to  
use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no re-  
sponsibility whatsoever for any dispute arising from the use of such technical information.  
The Products specified in this document are intended to be used with general-use electronic equipment  
or devices (such as audio visual equipment, office-automation equipment, communication devices, elec-  
tronic appliances and amusement devices).  
The Products are not designed to be radiation tolerant.  
While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or  
malfunction for a variety of reasons.  
Please be sure to implement in your equipment using the Products safety measures to guard against the  
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as  
derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your  
use of any Product outside of the prescribed scope or not in accordance with the instruction manual.  
The Products are not designed or manufactured to be used with any equipment, device or system  
which requires an extremely high level of reliability the failure or malfunction of which may result in a direct  
threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment,  
aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear  
no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intend-  
ed to be used for any such special purpose, please contact a ROHM sales representative before purchasing.  
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under  
the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.  
Thank you for your accessing to ROHM product informations.  
More detail product informations and catalogs are available, please contact your nearest sales office.  
THE AMERICAS / EUROPE / ASIA / JAPAN  
ROHM Customer Support System  
Contact us : webmaster@ rohm.co.jp  
www.rohm.com  
TEL : +81-75-311-2121  
FAX : +81-75-315-0172  
Copyright © 2009 ROHM CO.,LTD.  
21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan  
Appendix-Rev4.0  
配单直通车
BU3071HFV-TR产品参数
型号:BU3071HFV-TR
是否Rohs认证:符合
生命周期:Obsolete
IHS 制造商:ROHM CO LTD
零件包装代码:SOIC
包装说明:HVSSOF, TSSOP6,.11,20
针数:6
Reach Compliance Code:compliant
ECCN代码:EAR99
HTS代码:8542.39.00.01
风险等级:5.8
Is Samacsys:N
JESD-30 代码:R-PDSO-F6
长度:2.6 mm
端子数量:6
最高工作温度:70 °C
最低工作温度:-5 °C
最大输出时钟频率:54 MHz
封装主体材料:PLASTIC/EPOXY
封装代码:HVSSOF
封装等效代码:TSSOP6,.11,20
封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V
主时钟/晶体标称频率:28.636363 MHz
认证状态:Not Qualified
座面最大高度:0.75 mm
子类别:Clock Generators
最大压摆率:15 mA
最大供电电压:3.6 V
最小供电电压:3 V
标称供电电压:3.3 V
表面贴装:YES
技术:CMOS
温度等级:COMMERCIAL
端子形式:FLAT
端子节距:0.5 mm
端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.6 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1
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