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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Overview

KEMET’s C0G dielectric features a 125°C maximum operating

temperature and is considered “stable.” The Electronics

temperature. Capacitance change is limited to ±30ppm/ºC from

-55°C to +125°C.

Components, Assemblies & Materials Association (EIA)

characterizes C0G dielectric as a Class I material. Components

of this classiﬁcation are temperature compensating and are suited

for resonant circuit applications or those where Q and stability of

capacitance characteristics are required. C0G exhibits no change

in capacitance with respect to time and voltage and boasts a

negligible change in capacitance with reference to ambient

Beneﬁts

• Negligible capacitance change with respect to temperature from

-55°C to +125°C

• No capacitance decay with time

• Non-polar device, minimizing installation concerns

• 100% pure matte tin-plated termination ﬁnish allowing for

excellent solderability

• -55°C to +125°C operating temperature range

• RoHS compliant

• EIA 0201, 0402, 0603, 0805, 1206, 1210, 1808, 1812, 1825,

2220 and 2225 case sizes

• DC voltage ratings of 10V, 16V, 25V, 50V,100V and 200V

• Capacitance offerings ranging from 0.5pF up to 0.47μF

• Available capacitance tolerances of ±0.25pF, ±0.5pF, ±1%,

±2%, ±5%, ±10% and ±20%

• SnPb plated termination ﬁnish option available upon request (5% min)

Applications

• No piezoelectric noise

• Extremely low ESR and ESL

• High thermal stability

• High ripple current capability

• Preferred capacitance solution at line frequencies and into the

MHz range

Typical applications include critical timing, tuning, circuits requiring

low loss, circuits with pulse, high current, decoupling, bypass,

ﬁltering, transient voltage suppression, blocking and energy

storage.

• No capacitance change with respect to applied rated DC voltage

Ordering Information

C

1206

C

104

J

3

G

A

C

TU

Case Size Speciﬁcation/

Capacitance

Code (pF)

Capacitance

Tolerance¹

Failure Rate/

Design

Packaging/Grade

(C-Spec)³

Ceramic

Voltage

Dielectric

G = C0G

Termination Finish²

(L" x W")

Series

0201

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

C = Standard

2 Sig. Digits +

Number of Zeros

Use 9 for

1.0 - 9.9pF

Use 8 for

0.5 - .99pF

ex. 2.2pF = 229

ex. 0.5pF = 508

C = ±0.25pF 8 = 10V

A = N/A

C = 100% Matte Sn Blank = Bulk

TU = 7" Reel

D = ±0.5pF

F = ± 1%

G = ±2%

J = ±5%

K = ±10%

M = ±20%

4 = 16V

3 = 25V

5 = 50V

1 = 100V

2 = 200V

Unmarked

¹Additional capacitance tolerance offerings may be available. Contact KEMET for details.

²Additional termination ﬁnish options may be available. Contact KEMET for details.

³Additional reeling or packaging options may be available. Contact KEMET for details.

One WORLD

One Brand

One Strategy

One Focus

One Team

One KEMET

C1003_C0G • 8/10/2011

1

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

100% Tin or SnPb Plate

L

Dimensions – Millimeters (Inches)

W

B

T

Nickel Plate

S

Conductive Metalization

Electrodes

EIA

Size

Code

0201

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

Metric

Size

Code

0603

1005

1608

2012

S

L

W

Width

T

B

Mounting

Technique

Separation

Min.

Length

Thickness

Bandwidth

0.60 (.024) ± 0.03 (.001) 0.30 (.012) ± 0.03 (.001)

1.00 (.040) ± 0.05 (.002) 0.50 (.020) ± 0.05 (.002)

1.60 (.063) ± 0.15 (.006) 0.80 (.032) ± 0.15 (.006)

2.00 (.079) ± 0.20 (.008) 1.25 (.049) ± 0.20 (.008)

3.20 (.126) ± 0.20 (.008) 1.60 (.063) ± 0.20 (.008)

3.20 (.126) ± 0.20 (.008) 2.50 (.098) ± 0.20 (.008)

4.70 (.185) ± 0.50 (.020) 2.00 (.079) ± 0.20 (.008)

4.50 (.177) ± 0.30 (.012) 3.20 (.126) ± 0.30 (.012)

4.50 (.177) ± 0.30 (.012) 6.40 (.252) ± 0.40 (.016)

5.70 (.224) ± 0.40 (.016) 5.00 (.197) ± 0.40 (.016)

5.60 (.220) ± 0.40 (.016) 6.40 (.248) ± 0.40 (.016)

0.15 (.006) ± 0.05 (.002)

0.30 (.012) ± 0.10 (.004)

0.35 (.014) ± 0.15 (.006)

0.50 (0.02) ± 0.25 (.010)

0.60 (.024) ± 0.35 (.014)

N/A

Solder Reﬂow Only

0.30 (.012)

0.70 (.028)

0.75 (.030)

Solder Wave or

Solder Reﬂow

3216

3225

4520

4532

4564

5650

5664

N/A

Solder Reﬂow Only

Qualiﬁcation/Certiﬁcation

Commercial grade products are subject to internal qualiﬁcation. Details regarding test methods and conditions are referenced in Table

4, Performance and Reliability.

Environmental Compliance

RoHS compliant

C1003_C0G • 8/10/2011

2

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Electrical Parameters/Characteristics

Item

Parameters/Characteristics

Operating Temperature Range

-55°C to +125°C

±30PPM/ºC

0%

Capacitance Change with Reference to +25°C and 0 Vdc Applied (TCC)

Aging Rate (Max % Cap Loss/Decade Hour)

250% of rated voltage

(5 ± 1 seconds and charge/discharge not exceeding 50mA)

Dielectric Withstanding Voltage

Dissipation Factor (DF) Maximum Limit @ 25ºC

0.1%

1000 megohm microfarads or 100GΩ

(Rated voltage applied for 120 ± 5 secs @ 25°C)

Insulation Resistance (IR) Limit @ 25°C

To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.

Capacitance and Dissipation Factor (DF) measured under the following conditions:

1MHz ± 100kHz and 1.0Vrms ± 0.2V if capacitance ≤1000pF

1kHz ± 50Hz and 1.0Vrms ± 0.2V if capacitance >1000pF

Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 & Agilent E4980 have a feature known as Automatic

Level Control (ALC). The ALC feature should be switched to "ON".

Post Environmental Limits

High Temperature Life, Biased Humidity, Moisture Resistance

Dielectric

C0G

Rated DC Voltage Capacitance Value

All All

DF (%)

0.5

Cap Shift

IR

0.3% or ± 0.25 pF

10% of Initial Limit

C1003_C0G • 8/10/2011

3

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Table 1A – (0201 - 1206 Case Sizes)

Series

Voltage Code

Voltage DC

C0201

C0402

C0603

C0805

C1206

Cap

Code

8

4

3

8

4

3

5

1

2

8

4

3

5

1

2

8

4

3

5

1

2

8

4

3

5

1

2

Cap

Cap Tolerance

Product Availability and Chip Thickness Codes - See Table 2 for Chip Thickness Dimensions

0.50-0.75 pF 508-758

1.0-2.4 pF 109-249

C

D

BB BB BB BB

CB CB CB CB CB CB DC DC DC DC DC DC

D

CB CB CB CB CB CB DC DC DC DC DC DC EB EB EB EB EB EB

2.7-5.1 pF

5.6 pF

6.2 pF

6.8 pF

7.5 pF

8.2 pF

9.1 pF

10 pF

11 pF

12 pF

13 pF

15 pF

16 pF

18 pF

20 pF

22 pF

24 pF

27 pF

30 pF

33 pF

36 pF

39 pF

43 pF

47 pF

51 pF

56 pF

62 pF

68 pF

75 pF

82 pF

91 pF

100 pF

279

569

629

689

759

829

919

100

110

120

130

150

160

180

200

220

240

270

300

330

360

390

430

470

510

560

620

680

750

820

910

101

K

M

J

AB¹ AB¹ AB¹ BB BB BB BB

BB BB BB BB

AB² AB² AB² BB BB BB BB

BB BB BB BB

AB² AB² AB² BB BB BB BB

BB BB BB BB

AB² AB² AB² BB BB BB BB

BB BB BB BB

AB² AB² AB² BB BB BB BB

BB BB BB BB

AB² AB² AB² BB BB BB BB

BB BB BB BB

AB² AB² AB² BB BB BB BB

BB BB BB BB

AB² AB² AB² BB BB BB BB

BB BB BB BB

AB² AB² AB² BB BB BB BB

BB BB BB BB

AB² AB² AB² BB BB BB BB

BB BB BB BB

AB² AB² AB² BB BB BB BB

BB BB BB BB

AB² AB² AB² BB BB BB BB

BB BB BB BB

G

F

AB² AB² AB² BB BB BB BB BB

BB BB BB BB BB

BB BB BB BB

UD

110-180 pF 111-181

200-330 pF 201-331

360-430 pF 361-431

CB CB CB CB CB

DC DC DC DC DC DC EB EB EB EB EB EB

DC DC DC DC DC DD EB EB EB EB EB EB

DC DC DC DC DC DC EB EB EB EB EB EB

DC DC DC DC DD DD EB EB EB EB EB EB

UD

470 pF

510 pF

560 pF

471

511

561

620-820 pF 621-821

910 pF

911

102

112

122

132

1,000 pF

1,100 pF

1,200 pF

1,300 pF

1,500 pF

1,600 pF

1,800 pF

2,000 pF

2,200 pF

2,400 pF

2,700 pF

3,000 pF

DC DC DC DC DC

DD DD DD DD DD

EB EB EB EB EB EB

UD

C

1206

C

104

J

3

G

A

C

TU

K

BB BB BB BB

CB CB CB CB CB

BB BB BB BB

EB EB EB EB EC EC

Case Size Speciﬁcation/

Capacitance

Tolerance¹

Failure Rate/

Packaging/Grade

2

152

F

G

J

M

BB BB BB BB

CB CB CB CB CB

DD DD DD DD DD

EB EB EB EB ED EC

Ceramic

162

Voltage

Dielectric

Termination Finish

UD

(L" x W")

Series

Code (pF)

Design

(C-Spec)³

K

BB BB BB

CB CB CB CB CB

DD DD DD DD DD

DD DD DD DD DD EB EB EB EB ED ED

UD

C = 100% Matte Sn Blank = Bulk

EB EB EB EB ED ED

UD

182

202

222

242

272

302

0201

0402

0603

0805

1206

1210

1808

1812

1825

C = Standard

2 Sig. Digits +

C = ±0.25pF 8 = 10V

G = C0G

A = N/A

K

BB BB BB

CB CB CB CB CB

4 = 16V

DC DC DC DC DC

DD DD DD DD DC

EB EB EB EB ED ED

UD

Number of Zeros

D = ±0.5pF

F = ± 1%

G = ±2%

J = ±5%

TU = 7" Reel

BB BB BB

CB CB CB CB CB

3 = 25V

EB EB EB EB EE EE

Use 9 for

Unmarked

CB CB CB CB CB

5 = 50V

EB EB EB EB EC EC

1.0 - 9.9pF

Use 8 for

CB CB CB CB CB

1 = 100V

CB CB CB CB CB

2 = 200V

EC EC EC EC EC

UD

0.5 - .99pF

ex. 2.2pF = 229

K = ±10%

M = ±20%

Voltage DC

Cap

Code

ex. 0.5pF = 508

Voltage Code

8

4

3

8

4

3

5

1

2

8

4

3

5

1

2

8

4

3

5

1

2

8

4

3

5

1

2

Cap

Series

C0201

C0402

C0603

C0805

C1206

2220

2225

UD = Under Development

xx¹ Available only in K,M tolerance

xx² Available only in M tolerance.

These products are protected under US Patents 7,172,985 & 7,670,981, other patents pending, and any foreign counterparts.

C1003_C0G • 8/10/2011

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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Table 1A – (0201 - 1206 Case Sizes) con't

Series

Voltage Code

Voltage DC

C0201

C0402

C0603

C0805

C1206

Cap

Code

8

4

3

8

4

3

5

1

2

8

4

3

5

1

2

8

4

3

5

1

2

8

4

3

5

1

2

Cap

Cap Tolerance

Product Availability and Chip Thickness Codes - See Table 2 for Chip Thickness Dimensions

3,300 pF

3,600 pF

3,900 pF

4,300 pF

4,700 pF

5,100 pF

5,600 pF

6,200 pF

6,800 pF

7,500 pF

8,200 pF

9,100 pF

10,000 pF

12,000 pF

15,000 pF

18,000 pF

22,000 pF

27,000 pF

33,000 pF

39,000 pF

47,000 pF

56,000 pF

68,000 pF

82,000 pF

0.10 µF

332

362

392

432

472

512

562

622

682

752

822

912

103

123

153

183

223

273

333

393

473

563

683

823

104

F

G

J

K

M

CB CB CB CB CB

CB CB CB CB

CB CB CB

DD DD DD DD DC

DE DE DE DE DC

DC DC DC DC DC

DC DC DC DC DD

DC DC DC DC DE

DC DC DC DD DG

DC DC DC DD

EC EC EC EC EE

EC EC EC EC EF

EC EC EC EC EC

ED ED ED ED ED

EB EB EB EB EB

EC EC EC EC EB

ED ED ED ED EB

EB EB EB EB EB

EB EB EB EB EC

EB EB EB EB EE

EC EC EC EE EH

ED ED ED EF

UD

CB CB CB

DD DD DD DF

DF DF DF

DG DG DG

EF EF EF EH

EH EH EH EH

EH EH EH

Voltage DC

Cap

Code

Voltage Code

8

4

3

8

4

3

5

1

2

8

4

3

5

1

2

8

4

3

5

1

2

8

4

3

5

1

2

Cap

Series

C0201

C0402

C0603

C0805

C1206

Table 1B – (1210 - 2225 Case Sizes)

Series

C1210

C1808

C1812

C1825

C2220

C2225

Cap

Code

Voltage Code

8

4

3

5

1

2

5

1

2

5

1

2

5

1

2

3

1

2

5

1

2

Cap

Voltage DC

Cap Tolerance

Product Availability and Chip Thickness Codes See Table 2 for Chip Thickness Dimensions

0.5-0.75 pF 508-758

1.0-2.4 pF 109-249

2.7-9.1 pF 279-919

D

M

FB

K

10-13 pF 100-130

D

J

K

C

1206

C

104

J

3

G

A

C

TU

15-24 pF 150-240

D

G

K

Case Size Speciﬁcation/

Capacitance

Failure Rate/

Design

Packaging/Grade

(C-Spec)³

27-51 pF 270-510

D

F

G

K

M

FB

Ceramic

Voltage

Dielectric

G = C0G

Termination Finish²

1

FB

56-82 pF 560-820

(L" x W")

F

0201

0402

0603

0805

1206

Series

Code (pF)

Tolerance

91-200 pF 910-201

220-300 pF 221-301

330-430 pF 331-431

470-910 pF 471-911

M

FB

FC

FE

C = Standard

2 Sig. Digits +

C = ±0.25pF 8 = 10V

A = N/A

C = 100% Matte Sn Blank = Bulk

TU = 7" Reel

F

K

M

FB

Number of Zeros

D = ±0.5pF

4 = 16V

FB

LF LF

LF

Use 9 for

F = ± 1%

3 = 25V

Unmarked

FB

LF

GB

1,000 pF

1,100 pF

1,200 pF

1,300 pF

1,500 pF

102

112

122

132

152

LF

GB

1.0 - 9.9pF

G = ±2%

5 = 50V

FB

LF

Use 8 for

J = ±5%

1 = 100V

FB

LF

1210

0.5 - .99pF

K = ±10%

2 = 200V

F

1808

F

FB

LF

ex. 2.2pF = 229

M = ±20%

FB

1812

ex. 0.5pF = 508

Voltage DC

1825

2220

2225

Cap

Code

Voltage Code

8

4

3

5

1

2

5

1

2

5

1

2

5

1

2

3

1

2

5

1

2

Cap

Series

C1210

C1808

C1812

C1825

C2220

C2225

UD = Under Development

These products are protected under US Patents 7,172,985 & 7,670,981, other patents pending, and any foreign counterparts.

C1003_C0G • 8/10/2011

5

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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Table 1B – (1210 - 2225 Case Sizes) con't

Series

C1210

C1808

C1812

C1825

C2220

C2225

Cap

Code

Voltage Code

8

4

3

5

1

2

5

1

2

5

1

2

5

1

2

3

1

2

5

1

2

Cap

Voltage DC

Cap Tolerance

Product Availability and Chip Thickness Codes See Table 2 for Chip Thickness Dimensions

1,600 pF

1,800 pF

2,000 pF

2,200 pF

2,400 pF

2,700 pF

3,000 pF

3,300 pF

3,600 pF

3,900 pF

4,300 pF

4,700 pF

5,100 pF

5,600 pF

6,200 pF

6,800 pF

7,500 pF

8,200 pF

9,100 pF

10,000 pF

12,000 pF

15,000 pF

18,000 pF

22,000 pF

27,000 pF

33,000 pF

39,000 pF

47,000 pF

56,000 pF

68,000 pF

82,000 pF

0.10 µF

162

182

202

222

242

272

302

332

362

392

432

472

512

562

622

682

752

822

912

103

123

153

183

223

273

333

393

473

563

683

823

104

124

154

184

224

274

334

474

564

684

824

105

F

G

J

K

M

FB

FF

FB

FC

FE

FF

FG

FB

FC

FE

FG

FH

FJ

FB

FF

FB

FC

FE

FF

FG

FB

FC

FE

FG

FH

FJ

FB

FF

FB

FC

FE

FF

FG

FB

FC

FE

FG

FH

FJ

FB

FF

FB

FC

FE

FF

FG

FB

FC

FF

FG

FH

FM

FB

FC

FF

FG

FC

FE

FF

FB

FE

FF

FG

FH

FM

FE

FG

FC

FF

FG

LF

GB

HB

GB GD

GB GH

KE

FG

UD

GB

GJ

JB

UD

GB GH

UD

GB GH

GB GG

HB

HE

HG

HE

JB

JD

JG

JB

JD

JF

JG

UD

GB

GB GD

GB GH

GD GN

GH

0.12 µF

0.15 µF

0.18 µF

0.22 µF

0.27 µF

0.33 µF

0.47 µF

0.56 µF

FK

GK

0.68 µF

0.82 µF

1.0 µF

Voltage DC

Voltage Code

Cap

C

8

4

3

5

1

2

5

1

2

5

G

1

2

5

1

2

3

1

2

5

1

2

Cap

1206

C

104

J

3

A

C

TU

Code

Series

Case Size Speciﬁcation/

C1210

C1808

Voltage

C1812

C1825

C2220

C2225

Capacitance

Tolerance¹

Failure Rate/

Design

Packaging/Grade

(C-Spec)³

Ceramic

Dielectric

Termination Finish²

(L" x W")

Series

Code (pF)

UD = Under Development

0201

C = Standard

2 Sig. Digits +

Number of Zeros

Use 9 for

1.0 - 9.9pF

Use 8 for

0.5 - .99pF

ex. 2.2pF = 229

ex. 0.5pF = 508

C = ±0.25pF 8 = 10V

G = C0G

A = N/A

C = 100% Matte Sn Blank = Bulk

These products are protected under US Patents 7,172,985 & 7,670,981, other patents pending, and any foreign counterparts.

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

D = ±0.5pF

F = ± 1%

G = ±2%

J = ±5%

K = ±10%

M = ±20%

4 = 16V

3 = 25V

5 = 50V

1 = 100V

2 = 200V

TU = 7" Reel

Unmarked

C1003_C0G • 8/10/2011

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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Table 2 – Chip Thickness/Packaging Quantities

Thickness

Code

Chip

Size

Thickness ±

Range (mm)

QTY per Reel QTY per Reel QTY per Reel QTY per Reel QTY per Bulk

7" Plastic

13" Plastic

7" Paper

15000

10000

13" Paper

Cassette

AA

AB

BB

BC

PA

CB

CC

CD

MA

DB

DC

DD

DL

1005

0201

0402

0508

0603

0612

0805

1206

1210

1220

1632

1706

1808

1812

1825

Chip

0.20 ± 0.02

0.30 ± 0.03

0.50 ± 0.05

0.50 ± 0.10

0.80 ± 0.10

0.80 ± 0.07

0.80 ± 0.10

0.80 ± 0.15

0.80 ± 0.10

0.60 ± 0.10

0.78 ± 0.10

0.90 ± 0.10

0.95 ± 0.10

1.00 ± 0.10

1.10 ± 0.10

1.25 ± 0.15

1.25 ± 0.20

0.78 ± 0.10

0.80 ± 0.10

0.90 ± 0.10

0.95 ± 0.10

1.00 ± 0.10

1.10 ± 0.10

1.20 ± 0.15

1.25 ± 0.15

1.60 ± 0.15

1.60 ± 0.20

1.70 ± 0.20

0.78 ± 0.10

0.90 ± 0.10

0.95 ± 0.10

1.00 ± 0.10

1.10 ± 0.10

1.25 ± 0.15

1.40 ± 0.15

1.50 ± 0.20

1.55 ± 0.15

1.60 ± 0.20

1.70 ± 0.20

1.85 ± 0.20

1.90 ± 0.20

2.10 ± 0.20

2.25 ± 0.20

2.50 ± 0.20

3.35 ± 0.10

6.15 ± 0.15

0.80 ± 0.10

0.90 ± 0.10

1.00 ± 0.10

1.00 ± 0.15

0.90 ± 0.10

1.00 ± 0.10

1.00 ± 0.15

1.40 ± 0.15

1.60 ± 0.15

2.00 ± 0.15

1.00 ± 0.10

1.10 ± 0.10

1.25 ± 0.15

1.30 ± 0.10

1.40 ± 0.15

1.50 ± 0.10

1.55 ± 0.10

1.60 ± 0.20

1.70 ± 0.15

1.70 ± 0.20

1.90 ± 0.20

2.00 ± 0.20

2.50 ± 0.20

2.65 ± 0.35

5.00 ± 0.50

1.10 ± 0.15

1.15 ± 0.15

1.30 ± 0.15

1.40 ± 0.15

1.50 ± 0.15

Thickness ±

50000

4000

10000

4000

10000

15000

4000

10000

15000

4000

2500

4000

2000

4000

2500

2000

4000

2500

2000

1500

2000

1000

500

10000

8000

10000

8000

DE

DF

DG

DH

EB

4000

10000

EK

EC

EN

ED

EE

EF

EM

EG

EH

EJ

Package Quantity

Based on Finished Chip

Thickness Speciﬁcations

8000

FB

10000

8000

FC

FD

FE

FF

FG

FL

FO

FH

FP

8000

FM

FJ

8000

FN

8000

FT

4000

FK

8000

FR

8000

FS

4000

FV

1800

FW

PA

200

1000

4000

2500

1000

500

10000

4000

MA

NA

NB

NC

LD

LE

LF

LA

LB

4000

LC

4000

GB

GC

GD

GE

GH

GF

GG

GK

GJ

4000

GN

GL

GM

GO

GP

GR

HB

HC

HD

HE

HF

4000

2000

500

1400

350

1000

QTY per Reel

4000

Thickness

Code

QTY per Reel

7" Paper

QTY per Reel

13" Paper

QTY per Bulk

Cassette

Size

Range (mm)

7" Plastic

13" Plastic

C1003_C0G • 8/10/2011

7

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Table 2 – Chip Thickness/Packaging Quantities con’t

Thickness

Code

Chip

Size

Thickness ±

Range (mm)

QTY per Reel QTY per Reel QTY per Reel QTY per Reel QTY per Bulk

7" Plastic

13" Plastic

7" Paper

13" Paper

Cassette

HG

1825

2220

2225

Chip

1.60 ± 0.20

1.00 ± 0.15

1.10 ± 0.15

1.30 ± 0.15

1.40 ± 0.15

1.50 ± 0.15

1.60 ± 0.20

1.70 ± 0.15

1.80 ± 0.15

2.40 ± 0.15

3.50 ± 0.30

5.00 ± 0.50

1.00 ± 0.15

1.10 ± 0.15

1.30 ± 0.15

1.40 ± 0.15

1.60 ± 0.20

Thickness ±

1000

4000

JB

JC

1000

4000

JD

1000

4000

JE

1000

4000

JF

1000

4000

JP

1000

4000

JG

1000

4000

JH

1000

4000

JO

500

2000

JP

250

850

600

JR

150

KB

1000

4000

KC

1000

4000

KD

1000

4000

KE

1000

4000

KF

1000

4000

Thickness

Code

QTY per Reel

7" Plastic

QTY per Reel

13" Plastic

QTY per Reel

7" Paper

QTY per Reel

13" Paper

QTY per Bulk

Cassette

Size

Range (mm)

Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC-7351

Density Level A:

Maximum (Most)

Land Protrusion (mm)

Density Level B:

Median (Nominal)

Land Protrusion (mm)

Density Level C:

Minimum (Least)

Land Protrusion (mm)

EIA

Size

Code

Metric

Size

Code

C

Y

X

V1

V2

C

Y

X

V1

V2

C

Y

X

V1

V2

01005

0201

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

0402

0603

1005

1608

2012

3216

3225

4520

4532

4564

5650

5664

0.33

0.38

0.50

0.90

1.00

1.60

2.30

2.15

2.75

2.70

0.46

0.56

0.72

1.15

1.35

1.75

1.60

1.70

0.43

0.52

0.72

1.10

1.55

1.90

2.80

2.30

3.60

6.90

5.50

6.90

1.60

1.80

2.20

4.00

4.40

5.60

5.65

7.40

6.90

8.20

8.10

0.90

1.00

1.20

2.10

2.60

2.90

3.80

3.30

4.60

7.90

6.50

7.90

0.28

0.33

0.45

0.80

0.90

1.50

2.20

2.05

2.65

2.60

0.36

0.46

0.62

0.95

1.15

1.55

1.40

1.50

0.33

0.42

0.62

1.00

1.45

1.80

2.70

2.20

3.50

6.80

5.40

6.80

1.30

1.50

1.90

3.10

3.50

4.70

6.50

6.00

7.30

7.20

0.70

0.80

1.00

1.50

2.00

2.30

3.20

2.70

4.00

7.30

5.90

7.30

0.23

0.28

0.40

0.60

0.75

1.40

2.10

1.95

2.55

2.50

0.26

0.36

0.52

0.75

0.95

1.35

1.20

1.30

0.23

0.32

0.52

0.90

1.35

1.70

2.60

2.10

3.40

6.70

5.30

6.70

1.00

1.20

1.60

2.40

2.80

4.00

5.80

5.30

6.60

6.50

0.50

0.60

0.80

1.20

1.70

2.00

2.90

2.40

3.70

7.00

5.60

7.00

Density Level A: For low-density Product applications. Recommended for wave solder applications and provides a wider process window for reﬂow solder

processes. KEMET only recommends wave soldering of EIA 0603, 0805 and 1206 case sizes.

Density Level B: For products with a moderate level of component density. Provides a robust solder attachment condition for reﬂow solder processes.

Density Level C: For high component density product applications. Before adapting the minimum land pattern variations the user should perform qualiﬁcation

testing based on the conditions outlined in IPC standard 7351 (IPC-7351).

C1003_C0G • 8/10/2011

8

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Soldering Process

Recommended Soldering Technique:

• Solder wave or solder reﬂow for EIA case sizes 0603, 0805 and 1206

• All other EIA case sizes are limited to solder reﬂow only

Recommended Soldering Proﬁle:

• KEMET recommends following the guidelines outlined in IPC/JEDEC J-STD-020

Table 4 – Performance & Reliability: Test Methods and Conditions

Stress

Terminal Strength

Board Flex

Reference

JIS-C-6429

Test or Inspection Method

Appendix 1, Note: Force of 1.8kg for 60 seconds.

Appendix 2, Note: 2mm (min) for all except 3mm for C0G.

Magniﬁcation 50 X. Conditions:

a) Method B, 4 hours @ 155°C, dry heat @ 235°C

b) Method B @ 215°C category 3

Solderability

J-STD-002

c) Method D, category 3 @ 260°C

Temperature Cycling

Biased Humidity

JESD22 Method JA-104

MIL-STD-202 Method 103

1000 Cycles (-55°C to +125°C), Measurement at 24 hours. +/- 2 hours after test conclusion.

Load Humidity: 1000 hours 85°C/85%RH and Rated Voltage. Add 100K ohm resistor. Measurement

at 24 hours. +/- 2 hours after test conclusion.

Low Volt Humidity: 1000 hours 85°C/85%RH and 1.5V. Add 100K ohm resistor.

Measurement at 24 hours. +/- 2 hours after test conclusion.

t = 24 hours/cycle. Steps 7a & 7b not required. Unpowered.

Measurement at 24 hours. +/- 2 hours after test conclusion.

-55°C/+125°C. Note: Number of cycles required-300, Maximum transfer time-20 seconds, Dwell

time-15 minutes. Air-Air.

Moisture Resistance

Thermal Shock

MIL-STD-202 Method 106

MIL-STD-202 Method 107

MIL-STD-202 Method 108

/ EIA -198

High Temperature Life

1000 hours at 125°C (85°C for X5R, Z5U and Y5V) with 2 X rated voltage applied.

Storage Life

MIL-STD-202 Method 108

MIL-STD-202 Method 213

MIL-STD-202 Method 215

150°C, 0VDC, for 1000 Hours.

Mechanical Shock

Resistance to Solvents

Figure 1 of Method 213, Condition F.

Add aqueous wash chemical - OKEM Clean or equivalent.

Storage and Handling

Ceramic chip capacitors should be stored in normal working environments. While the chips themselves are quite robust in other

environments, solderability will be degraded by exposure to high temperatures, high humidity, corrosive atmospheres, and long term

storage. In addition, packaging materials will be degraded by high temperature – reels may soften or warp, and tape peel force may

increase. KEMET recommends that maximum storage temperature not exceed 40ºC, and maximum storage humidity not exceed

70% relative humidity. In addition, temperature ﬂuctuations should be minimized to avoid condensation on the parts, and atmospheres

should be free of chlorine and sulfur bearing compounds. For optimized solderability, chip stock should be used promptly, preferably

within 1.5 years of receipt.

C1003_C0G • 8/10/2011

9

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Tape & Reel Packaging Information

KEMET offers Multilayer Ceramic Chip Capacitors packaged in

8mm, 12mm and 16mm tape on 7" and 13" reels in accordance

with EIA standard 481. This packaging system is compatible with

all tape fed automatic pick and place systems. See Table 2 for

details on reeling quantities for commercial chips.

Bar Code Label

Anti-Static Reel

®

Embossed Plastic* or

Punched Paper Carrier.

Chip and KPS Orientation in Pocket

(except 1825 Commercial, and 1825 & 2225 Military)

KEMET

Sprocket Holes

Embossment or Punched Cavity

8mm, 12mm

or 16mm Carrier Tape

Anti-Static Cover Tape

(.10mm (.004") Max Thickness)

178mm (7.00")

or

330mm (13.00")

*EIA 01005, 0201, 0402 and 0603 case sizes available on punched paper carrier only.

Table 5 – Carrier Tape Conﬁguration (mm)

EIA Case Size

Tape size (W)*

Pitch (P₁)*

01005 - 0402

0603 - 1210

8

2

4

1805 - 1808

12

16

8

4

≥ 1812

8

KPS 1210

8

KPS 1812 & 2220

Array 0508 & 0612

12

4

*Refer to Figure 1 for W and P₁carrier tape reference locations.

*Refer to Table 6 for tolerance speciﬁcations.

C1003_C0G • 8/10/2011

10

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Figure 1 – Embossed (Plastic) Carrier Tape Dimensions

T

P2

[10 pitches cumulative

tolerance on tape ±0.2 mm]

2

E

1

Po

ØDo

Ao

F

Ko

W

E

2

B

1

Bo

S

1

P

1

T

1

Embossment

For cavity size,

see Note 1 Table 5

Center Lines of Cavity

ØD

1

Cover Tape

is for tape feeder reference only,

including draft concentric about B

B

1

o

.

User Direction of Unreeling

Table 6 – Embossed (Plastic) Carrier Tape Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

D₁Min.

Note 1

1.0

(0.039)

R Ref.

Note 2

25.0

(0.984)

S₁Min.

Note 3

Tape Size

8mm

D₀

E₁

P₀

P₂

T Max. T₁Max.

1.5 +0.10/-0.0

(0.059 +0.004/-0.0)

1.75 ± 0.10

4.0 ± 0.10

2.0 ± 0.05

0.600

(0.024)

0.600

0.100

12mm

(0.069 ± 0.004) (0.157 ± 0.004) (0.079 ± 0.002)

(0.024) (0.004)

1.5

(0.059)

30

(1.181)

16mm

Variable Dimensions — Millimeters (Inches)

B₁Max.

Note 4

4.35

(0.171)

Tape Size

8mm

Pitch

E₂Min.

F

P₁

T₂Max

W Max

A₀,B₀& K₀

Note 5

6.25

(0.246)

3.5 ± 0.05

(0.138 ± 0.002) (0.157 ± 0.004)

4.0 ± 0.10

2.5

(0.098)

8.3

(0.327)

Single (4mm)

Single (4mm) &

Double (8mm)

8.2

(0.323)

10.25

(0.404)

5.5 ± 0.05

(0.217 ± 0.002) (0.315 ± 0.004)

8.0 ± 0.10

4.6

(0.181)

12.3

(0.484)

12mm

12.1

(0.476)

14.25

(0.561)

5.5 ± 0.05 8.0 ± 0.10

(0.217 ± 0.002) (0.315 ± 0.004)

4.6

(0.181)

16.3

(0.642)

16mm

Triple (12mm)

1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossment location and

hole location shall be applied independent of each other.

2. The tape with or without components shall pass around R without damage (see Figure 5).

3. If S₁<1.0 mm, there may not be enough area for cover tape to be properly applied (see EIA Document 481 paragraph 4.3 (b)).

4. B1 dimension is a reference dimension for tape feeder clearance only.

5. The cavity deﬁned by A₀, B₀and K₀shall surround the component with sufﬁcient clearance that:

(a) the component does not protrude above the top surface of the carrier tape.

(b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

(c) rotation of the component is limited to 20° maximum for 8 and 12mm tapes and 10° maximum for 16mm tapes (see Figure 3).

(d) lateral movement of the component is restricted to 0.5 mm maximum for 8mm and 12mm wide tape and to 1.0mm maximum for 16mm tape (see Figure 4).

(e) for KPS Series product A₀and B₀are measured on a plane 0.3mm above the bottom of the pocket.

(f) see Addendum in EIA Document 481 for standards relating to more precise taping requirements.

C1003_C0G • 8/10/2011

11

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Figure 2 – Punched (Paper) Carrier Tape Dimensions

T

P2

[10 pitches cumulative

tolerance on tape ±0.2 mm]

E

1

Po

ØDo

0

A

F

W

2

E

0

B

Bottom Cover Tape

P

1

G

Cavity Size,

See

1

T

1

T

Top Cover Tape

Center Lines of Cavity

Note 1, Table 7

Bottom Cover Tape

User Direction of Unreeling

Table 7 – Punched (Paper) Carrier Tape Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

R Ref.

Note 2

Tape Size

8mm

D₀

E₁

P₀

P₂

T₁Max

G Min

1.5 +0.10-0.0

(0.059 +0.004, -0.0)

1.75 ±0.10

(0.069 ±0.004)

4.0 ±0.10

(0.157 ±0.004)

2.0 ±0.05

(0.079 ±0.002)

0.10

(.004) Max.

0.75

(.030)

25

(.984)

Variable Dimensions — Millimeters (Inches)

Tape Size

8mm

Pitch

E2 Min

F

P₁

T Max

W Max

A₀B₀

2.0 ± 0.05

(0.079 ± 0.002)

4.0 ± 0.10

8.3

(0.327)

8.3

Half (2mm)

Single (4mm)

6.25

(0.246)

3.5 ± 0.05

(0.138 ± 0.002)

1.1

(0.098)

Note 5

8mm

(0.157 ± 0.004)

(0.327)

1. The cavity deﬁned by A₀, B₀and T shall surround the component with sufﬁcient clearance that:

a) the component does not protrude beyond either surface of the carrier tape.

b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

d) lateral movement of the component is restricted to 0.5 mm maximum (see Figure 4).

e) see Addendum in EIA Document 481 for standards relating to more precise taping requirements.

2. The tape with or without components shall pass around R without damage (see Figure 5).

C1003_C0G • 8/10/2011

12

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Packaging Information Performance Notes

1. Cover Tape Break Force: 1.0 Kg Minimum.

2. Cover Tape Peel Strength: The total peel strength of the cover tape from the carrier tape shall be:

Tape Width

Peel Strength

8mm

0.1 Newton to 1.0 Newton (10gf to 100gf)

0.1 Newton to 1.3 Newton (10gf to 130gf)

12mm & 16mm

The direction of the pull shall be opposite the direction of the carrier tape travel. The pull angle of the carrier tape shall be 165° to 180° from the plane of the

carrier tape. During peeling, the carrier and/or cover tape shall be pulled at a velocity of 300±10 mm/minute.

3. Labeling: Bar code labeling (standard or custom) shall be on the side of the reel opposite the sprocket holes. Refer to EIA-556 and EIA-624.

Figure 3 – Maximum Component Rotation

°

T

Maximum Component Rotation

Top View

Maximum Component Rotation

Side View

Typical Pocket Centerline

Tape

Maximum

°

T

s

Width (mm) Rotation (

)

8,12

16-200

20

10

Bo

Tape

Maximum

°

S

Width (mm) Rotation (

)

8,12

16-56

72-200

20

10

5

Typical Component Centerline

Ao

Figure 4 – Maximum Lateral Movement

8mm & 12mm Tape

16mm Tape

0.5 mm maximum

1.0 mm maximum

0.5 mm maximum

Figure 5 – Bending Radius

Embossed

Carrier

Punched

Carrier

R

Bending

Radius

R

C1003_C0G • 8/10/2011

13

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Figure 6 – Reel Dimensions

Full Radius,

See Note

W3 (Includes

flange distortion

at outer edge)

Access Hole at

Slot Location

(Ø 40 mm min.)

W

2 (Measured at hub)

D

(See Note)

A

N

C

(Arbor hole

W

1 (Measured at hub)

diameter)

If present,

tape slot in core

for tape start:

2.5 mm min. width x

10.0 mm min. depth

B

(see Note)

Note: Drive spokes optional; if used, dimensions B and D shall apply.

Table 8 – Reel Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

Tape Size

8mm

A

B Min

C

D Min

178 ± 0.20

(7.008 ± 0.008)

or

330 ± 0.20

(13.000 ± 0.008)

1.5

(0.059)

13.0 +0.5/-0.2

(0.521 +0.02/-0.008)

20.2

(0.795)

12mm

16mm

Variable Dimensions — Millimeters (Inches)

Tape Size

8mm

N Min

W₁

W₂Max

W₃

8.4 +1.5/-0.0

(0.331 +0.059/-0.0)

14.4

(0.567)

50

(1.969)

12.4 +2.0/-0.0

18.4

Shall accommodate tape width

without interference

12mm

16mm

(0.488 +0.078/-0.0)

(0.724)

16.4 +2.0/-0.0

(0.646 +0.078/-0.0)

22.4

(0.882)

C1003_C0G • 8/10/2011

14

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Figure 7 – Tape Leader & Trailer Dimensions

Embossed Carrier

Carrier Tape

Punched Carrier

8 mm & 12 mm only

Round Sprocket Holes

START

END

Top Cover Tape

Elongated Sprocket Holes

(32 mm tape and wider)

100 mm Min.

Leader

Trailer

160 mm minimum,

Components

400 mm Minimum,

Top Cover Tape

Figure 8 – Maximum Camber

Elongated sprocket holes

(32 mm & wider tapes)

Carrier Tape

Round Sprocket Holes

1 mm maximum, either direction

Straight Edge

250 mm

C1003_C0G • 8/10/2011

15

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Figure 9 – Bulk Cassette Packaging (Ceramic Chips Only)

Meets Dimensional Requirements IEC-286 and EIAJ 7201

Unit mm *Reference

53 3*

10*

1.5 ± ⁰₀^.1

2.0 ± ₀⁰_.1

3.0 ± ⁰₀^.2

5 0*

110 ± 0.7

Table 9 – Capacitor Dimensions for Bulk Cassette

Cassette Packaging – Millimeters

EIA Size Metric Size

S Separation

minimum

0.3

Number of

Pcs/Cassette

W Width

B Bandwidth

T Thickness

L Length

Code

0402

1005

1.0 ± 0.05

1.6 ± 0.07

0.5 ± 0.05

0.8 ± 0.07

0.2 to 0.4

0.2 to 0.5

0.5 ± .05

0.8 ± .07

50,000

0603

1608

0.7

15,000

Table 10 – Capacitor Marking

Laser marking is available as an extra-cost option for most KEMET ceramic chips. Such marking is two sided, and includes a K to

identify KEMET, followed by two characters (per EIA-198) to identify the capacitance value. Note that marking is not available for any

Y5V chip. ln addition, the 0603 marking option is limited to the K only. (Marking Optional – Not Available for 0402 Size)

N u m e r a l

Alpha

Character

Capacitance (pF) For Various Numeral Identiﬁers

9

0

1

2

3

4

5

6

7

A

B

C

D

E

F

G

H

J

0.1

1

10

11

12

13

15

16

18

20

22

24

27

30

33

36

39

43

47

51

56

62

68

75

82

91

25

35

40

45

50

60

70

80

90

100

110

120

130

150

160

180

200

220

240

270

300

330

360

390

430

470

510

560

620

680

750

820

910

250

350

400

450

500

600

700

800

900

1000

1100

1200

1300

1500

1600

1800

2000

2200

2400

2700

3000

3300

3600

3900

4300

4700

5100

5600

6200

6800

7500

8200

9100

2500

3500

4000

4500

5000

6000

7000

8000

9000

10000

11000

12000

13000

15000

16000

18000

20000

22000

24000

27000

30000

33000

36000

39000

43000

47000

51000

56000

62000

68000

75000

82000

91000

25000

35000

40000

45000

50000

60000

70000

80000

90000

100000

110000

120000

130000

150000

160000

180000

200000

220000

240000

270000

300000

330000

360000

390000

430000

470000

510000

560000

620000

680000

750000

820000

910000

250000

350000

400000

450000

500000

600000

700000

800000

900000

1000000

1100000

1200000

1300000

1500000

1600000

1800000

2000000

2200000

2400000

2700000

3000000

3300000

3600000

3900000

4300000

4700000

5100000

5600000

6200000

6800000

7500000

8200000

9100000

2500000

3500000

4000000

4500000

5000000

6000000

7000000

8000000

9000000

10000000

11000000

12000000

13000000

15000000

16000000

18000000

20000000

22000000

24000000

27000000

30000000

33000000

36000000

39000000

43000000

47000000

51000000

56000000

62000000

68000000

75000000

82000000

91000000

25000000

35000000

40000000

45000000

50000000

60000000

70000000

80000000

90000000

0.11

0.12

0.13

0.15

0.16

0.18

0.2

0.22

0.24

0.27

0.3

0.33

0.36

0.39

0.43

0.47

0.51

0.56

0.62

0.68

0.75

0.82

0.91

0.25

0.35

0.4

1.1

1.2

1.3

1.5

1.6

1.8

2

2.2

2.4

2.7

3

3.3

3.6

3.9

4.3

4.7

5.1

5.6

6.2

6.8

7.5

8.2

9.1

2.5

3.5

4

Example shown is 1,000 pF capacitor

K

L

M

N

P

Q

R

S

T

U

V

W

X

Y

Z

a

b

d

e

f

m

n

t

0.45

0.5

0.6

0.7

0.8

4.5

5

6

7

8

y

0.9

9

C1003_C0G • 8/10/2011

16

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

KEMET Corporation

World Headquarters

Europe

Asia

Southern Europe

Geneva, Switzerland

Tel: 41-22-715-0100

Northeast Asia

Hong Kong

Tel: 852-2305-1168

2835 KEMET Way

Simpsonville, SC 29681

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Tel: 33-1-4646-1009

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Tel: 86-755-2518-1306

Mailing Address:

P.O. Box 5928

Greenville, SC 29606

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Tel: 39-051-939111

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www.kemet.com

Tel: 864-963-6300

Fax: 864-963-6521

Milan, Italy

Tel: 39-02-57518176

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Tel: 86-21-6447-0707

Corporate Ofﬁces

Fort Lauderdale, FL

Tel: 954-766-2800

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Tel: 39-06-23231718

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Tel: 886-2-27528585

Madrid, Spain

Tel: 34-91-804-4303

North America

Southeast Asia

Singapore

Tel: 65-6586-1900

Southeast

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Tel: 407-855-8886

Central Europe

Landsberg, Germany

Tel: 49-8191-3350800

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Tel: 60-4-6430200

Northeast

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Tel: 978-658-1663

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Tel: 91-806-53-76817

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Tel: 49-2307-3619672

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Tel: 610-692-4642

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Tel: 48-55-279-7025

Central

Schaumburg, IL

Tel: 847-882-3590

Northern Europe

Bishop’s Stortford, United Kingdom

Tel: 44-1279-757201

Carmel, IN

Tel: 317-706-6742

Weymouth, United Kingdom

Tel: 44-1305-830747

West

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Tel: 408-433-9950

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Tel: 44-1236-434455

Mexico

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Tel: 52-33-3123-2141

Färjestaden, Sweden

Tel: 46-485-563934

Espoo, Finland

Tel: 358-9-5406-5000

Note: KEMET reserves the right to modify minor details of internal and external construction at any time in the interest of product improvement. KEMET does not

assume any responsibility for infringement that might result from the use of KEMET Capacitors in potential circuit designs. KEMET is a registered trademark of

KEMET Electronics Corporation.

C1003_C0G • 8/10/2011

17

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Other KEMET Resources

Tools

Resource

Location

Conﬁgure A Part: CapEdge

SPICE & FIT Software

http://capacitoredge.kemet.com

http://www.kemet.com/spice

http://www.kemet.com/keask

Search Our FAQs: KnowledgeEdge

Product Information

Resource

Products

Location

http://www.kemet.com/products

Technical Resources (Including Soldering

Techniques)

http://www.kemet.com/technicalpapers

RoHS Statement

http://www.kemet.com/rohs

Quality Documents

http://www.kemet.com/qualitydocuments

Product Request

Resource

Location

Sample Request

Engineering Kit Request

http://www.kemet.com/sample

http://www.kemet.com/kits

Contact

Resource

Website

Location

www.kemet.com

Contact Us

Investor Relations

Call Us

http://www.kemet.com/contact

http://www.kemet.com/ir

1-877-MyKEMET

Twitter

http://twitter.com/kemetcapacitors

Disclaimer

All product speciﬁcations, statements, information and data (collectively, the “Information”) are subject to change without notice.

All Information given herein is believed to be accurate and reliable, but is presented without guarantee, warranty, or responsibility of any kind, expressed or implied.

Statements of suitability for certain applications are based on our knowledge of typical operating conditions for such applications, but are not intended to constitute – and we

speciﬁcally disclaim – any warranty concerning suitability for a speciﬁc customer application or use. This Information is intended for use only by customers who have the requisite

experience and capability to determine the correct products for their application. Any technical advice inferred from this Information or otherwise provided by us with reference to the

use of our products is given gratis, and we assume no obligation or liability for the advice given or results obtained.

Although we design and manufacture our products to the most stringent quality and safety standards, given the current state of the art, isolated component failures may still occur.

Accordingly, customer applications which require a high degree of reliability or safety should employ suitable designs or other safeguards (such as installation of protective circuitry or

redundancies) in order to ensure that the failure of an electrical component does not result in a risk of personal injury or property damage.

Although all product-related warnings, cautions and notes must be observed, the customer should not assume that all safety measures are indicated or that other measures may not

be required.

C1003_C0G • 8/10/2011

18

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10VDC-200VDC (Commercial Grade)

Digitally signed by Marcy Brand

DN: c=US, st=FL, l=Fort Lauderdale, o=KEMET Corporation, ou=Marketing Communications, cn=Marcy Brand,

email=marcybrand@kemet.com

Date: 2011.08.12 13:44:02 -04'00'

C1003_C0G • 8/10/2011

19

型号:	C1812C154K1RAC
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
IHS 制造商：	KEMET ELECTRONICS CORP
包装说明：	, 1812
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8532.24.00.20
风险等级：	5.21
电容：	0.15 µF
电容器类型：	CERAMIC CAPACITOR
介电材料：	CERAMIC
高度：	1 mm
JESD-609代码：	e3
长度：	4.5 mm
安装特点：	SURFACE MOUNT
多层：	Yes
负容差：	10%
端子数量：	2
最高工作温度：	125 °C
最低工作温度：	-55 °C
封装形状：	RECTANGULAR PACKAGE
封装形式：	SMT
包装方法：	TR, EMBOSSED PLASTIC, 7/13 INCH
正容差：	10%
额定（直流）电压（URdc）：	100 V
尺寸代码：	1812
表面贴装：	YES
温度特性代码：	X7R
温度系数：	15% ppm/ °C
端子面层：	Matte Tin (Sn) - with Nickel (Ni) barrier
端子形状：	WRAPAROUND
宽度：	3.2 mm
Base Number Matches：	1

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