C2225C104K1RACTU全新原装原理图各脚功能电路原理芯片引脚定义-中国IC网-芯三七

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)

C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Overview

KEMET’s C0G dielectric features a 125°C maximum operating

temperature and is considered “stable.” The Electronics

Components, Assemblies & Materials Association (EIA)

characterizes C0G dielectric as a Class I material. Components

ofꢀthisꢀclassiﬁcationꢀareꢀtemperatureꢀcompensatingꢀandꢀareꢀ

suited for resonant circuit applications or those where Q and

stability of capacitance characteristics are required. C0G exhibits

no change in capacitance with respect to time and voltage and

boasts a negligible change in capacitance with reference to

ambient temperature. Capacitance change is limited to ±30

ppm/ºC from -55°C to +125°C.

Beneﬁts

• -55°C to +125°C operating temperature range

• Lead (Pb)-Free, RoHS, and REACH compliant

• EIA 0201, 0402, 0603, 0805, 1206, 1210, 1808, 1812, 1825,

2220, and 2225 case sizes

• DC voltage ratings of 10 V, 16 V, 25 V, 50 V, 100 V, 200 V and 250 V

•ꢀ Capacitanceꢀofferingsꢀrangingꢀfromꢀ0.5ꢀpFꢀupꢀtoꢀ0.47ꢀμFꢀ

• Available capacitance tolerances of ±0.10 pF, ±0.25 pF, ±0.5

pF, ±1%, ±2%, ±5%, ±10%, and ±20%

• No piezoelectric noise

• Extremely low ESR and ESL

• High thermal stability

• High ripple current capability

Click image above for interactive 3D content

Open PDF in Adobe Reader for full functionality

Ordering Information

C

1206

C

104

J

3

G

A

C

TU

Case Size Speciﬁcation/

(L" x W")

Capacitance

Code (pF)

Capacitance

Tolerance²

Failure Rate/

Design

Packaging/Grade

(C-Spec)⁴

Ceramic

Voltage

Dielectric

G = C0G

Termination Finish³

Series¹

0201

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

C = Standard 2ꢀsigniﬁcantꢀdigitsꢀ+

B = ±0.10 pF

C = ±0.25 pF 4 = 16 V

8 = 10 V

A = N/A

C = 100% Matte Sn Blank = Bulk

TU = 7" Reel

number of zeros.

Use 9 for 1.0 – 9.9 pF D = ±0.5 pF

Use 8 for 0.5 – .99 pF F = ±1%

e.g., 2.2 pF = 229

e.g., 0.5 pF = 508

3 = 25 V

5 = 50 V

1 = 100 V

2 = 200 V

A = 250 V

Unmarked

G = ±2%

J = ±5%

K = ±10%

M = ±20%

¹Flexible termination option is available. Please see FT-CAP product bulletin C1062_C0G_FT-CAP_SMD

²Additional capacitance tolerance offerings may be available. Contact KEMET for details.

³Additional termination ﬁnish options may be available. Contact KEMET for details.

⁴Additional reeling or packaging options may be available. Contact KEMET for details.

One world. One KEMET

C1003_C0G • 4/30/2014

1

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Dimensions – Millimeters (Inches)

L

W

T

B

S

EIA

Size

Code

Metric

Size

Code

S

L

W

Width

T

B

Mounting

Technique

Separation

Minimum

Length

Thickness

Bandwidth

0201

0402

0603

0805

1206

1210

1808

1812

1825

2220

2225

0603

1005

1608

2012

3216

3225

4520

4532

4564

5650

5664

0.60 (.024) ± 0.03 (.001) 0.30 (.012) ± 0.03 (.001)

1.00 (.040) ± 0.05 (.002) 0.50 (.020) ± 0.05 (.002)

1.60 (.063) ± 0.15 (.006) 0.80 (.032) ± 0.15 (.006)

2.00 (.079) ± 0.20 (.008) 1.25 (.049) ± 0.20 (.008)

3.20 (.126) ± 0.20 (.008) 1.60 (.063) ± 0.20 (.008)

3.20 (.126) ± 0.20 (.008) 2.50 (.098) ± 0.20 (.008)

4.70 (.185) ± 0.50 (.020) 2.00 (.079) ± 0.20 (.008)

4.50 (.177) ± 0.30 (.012) 3.20 (.126) ± 0.30 (.012)

4.50 (.177) ± 0.30 (.012) 6.40 (.252) ± 0.40 (.016)

5.70 (.224) ± 0.40 (.016) 5.00 (.197) ± 0.40 (.016)

5.60 (.220) ± 0.40 (.016) 6.40 (.248) ± 0.40 (.016)

0.15 (.006) ± 0.05 (.002)

0.30 (.012) ± 0.10 (.004)

0.35 (.014) ± 0.15 (.006)

0.50 (0.02) ± 0.25 (.010)

0.60 (.024) ± 0.35 (.014)

N/A

SolderꢀReﬂowꢀOnly

0.30 (.012)

0.70 (.028)

0.75 (.030)

Solder Wave or

SolderꢀReﬂow

See Table 2 for

Thickness

N/A

SolderꢀReﬂowꢀOnly

Beneﬁts cont'd

• Preferred capacitance solution at line frequencies and into the MHz range

• No capacitance change with respect to applied rated DC voltage

• Negligible capacitance change with respect to temperature from -55°C to +125°C

• No capacitance decay with time

• Non-polar device, minimizing installation concerns

•ꢀ 100%ꢀpureꢀmatteꢀtin-platedꢀterminationꢀﬁnishꢀallowingꢀforꢀexcellentꢀsolderability

•ꢀ SnPbꢀplatedꢀterminationꢀﬁnishꢀoptionꢀavailableꢀuponꢀrequestꢀ(5%ꢀminimum)

Applications

Typical applications include critical timing, tuning, circuits requiring low loss, circuits with pulse, high current, decoupling, bypass,

ﬁltering,ꢀtransientꢀvoltageꢀsuppression,ꢀblockingꢀandꢀenergyꢀstorage.

C1003_C0G • 4/30/2014

2

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Qualiﬁcation/Certiﬁcation

CommercialꢀGradeꢀproductsꢀareꢀsubjectꢀtoꢀinternalꢀqualiﬁcation.ꢀDetailsꢀregardingꢀtestꢀmethodsꢀandꢀconditionsꢀareꢀreferencedꢀinꢀ

Table 4, Performance and Reliability.

Environmental Compliance

Lead (Pb)-Free, RoHS, and REACH compliant without exemptions.

Electrical Parameters/Characteristics

Item

Parameters/Characteristics

Operating Temperature Range

-55°C to +125°C

±30 ppm/ºC

Capacitance Change with Reference to +25°C and 0 VDC Applied (TCC)

Aging Rate (Maximum % Capacitance Loss/Decade Hour)

0%

250% of rated voltage

(5 ±1 seconds and charge/discharge not exceeding 50 mA)

Dielectric Withstanding Voltage (DWV)

0.1%

Dissipation Factor (DF) Maximum Limit @ 25ºC

1,000ꢀmegohmꢀmicrofaradsꢀorꢀ100ꢀGΩ

(Rated voltage applied for 120 ±5 seconds @ 25°C)

Insulation Resistance (IR) Limit @ 25°C

To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.

Capacitance and Dissipation Factor (DF) measured under the following conditions:

1 MHz ±100 kHz and 1.0 Vrms ±0.2 V if capacitance ≤ 1,000 pF

1 kHz ±50 Hz and 1.0 Vrms ±0.2 V if capacitance > 1,000 pF

Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 and Agilent E4980 have a feature known as

Automatic Level Control (ALC). The ALC feature should be switched to "ON."

Post Environmental Limits

High Temperature Life, Biased Humidity, Moisture Resistance

Rated DC

Voltage

Capacitance

Value

Dissipation Factor

(Maximum %)

Capacitance

Shift

Insulation

Resistance

Dielectric

C0G

All

0.5

0.3% or ±0.25 pF 10% of Initial Limit

C1003_C0G • 4/30/2014

3

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Table 1A – Capacitance Range/Selection Waterfall (0201 – 1206 Case Sizes)

Case Size/

Series

C0201C

C0402C

C0603C

C0805 C

C1206C

Cap

Code

Voltage Code

8

4

3

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

Cap

Rated Voltage (VDC)

Capacitance

Tolerance

Product Availability and Chip Thickness Codes

See Table 2 for Chip Thickness Dimensions

0.50 & 0.75 pF

0.75 pF

1.0– 9.1 pF*

10 pF

508 & 758

758

109 – 919*

100

110

120

130

150

160

180

B

C D

BB BB BB BB

CB CB CB CB CB CB

DC DC DC DC DC DC

DJ DJ DJ DJ DC DC

DC DC DC DC DC DC

EB EB EB EB EB EB

F

G

J

K M AB¹ AB¹ AB¹ BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB

K M BB BB BB BB

K M AB² AB² AB² BB BB BB BB BB BB BB CB CB CB CF CB CB

BB BB BB BB BB BB BB CB CB CB CB CB CB

11 pF

12 pF

13 pF

15 pF

16 pF

18 pF

20 pF

22 pF

24 pF

27 pF

30 pF

33 pF

36 pF

39 pF

43 pF

47 pF

51 pF

56 pF

62 pF

68 pF

75 pF

82 pF

91 pF

200

220

240

270

300

330

360

390

430

470

510

560

620

680

750

820

910

101

111 – 181*

201

221

241

271

301

331

361

391

431

471

511

561

621

681

751

100 pF

110 – 180 pF*

200 pF

220 pF

240 pF

270 pF

300 pF

330 pF

360 pF

390 pF

430 pF

470 pF

510 pF

560 pF

620 pF

680 pF

750 pF

820 pF

910 pF

1,000 pF

1,100 pF

1,200 pF

1,300 pF

K M

BB BB BB BB BB BB BB CB CB CB CB CB CB CB DC DC DC DC DC DC

BB BB BB BB BB BD BD CB CB CB CB CB CB CB DC DC DC DC DC DC

BB BB BB BB BB BD BD CB CB CB CF CB CB CB DC DC DC DC DC DC

BB BB BB BB BB

BB BB BB BB

CB CB CB CB CB CB CB DC DC DC DC DC DC

CB CB CB CB CB CB CB DC DC DC DC DC DD

CB CB CB CB CB CB CB DC DC DC DC DC DC

CB CB CB CB CB CB CB DC DC DC DC DD DD

821

911

102

112

122

132

CB CB CB CB CB CH CH DC DC DC DC DC DC DC EB EB EB EB EB EB

CB CB CB CB CB CH CH DD DD DD DD DD DC DC EB EB EB EB EC EC

BB BB BB BB

Rated Voltage (VDC)

Voltage Code

Cap

Code

8

4

3

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

Cap

Case Size/Series C0201C

C0402C

C0603C

C0805C

C1206C

*Capacitance range Includes E24 decade values only. (i.e., 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82 and 91).

xx¹ Available only in D, J, K,M tolerance

xx² Available only in J, K, M tolerance.

These products are protected under US Patents 7,172,985 & 7,670,981, other patents pending, and any foreign counterparts.

C1003_C0G • 4/30/2014

4

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Table 1A – Capacitance Range/Selection Waterfall (0201 – 1206 Case Sizes) cont'd

Case Size/

Series

C0201C

C0402C

C0603C

C0805 C

C1206C

Cap

Code

Voltage Code

8

4

3

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

Cap

Rated Voltage (VDC)

Capacitance

Tolerance

Product Availability and Chip Thickness Codes

See Table 2 for Chip Thickness Dimensions

1,500 pF

1,600 pF

1,800 pF

2,000 pF

2,200 pF

2,400 pF

2,700 pF

3,000 pF

3,300 pF

3,600 pF

3,900 pF

4,300 pF

4,700 pF

5,100 pF

5,600 pF

6,200 pF

6,800 pF

7,500 pF

8,200 pF

9,100 pF

10,000 pF

12,000 pF

15,000 pF

18,000 pF

22,000 pF

27,000 pF

33,000 pF

39,000 pF

47,000 pF

56,000 pF

68,000 pF

82,000 pF

0.10 µF

152

162

182

202

222

242

272

302

332

362

392

432

472

512

562

622

682

752

822

912

103

123

153

183

223

273

333

393

473

563

683

823

104

F

G

J

K M

BB BB BB BB

BB BB BB

CB CB CB CB CB CH CH DD DD DD DD DD DC DC EB EB EB EB ED EC

CB CB CB CB CB CH CH DD DD DD DD DD DC DC EB EB EB EB ED ED

CB CB CB CB CB CH CH DC DC DC DC DC DC DC EB EB EB EB ED ED

CB CB CB CB CB CH CH DC DC DC DC DC DC DC EB EB EB EB EE EE

CB CB CB CB CB

CB CB CB CB

CB CB CB

DC DC DC DC DC DC DC EB EB EB EB EC EC

DD DD DD DD DC DC DC EC EC EC EC EC EB EB

DD DD DD DD DC DC DC EC EC EC EC EE EB EB

DD DD DD DD DC DD DD EC EC EC EC EE EB EB

DE DE DE DE DC DD DD EC EC EC EC EF EB EB

DE DE DE DE DC DD DD EC EC EC EC EC EB EB

DE DE DE DE DC DD DD ED ED ED ED ED EB EB

DC DC DC DC DC DD DD ED ED ED ED ED EB EB

DC DC DC DC DC DG DG EB EB EB EB EB EB EB

DC DC DC DC DC DG DG EC EC EC EC EB EC EC

CB CB CB

DC DC DC DC DC

DC DC DC DC DD

DC DC DC DC DE

DC DC DC DD DG

DC DC DC DD

DD DD DD DF

DF DF DF

EC EC EC EC EB EC EC

ED ED ED ED EB EC EC

EB EB EB EB EB ED ED

EB EB EB EB EB EF EF

EB EB EB EB EB EH EH

EB EB EB EB EC EH EH

EB EB EB EB EE

DG DG DG

EB EB EB EB EE

DG DG DG

EC EC EC EE EH

DG DG DG

EC EC EC EE EH

ED ED ED EF

EF EF EF EH

EH EH EH EH

EH EH EH

Rated Voltage (VDC)

Voltage Code

Cap

Code

8

4

3

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

8

4

3

5

1

2

A

Cap

Case Size/Series C0201C

C0402C

C0603C

C0805C

C1206C

*Capacitance range Includes E24 decade values only. (i.e., 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82 and 91).

xx¹ Available only in D, J, K,M tolerance

xx² Available only in J, K, M tolerance.

These products are protected under US Patents 7,172,985 & 7,670,981, other patents pending, and any foreign counterparts.

C1003_C0G • 4/30/2014

5

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Table 1B – Capacitance Range/Selection Waterfall (1210 – 2225 Case Sizes)

Case Size/

Series

C1210C

C1808C

C1812C

C1825C

C2220C

C2225C

Cap

Code

Voltage Code

8

4

3

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

Cap

Rated Voltage (VDC)

Capacitance

Tolerance

Product Availability and Chip Thickness Codes

See Table 2 for Chip Thickness Dimensions

1.0 – 9.1 pF*

10 – 91 pF*

100 – 300 pF* 101 – 301*

330 – 430 pF* 331 – 431*

470 – 910 pF* 471 – 911*

109 – 919* B C D

100 – 910*

FB FB FB FB FB FB

F G J K M FB FB FB FB FB FB

F G J K M FB FB FB FB FB FC

F G J K M FB FB FB FB FB FE

F G J K M FB FB FB FB FC FE

F G J K M FB FB FB FB FC FG

F G J K M FB FB FB FB FC FC

F G J K M FB FB FB FB FC FF

F G J K M FB FB FB FB FF FF

F G J K M FF FF FF FF FG FG

F G J K M FB FB FB FB FG FG

F G J K M FB FB FB FB FG FB FB

F G J K M FC FC FC FC FC FB FB

F G J K M FE FE FE FE FE FB FB

F G J K M FF FF FF FF FF FB FB

F G J K M FG FG FG FG FB FB FB

F G J K M FG FG FG FG FB FC FC

F G J K M FB FB FB FB FB FC FC

F G J K M FB FB FB FB FB FF FF

F G J K M FB FB FB FB FB FG FG

F G J K M FB FB FB FB FB FH FH

F G J K M FB FB FB FB FE FH FH

F G J K M FB FB FB FB FE FJ FJ

F G J K M FB FB FB FB FF

F G J K M FB FB FB FC FG

F G J K M FC FC FC FF FH

F G J K M FE FE FE FG FM

F G J K M FG FG FG FH

LF LF LF

LF LF

GB GB GB

1,000 pF

1,100 pF

1,200 pF

1,300 pF

1,500 pF

1,600 pF

1,800 pF

2,000 pF

2,200 pF

2,400 pF

2,700 pF

3,000 pF

3,300 pF

3,600 pF

3,900 pF

4,300 pF

4,700 pF

5,100 pF

5,600 pF

6,200 pF

6,800 pF

7,500 pF

8,200 pF

9,100 pF

10,000 pF

12,000 pF

15,000 pF

18,000 pF

22,000 pF

27,000 pF

33,000 pF

39,000 pF

47,000 pF

56,000 pF

68,000 pF

82,000 pF

0.10 µF

102

112

122

132

152

162

182

202

222

242

272

302

332

362

392

432

472

512

562

622

682

752

822

912

103

123

153

183

223

273

333

393

473

563

683

823

104

124

154

184

224

274

334

394

474

GB GB GB

GB GB GD

GB GB GH

GB GB GJ

LF LF

HB HB HB

LF LF

KE KE KE

JE JE JB JB KE KE KE

KE KE KE

GB GH GB GB HB HB HB

JE JE JB JB KE KE KE

KE KE KE

GB GH GB GB HB HB HE

GB GG GB GB HB HB HE

GB GB GB GB HB HB

GB GB GB GB HB HE

GB GB GB GB HB HG

GB GB GB GB

GB GB GD GD

GB GB GK GK

GB GB GM GM

GB GD GM GM

GB GH

JE JE JB JB KE KE KE

JE JE JB JB KE KE

JE JB JB JB KE KE

JB JB JB JB KE

JB JB JB JB

JB JB JD JD

0.12 µF

0.15 µF

0.18 µF

0.22 µF

0.27 µF

0.33 µF

0.39 µF

0.47 µF

F G J K M FH FH FH FM

F G J K M FJ FJ FJ

F G J K M FK FK FK

F G J K M

GD GN

JB JB JG JG

GH

JB JD JG JG

GK

JB JD JL JL

JB JF

JD JG

JG

Rated Voltage (VDC)

Cap

Code

Voltage Code

Case Size/

Series

8

4

3

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

A

5

1

2

Cap

C1210C

C1808C

C1812C

C1825C

C2220C

C2225C

*Capacitance range Includes E24 decade values only. (i.e., 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62, 68, 75, 82 and 91).

These products are protected under US Patents 7,172,985 & 7,670,981, other patents pending, and any foreign counterparts.

C1003_C0G • 4/30/2014

6

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Table 2 – Chip Thickness/Packaging Quantities

Paper Quantity

7" Reel 13" Reel

Plastic Quantity

7" Reel 13" Reel

Thickness Case Thickness ±

Code

Size

Range (mm)

AB

BB

BD

CB

CF

CH

DJ

DC

DD

DE

DF

DG

EB

EC

ED

EE

EF

EH

FB

FC

FE

FF

FG

FH

FM

FJ

FK

NC

LF

GB

GD

GH

GG

GK

GJ

GN

GM

HB

HE

HG

JB

0201

0402

0603

0805

1206

1210

1706

1808

1812

1825

2220

2225

0.30 ± 0.03

0.50 ± 0.05

0.55 ± 0.05

0.80 ± 0.07

0.80 ± 0.07*

0.85 ± 0.07

0.70 ± 0.20

0.78 ± 0.10

0.90 ± 0.10

1.00 ± 0.10

1.10 ± 0.10

1.25 ± 0.15

0.78 ± 0.10

0.90 ± 0.10

1.00 ± 0.10

1.10 ± 0.10

1.20 ± 0.15

1.60 ± 0.20

0.78 ± 0.10

0.90 ± 0.10

1.00 ± 0.10

1.10 ± 0.10

1.25 ± 0.15

1.55 ± 0.15

1.70 ± 0.20

1.85 ± 0.20

2.10 ± 0.20

1.00 ± 0.15

1.00 ± 0.10

1.25 ± 0.15

1.40 ± 0.15

1.55 ± 0.10

1.60 ± 0.20

1.70 ± 0.15

1.70 ± 0.20

2.00 ± 0.20

1.10 ± 0.15

1.40 ± 0.15

1.60 ± 0.20

1.00 ± 0.15

1.30 ± 0.15

1.40 ± 0.15

1.50 ± 0.15

1.70 ± 0.15

2.00 ± 0.20

1.40 ± 0.15

15,000

10,000

4,000

0

50,000

10,000

15,000

10,000

4,000

0

2,500

4,000

2,500

2,000

4,000

2,500

2,000

4,000

2,500

1,000

500

10,000

8,000

10,000

8,000

10,000

4,000

2,000

4,000

2,000

4,000

0

4,000

0

10,000

0

1,000

500

JD

JE

JF

JG

JL

KE

0

1,000

7" Reel

13" Reel

7" Reel

13" Reel

Thickness

Code

Case

Size

Thickness ±

Range (mm)

Paper Quantity

Plastic Quantity

Package quantity based on ﬁnished chip thickness speciﬁcations.

C1003_C0G • 4/30/2014

7

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC–7351

Density Level A:

Maximum (Most)

Land Protrusion (mm)

Density Level B:

Median (Nominal)

Land Protrusion (mm)

Density Level C:

Minimum (Least)

Land Protrusion (mm)

EIA

Size

Code

Metric

Size

Code

C

Y

X

V1

V2

C

Y

X

V1

V2

C

Y

X

V1

V2

0201

0402

0603

0805

1206

1210

1210¹

1808

1812

1825

2220

2225

0603

1005

1608

2012

3216

3225

4520

4532

4564

5650

5664

0.38

0.56

0.52

1.80

1.00

0.33

0.46

0.42

1.50

0.80

0.28

0.36

0.32

1.20

0.60

0.50

0.90

1.00

1.60

1.50

2.30

2.15

2.75

2.70

0.72

1.15

1.35

1.60

1.75

1.60

1.70

0.72

1.10

1.55

1.90

2.80

2.90

2.30

3.60

6.90

5.50

6.90

2.20

4.00

4.40

5.60

5.65

5.60

7.40

6.90

8.20

8.10

1.20

2.10

2.60

2.90

3.80

3.90

3.30

4.60

7.90

6.50

7.90

0.45

0.80

0.90

1.50

1.40

2.20

2.05

2.65

2.60

0.62

0.95

1.15

1.40

1.55

1.40

1.50

0.62

1.00

1.45

1.80

2.70

2.80

2.20

3.50

6.80

5.40

6.80

1.90

3.10

3.50

4.70

6.50

6.00

7.30

7.20

1.00

1.50

2.00

2.30

3.20

3.30

2.70

4.00

7.30

5.90

7.30

0.40

0.60

0.75

1.40

1.30

2.10

1.95

2.55

2.50

0.52

0.75

0.95

1.20

1.35

1.20

1.30

0.52

0.90

1.35

1.70

2.60

2.70

2.10

3.40

6.70

5.30

6.70

1.60

2.40

2.80

4.00

5.80

5.30

6.60

6.50

0.80

1.20

1.70

2.00

2.90

3.00

2.40

3.70

7.00

5.60

7.00

¹Only for capacitance values ≥ 22 µF

Density Level A: For low-density product applications. Recommended for wave solder applications and provides a wider process window for reﬂow solder

processes. KEMET only recommends wave soldering of EIA 0603, 0805 and 1206 case sizes.

Density Level B: For products with a moderate level of component density. Provides a robust solder attachment condition for reﬂow solder processes.

Density Level C: For high component density product applications. Before adapting the minimum land pattern variations the user should perform qualiﬁcation

testing based on the conditions outlined in IPC Standard 7351 (IPC–7351).

Image below based on Density Level B for an EIA 1210 case size.

V1

Y

V2

X

C

Grid Placement Courtyard

C1003_C0G • 4/30/2014

8

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Soldering Process

Recommended Soldering Technique:

ꢀ •ꢀSolderꢀwaveꢀorꢀsolderꢀreﬂowꢀforꢀEIAꢀcaseꢀsizesꢀ0603,ꢀ0805ꢀandꢀ1206

ꢀ •ꢀAllꢀotherꢀEIAꢀcaseꢀsizesꢀareꢀlimitedꢀtoꢀsolderꢀreﬂowꢀonly

Recommended Reﬂow Soldering Proﬁle:

KEMET’s families of surface mount multilayer ceramic capacitors (SMD MLCCs) are compatible with wave (single or dual), convection,

IRꢀorꢀvaporꢀphaseꢀreﬂowꢀtechniques.ꢀPreheatingꢀofꢀtheseꢀcomponentsꢀisꢀrecommendedꢀtoꢀavoidꢀextremeꢀthermalꢀstress.ꢀKEMET’sꢀ

recommendedꢀproﬁleꢀconditionsꢀforꢀconvectionꢀandꢀIRꢀreﬂowꢀreﬂectꢀtheꢀproﬁleꢀconditionsꢀofꢀtheꢀIPC/J-STD-020ꢀstandardꢀforꢀmoistureꢀ

sensitivityꢀtesting.ꢀTheseꢀdevicesꢀcanꢀsafelyꢀwithstandꢀaꢀmaximumꢀofꢀthreeꢀreﬂowꢀpassesꢀatꢀtheseꢀconditions.

T_P

T_L

Termination Finish

t_P

Maximum Ramp Up Rate = 3°C/sec

Maximum Ramp Down Rate = 6°C/sec

Proﬁle Feature

SnPb

100% Matte Sn

t_L

Preheat/Soak

T_smax

T_smin

Temperature Minimum (T_Smin

Temperature Maximum (T_Smax

Time (t_S) from T_Sminto T_Smax

)

100°C

150°C

200°C

)

t_S

60 – 120 seconds

Ramp-Up Rate (T_Lto T_P)

Liquidous Temperature (T_L)

Time Above Liquidous (t_L)

Peak Temperature (T_P)

3°C/second maximum 3°C/second maximum

25

183°C

60 – 150 seconds

235°C

217°C

60 – 150 seconds

260°C

25° C to Peak

Time

Time Within 5°C of Maximum

Peak Temperature (t_P)

20 seconds maximum 30 seconds maximum

Ramp-Down Rate (T_Pto T_L) 6°C/second maximum 6°C/second maximum

Time 25°C to Peak

6 minutes maximum

8 minutes maximum

Temperature

Note 1: All temperatures refer to the center of the package, measured on the

capacitor body surface that is facing up during assembly reﬂow.

C1003_C0G • 4/30/2014

9

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Table 4 – Performance & Reliability: Test Methods and Conditions

Stress

Reference

Test or Inspection Method

Terminal Strength

JIS–C–6429

Appendix 1, Note: Force of 1.8 kg for 60 seconds.

Appendix 2, Note: Standard termination system – 2.0 mm (minimum) for all except 3 mm for C0G.

Flexible termination system – 3.0 mm (minimum).

Board Flex

JIS–C–6429

Magniﬁcationꢀ50ꢀX.ꢀConditions:

a) Method B, 4 hours @ 155°C, dry heat @ 235°C

b) Method B @ 215°C category 3

Solderability

J–STD–002

c) Method D, category 3 @ 260°C

Temperature Cycling

Biased Humidity

JESD22 Method JA–104

MIL–STD–202 Method 103

1,000 Cycles (-55°C to +125°C). Measurement at 24 hours +/- 2 hours after test conclusion.

Load Humidity: 1,000 hours 85°C/85% RH and rated voltage. Add 100 K ohm resistor. Measurement

at 24 hours +/- 2 hours after test conclusion.

Low Volt Humidity: 1,000 hours 85°C/85% RH and 1.5 V. Add 100 K ohm resistor.

Measurement at 24 hours +/- 2 hours after test conclusion.

t = 24 hours/cycle. Steps 7a and 7b not required. Unpowered.

Measurement at 24 hours +/- 2 hours after test conclusion.

-55°C/+125°C. Note: Number of cycles required – 300, maximum transfer time – 20 seconds, dwell

time – 15 minutes. Air – Air.

Moisture Resistance

Thermal Shock

MIL–STD–202 Method 106

MIL–STD–202 Method 107

MIL–STD–202 Method 108

/EIA–198

High Temperature Life

Storage Life

1,000ꢀhoursꢀatꢀ125°Cꢀ(85°CꢀforꢀX5R,ꢀZ5UꢀandꢀY5V)ꢀwithꢀ2ꢀXꢀratedꢀvoltageꢀapplied.

MIL–STD–202 Method 108 150°C, 0 VDC for 1,000 hours.

5ꢀg'sꢀforꢀ20ꢀmin.,ꢀ12ꢀcyclesꢀeachꢀofꢀ3ꢀorientations.ꢀNote:ꢀUseꢀ8"ꢀXꢀ5"ꢀPCBꢀ0.031"ꢀthickꢀ7ꢀsecureꢀ

MIL–STD–202 Method 204 points on one long side and 2 secure points at corners of opposite sides. Parts mounted within 2"

from any secure point. Test from 10 – 2,000 Hz

Vibration

Mechanical Shock

MIL–STD–202 Method 213 Figure 1 of Method 213, Condition F.

Resistance to Solvents MIL–STD–202 Method 215 Add aqueous wash chemical, OKEM Clean or equivalent.

Storage and Handling

Ceramic chip capacitors should be stored in normal working environments. While the chips themselves are quite robust in other

environments, solderability will be degraded by exposure to high temperatures, high humidity, corrosive atmospheres, and long term

storage. In addition, packaging materials will be degraded by high temperature– reels may soften or warp and tape peel force may

increase. KEMET recommends that maximum storage temperature not exceed 40ºC and maximum storage humidity not exceed 70%

relativeꢀhumidity.ꢀTemperatureꢀﬂuctuationsꢀshouldꢀbeꢀminimizedꢀtoꢀavoidꢀcondensationꢀonꢀtheꢀpartsꢀandꢀatmospheresꢀshouldꢀbeꢀfreeꢀofꢀ

chlorine and sulfur bearing compounds. For optimized solderability chip stock should be used promptly, preferably within 1.5 years of

receipt.

C1003_C0G • 4/30/2014 10

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Construction

Detailed Cross Section

Dielectric Material

(CaZrO₃)

Dielectric Material

(CaZrO₃)

Barrier Layer

(Ni)

Termination Finish

(100% Matte Sn)

Base Metal

(Cu)

Inner Electrodes

(Ni)

Base Metal

(Cu)

Barrier Layer

(Ni)

Termination Finish

(100% Matte Sn)

Inner Electrodes

(Ni)

Capacitor Marking (Optional):

Laser marking option is not available on:

•ꢀ C0G,ꢀUltraꢀStableꢀX8RꢀandꢀY5Vꢀdielectricꢀdevicesꢀ

• EIA 0402 case size devices

• EIA 0603 case size devices with Flexible Termination option.

• KPS Commercial and Automotive grade stacked devices.

These capacitors are supplied unmarked only.

C1003_C0G • 4/30/2014 11

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Tape & Reel Packaging Information

KEMET offers multilayer ceramic chip capacitors packaged in 8, 12 and 16 mm tape on 7" and 13" reels in accordance with EIA

Standard 481. This packaging system is compatible with all tape-fed automatic pick and place systems. See Table 2 for details on

reeling quantities for commercial chips.

Bar Code Label

Anti-Static Reel

®

Embossed Plastic* or

Punched Paper Carrier.

Chip and KPS Orientation in Pocket

(except 1825 Commercial, and 1825 and 2225 Military)

KEMET

Sprocket Holes

Embossment or Punched Cavity

8 mm, 12 mm

or 16 mm Carrier Tape

Anti-Static Cover Tape

(.10 mm (.004") Maximum Thickness)

178 mm (7.00")

or

330 mm (13.00")

*EIA 01005, 0201, 0402 and 0603 case sizes available on punched paper carrier only.

Table 5 – Carrier Tape Conﬁguration – Embossed Plastic & Punched Paper (mm)

EIA Case Size

01005 – 0402

0603 – 1210

Tape Size (W)*

Pitch (P₁)*

8

2

4

1805 – 1808

12

16

8

4

≥ꢀ1812

8

KPS 1210

8

KPS 1812 & 2220

Array 0508 & 0612

12

4

*Refer to Figures 1 & 2 for W and P₁carrier tape reference locations.

*Refer to Tables 6 & 7 for tolerance speciﬁcations.

C1003_C0G • 4/30/2014 12

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Figure 1 – Embossed (Plastic) Carrier Tape Dimensions

T

P2

[10 pitches cumulative

tolerance on tape ± 0.2 mm]

2

E

1

Po

ØDo

Ao

F

Ko

W

E

2

B

1

Bo

S

1

P

1

T

1

Embossment

For cavity size,

see Note 1 Table 4

Center Lines of Cavity

ØD

1

Cover Tape

is for tape feeder reference only,

including draft concentric about B

B

1

o

.

User Direction of Unreeling

Table 6 – Embossed (Plastic) Carrier Tape Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

D₁Minimum

Note 1

1.0

(0.039)

R Reference S₁Minimum

T

T₁

Tape Size

8 mm

D₀

E₁

P₀

P₂

Note 2

Note 3

Maximum

25.0

(0.984)

1.5 +0.10/-0.0

(0.059 +0.004/-0.0)

1.75 ±0.10

4.0 ±0.10

2.0 ±0.05

0.600

(0.024)

0.600

(0.024)

0.100

(0.004)

12 mm

16 mm

(0.069 ±0.004) (0.157 ±0.004) (0.079 ±0.002)

1.5

(0.059)

30

(1.181)

Variable Dimensions — Millimeters (Inches)

B₁Maximum

Note 4

4.35

(0.171)

E₂

T₂

W

Tape Size

8 mm

Pitch

F

P₁

A₀,B₀& K₀

Minimum

6.25

(0.246)

Maximum

2.5

(0.098)

Maximum

8.3

(0.327)

3.5 ±0.05

(0.138 ±0.002) (0.157 ±0.004)

4.0 ±0.10

Single (4 mm)

Single (4 mm) &

Double (8 mm)

8.2

10.25

5.5 ±0.05

8.0 ±0.10

4.6

12.3

12 mm

16 mm

Note 5

(0.323)

(0.404)

(0.217 ±0.002) (0.315 ±0.004)

(0.181)

(0.484)

12.1

(0.476)

14.25

(0.561)

7.5 ±0.05 12.0 ±0.10

(0.138 ±0.002) (0.157 ±0.004)

4.6

(0.181)

16.3

(0.642)

Triple (12 mm)

1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossment location and

hole location shall be applied independent of each other.

2. The tape with or without components shall pass around R without damage (see Figure 6).

3. If S₁< 1.0 mm, there may not be enough area for cover tape to be properly applied (see EIA Standard 481 paragraph 4.3 section b).

4. B₁dimension is a reference dimension for tape feeder clearance only.

5. The cavity deﬁned by A₀, B₀and K₀shall surround the component with sufﬁcient clearance that:

(a) the component does not protrude above the top surface of the carrier tape.

(b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

(c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 3).

(d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape (see Figure 4).

(e) for KPS Series product, A₀and B₀are measured on a plane 0.3 mm above the bottom of the pocket.

(f) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

C1003_C0G • 4/30/2014 13

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Figure 2 – Punched (Paper) Carrier Tape Dimensions

T

P2

[10 pitches cumulative

tolerance on tape ± 0.2 mm]

E

1

Po

ØDo

0

A

F

W

2

E

0

B

Bottom Cover Tape

P

1

G

Cavity Size,

See

1

T

1

T

Top Cover Tape

Center Lines of Cavity

Note 1, Table 7

Bottom Cover Tape

User Direction of Unreeling

Table 7 – Punched (Paper) Carrier Tape Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

R Reference

Note 2

Tape Size

8 mm

D₀

E₁

P₀

P₂

T₁Maximum

0.10

G Minimum

1.5 +0.10 -0.0

(0.059 +0.004 -0.0)

1.75 ±0.10

(0.069 ±0.004)

4.0 ±0.10

(0.157 ±0.004)

2.0 ±0.05

(0.079 ±0.002) (0.004) Maximum

0.75

(0.030)

25

(0.984)

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

Pitch

E2 Minimum

F

P₁

T Maximum

W Maximum

A₀B₀

2.0 ±0.05

(0.079 ±0.002)

4.0 ±0.10

8.3

(0.327)

8.3

Half (2 mm)

Single (4 mm)

6.25

(0.246)

3.5 ±0.05

(0.138 ±0.002)

1.1

(0.098)

Note 1

8 mm

(0.157 ±0.004)

(0.327)

1. The cavity deﬁned by A₀, B₀and T shall surround the component with sufﬁcient clearance that:

a) the component does not protrude beyond either surface of the carrier tape.

b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed.

c) rotation of the component is limited to 20° maximum (see Figure 3).

d) lateral movement of the component is restricted to 0.5 mm maximum (see Figure 4).

e) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements.

2. The tape with or without components shall pass around R without damage (see Figure 6).

C1003_C0G • 4/30/2014 14

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Packaging Information Performance Notes

1. Cover Tape Break Force: 1.0 Kg minimum.

2. Cover Tape Peel Strength: The total peel strength of the cover tape from the carrier tape shall be:

Tape Width

8 mm

Peel Strength

0.1 to 1.0 Newton (10 to 100 gf)

0.1 to 1.3 Newton (10 to 130 gf)

12 and 16 mm

The direction of the pull shall be opposite the direction of the carrier tape travel. The pull angle of the carrier tape shall be 165° to 180°

from the plane of the carrier tape. During peeling, the carrier and/or cover tape shall be pulled at a velocity of 300 ±10 mm/minute.

3. Labeling: Bar code labeling (standard or custom) shall be on the side of the reel opposite the sprocket holes. Refer to EIA

Standards 556 and 624.

Figure 3 – Maximum Component Rotation

°

T

Maximum Component Rotation

Top View

Maximum Component Rotation

Side View

Typical Pocket Centerline

Tape

Maximum

°

T

s

Width (mm) Rotation (

)

8,12

16 – 200

20

10

Bo

Tape

Maximum

°

S

Width (mm) Rotation (

)

8,12

16 – 56

72 – 200

20

10

5

Typical Component Centerline

Ao

Figure 4 – Maximum Lateral Movement

Figure 5 – Bending Radius

Embossed

Carrier

Punched

Carrier

8 mm & 12 mm Tape

16 mm Tape

0.5 mm maximum

1.0 mm maximum

R

Bending

Radius

R

C1003_C0G • 4/30/2014 15

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Figure 6 – Reel Dimensions

Full Radius,

See Note

W3 (Includes

flange distortion

at outer edge)

Access Hole at

Slot Location

(Ø 40 mm minimum)

W

2 (Measured at hub)

D

(See Note)

A

N

C

(Arbor hole

W

1 (Measured at hub)

diameter)

If present,

tape slot in core

for tape start:

2.5 mm minimum width x

10.0 mm minimum depth

B

(see Note)

Note: Drive spokes optional; if used, dimensions B and D shall apply.

Table 8 – Reel Dimensions

Metric will govern

Constant Dimensions — Millimeters (Inches)

Tape Size

8 mm

A

B Minimum

C

D Minimum

178 ±0.20

(7.008 ±0.008)

or

330 ±0.20

(13.000 ±0.008)

1.5

(0.059)

13.0 +0.5/-0.2

(0.521 +0.02/-0.008)

20.2

(0.795)

12 mm

16 mm

Variable Dimensions — Millimeters (Inches)

Tape Size

8 mm

N Minimum

W₁

W₂Maximum

W₃

8.4 +1.5/-0.0

(0.331 +0.059/-0.0)

14.4

(0.567)

50

(1.969)

12.4 +2.0/-0.0

18.4

Shall accommodate tape width

without interference

12 mm

16 mm

(0.488 +0.078/-0.0)

(0.724)

16.4 +2.0/-0.0

(0.646 +0.078/-0.0)

22.4

(0.882)

C1003_C0G • 4/30/2014 16

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Figure 7 – Tape Leader & Trailer Dimensions

Embossed Carrier

Carrier Tape

Round Sprocket Holes

Punched Carrier

8 mm & 12 mm only

START

END

Top Cover Tape

Elongated Sprocket Holes

(32 mm tape and wider)

100 mm

Minimum Leader

400 mm Minimum

Trailer

160 mm Minimum

Components

Top Cover Tape

Figure 8 – Maximum Camber

Elongated sprocket holes

(32 mm & wider tapes)

Carrier Tape

Round Sprocket Holes

1 mm Maximum, either direction

Straight Edge

250 mm

Bulk Cassette Packaging (Ceramic Chips Only)

Meets Dimensional Requirements IEC–286 and EIAJ 7201

Unit mm *Reference

53 3*

10*

1.5 ± ⁰₀^.1

2.0 ± ₀⁰_.1

3.0 ± ⁰₀^.2

5 0*

110 ± 0.7

Capacitor Dimensions for Bulk Cassette

Cassette Packaging – Millimeters

EIA Size Metric Size

S Separation

Minimum

Number of

Pieces/Cassette

L Length

W Width

B Bandwidth

T Thickness

Code

0402

1005

1.0 ±0.05

1.6 ±0.07

0.5 ±0.05

0.8 ±0.07

0.2 to 0.4

0.2 to 0.5

0.3

0.5 ±0.05

0.8 ±0.07

50,000

0603

1608

0.7

15,000

C1003_C0G • 4/30/2014 17

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

KEMET Corporation

World Headquarters

Europe

Asia

Southern Europe

Paris, France

Tel: 33-1-4646-1006

Northeast Asia

Hong Kong

Tel: 852-2305-1168

2835 KEMET Way

Simpsonville, SC 29681

Sasso Marconi, Italy

Tel: 39-051-939111

Shenzhen, China

Tel: 86-755-2518-1306

Mailing Address:

P.O. Box 5928

Greenville, SC 29606

Beijing, China

Central Europe

Landsberg, Germany

Tel: 49-8191-3350800

Tel: 86-10-5829-1711

www.kemet.com

Tel: 864-963-6300

Fax: 864-963-6521

Shanghai, China

Tel: 86-21-6447-0707

Kamen, Germany

Tel: 49-2307-438110

Corporate Ofﬁces

Fort Lauderdale, FL

Tel: 954-766-2800

Taipei, Taiwan

Tel: 886-2-27528585

Northern Europe

Bishop’s Stortford, United Kingdom

Tel: 44-1279-460122

North America

Southeast Asia

Singapore

Southeast

Tel: 65-6586-1900

Lake Mary, FL

Tel: 407-855-8886

Espoo, Finland

Tel: 358-9-5406-5000

Penang, Malaysia

Tel: 60-4-6430200

Northeast

Wilmington, MA

Tel: 978-658-1663

Bangalore, India

Tel: 91-806-53-76817

Central

Novi, MI

Tel: 248-306-9353

West

Milpitas, CA

Tel: 408-433-9950

Mexico

Guadalajara, Jalisco

Tel: 52-33-3123-2141

Note: KEMET reserves the right to modify minor details of internal and external construction at any time in the interest of product improvement. KEMET does not

assume any responsibility for infringement that might result from the use of KEMET Capacitors in potential circuit designs. KEMET is a registered trademark of

KEMET Electronics Corporation.

C1003_C0G • 4/30/2014 18

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) – C0G Dielectric, 10 – 200 VDC (Commercial Grade)

Disclaimer

Allꢀproductꢀspeci ꢀcations,ꢀstatements,ꢀinformationꢀandꢀdataꢀ(collectively,ꢀtheꢀ“Information”)ꢀinꢀthisꢀdatasheetꢀareꢀsubjectꢀtoꢀchange.ꢀTheꢀcustomerꢀisꢀresponsibleꢀforꢀcheckingꢀandꢀ

verifying the extent to which the Information contained in this publication is applicable to an order at the time the order is placed.

All Information given herein is believed to be accurate and reliable, but it is presented without guarantee, warranty, or responsibility of any kind, expressed or implied.

Statements of suitability for certain applications are based on KEMET Electronics Corporation’s (“KEMET”) knowledge of typical operating conditions for such applications, but are

notꢀintendedꢀtoꢀconstituteꢀ–ꢀandꢀKEMETꢀspeci ꢀcallyꢀdisclaimsꢀ–ꢀanyꢀwarrantyꢀconcerningꢀsuitabilityꢀforꢀaꢀspeci ꢀcꢀcustomerꢀapplicationꢀorꢀuse.ꢀTheꢀInformationꢀisꢀintendedꢀforꢀuseꢀonlyꢀ

by customers who have the requisite experience and capability to determine the correct products for their application. Any technical advice inferred from this Information or otherwise

provided by KEMET with reference to the use of KEMET’s products is given gratis, and KEMET assumes no obligation or liability for the advice given or results obtained.

Although KEMET designs and manufactures its products to the most stringent quality and safety standards, given the current state of the art, isolated component failures may still

occur. Accordingly, customer applications which require a high degree of reliability or safety should employ suitable designs or other safeguards (such as installation of protective

circuitry or redundancies) in order to ensure that the failure of an electrical component does not result in a risk of personal injury or property damage.

Although all product–related warnings, cautions and notes must be observed, the customer should not assume that all safety measures are indicted or that other measures may not

be required.

C1003_C0G • 4/30/2014 19

型号:	C2225C104K5RACTU
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	2225
包装说明：	, 2225
Reach Compliance Code：	compliant
ECCN代码：	EAR99
HTS代码：	8532.24.00.20
Factory Lead Time：	13 weeks
风险等级：	5.31
电容：	0.1 µF
电容器类型：	CERAMIC CAPACITOR
介电材料：	CERAMIC
高度：	1.1 mm
JESD-609代码：	e3
长度：	6.4 mm
安装特点：	SURFACE MOUNT
多层：	Yes
负容差：	10%
端子数量：	2
最高工作温度：	125 °C
最低工作温度：	-55 °C
封装形状：	RECTANGULAR PACKAGE
封装形式：	SMT
包装方法：	TR, Embossed Plastic, 7 Inch
正容差：	10%
额定（直流）电压（URdc）：	50 V
尺寸代码：	2225
表面贴装：	YES
温度特性代码：	X7R
温度系数：	15% ppm/ °C
端子面层：	Matte Tin (Sn) - with Nickel (Ni) barrier
端子形状：	WRAPAROUND
宽度：	5.6 mm
Base Number Matches：	1

电子百科

产品导航

产品型号C2225C104K2GACTU的Datasheet PDF文件预览

C2225C104K1RACTU相关产品

C2225C104K1RACTU相关文章

IC37:专业IC行业平台