ZN448供应商报价哪里找芯片批发报价原理和应用中文资料-中国IC网-芯三七

DS3013 - 2.2

ZN448/ZN449

8-BIT MICROPROCESSOR COMPATIBLE A-D CONVERTER

The ZN448 and ZN449 are 8-bit successive

approximation A-D converters designed to be easily

interfacedtomicroprocessors. Allactivecircuitryiscontained

on-chip including a clock generator and stable 2.5V bandgap

reference, control logic and double buffered latches with

reference.

BUSY (END OF CONVERSION)

RD (OUTPUT ENABLE)

CLOCK

1

2

3

4

18 DB

17 DB

16 DB

15 DB

0

(LSB)

1

2

3

WR (START CONVERSION)

Only a reference resistor and capacitor, clock resistor and

capacitor and input resistors are required for operation with

either unipolar or bipolar input voltage.

R

EXT

IN

REF IN

REF OUT

5

6

7

14 DB

13 DB

12 DB

4

5

6

V

8

9

11 DB

7

(MSB)

FEATURES

■

Easy Interfacing to Microprocessor, or operates as a

GROUND

10 +VCC (+5V)

'Stand-Alone' Converter

ZN448/9E (DP18)

■

Fast: 9 microseconds Conversion time Guaranteed

Choice of Linearity: 0.5 LSB - ZN448, 1 LSB - ZN449

On-Chip Clock

Choice of On-Chip or External Reference Voltage

Unipolar or Bipolar Input Ranges

BUSY (END OF CONVERSION)

1

2

3

4

18

17

16

15

DB

0

(LSB)

RD (OUTPUT ENABLE)

CLOCK

1

2

3

Commercial Temperature Range

WR (START CONVERSION)

ORDERING INFORMATION

R

EXT

IN

REF IN

REF OUT

5

6

7

14

13

12

DB

4

5

6

Linearity

error (LSB) temperature

Operating

V

Device type

Package

V

ZN448E

ZN449D

ZN449E

0.5

1

0°C to +70°C

DP18

MP18

DP18

V

8

9

11

10

DB

7

(MSB)

GROUND

+VCC (+5V)

1

ZN449D (MP18)

Fig.1 Pin connection - top view

COMPARATOR

5

6

7

ANALOGUE

+

R

EXT

INPUT

-

8-BIT DAC

V

IN

REF

8

V

OUT

REF

3

CLOCK

CK RC OR

2.5V

REFERENCE

GENERATOR

EXT CLOCK

4

1

INTERFACE

AND

CONTROL

LOGIC

WR

SUCCESSIVE

APPROXIMATION REGISTER

9

GROUND

BUSY

10

V

(+5V)

CC

2

3-STATE BUFFERS

RD

11

7

12

13

14

15

16

17

18

0

DB

Fig.2 System diagram

ZN448/9

ABSOLUTE MAXIMUM RATINGS

Supply voltage VCC

+7

Max. voltage, logic and VREF input

Operating temperature range

Storage temperature range

+VCC

0°C to +70°C (MP and DP package)

-55°C to +125°C

ELECTRICAL CHARACTERISTICS (at VCC = 5V, Tamb = 25°C and fCLK = 1.6MHz unless otherwise specified).

Min.

Typ.

Max.

Parameter

Units

Conditions

ZN448

Linearity error

Differential linearity error

Zero transition

-

12

-

15

±0.5

±0.75

18

LSB

mV

DP package

(00000000→00000001)

Full-scale→transition

(11111110 11111111)

2.545

2.550

2.555

V

VREF = 2.560V

ZN449

Linearity error

Differential linearity error

Zero transition

(00000000→00000001)

Full-scale→transition

(11111110 11111111)

-

7

-

12

15

2.550

±1

17

20

2.558

LSB

mV

V

MP package

DP package

V^REF= 2.560V

10

2.542

All Types

Resolution

8

-

1

4.5

-

±3

±6

±2.5

±8

-

5

25

125

-

bits

ppm/°C

µV/°C

V

mA

mW

Linearity temperature coefficient

Differential linearity temperature coefficient

Full-scale temperature coefficient

Zero temperature coefficient

Reference input range

Supply voltage

3

5.5

40

200

Supply current

Power consumption

-

Comparator

Input current

Input resistance

Tail current

Negative supply

Input voltage

-

25

-3

1

100

65

-5

-

µA

kΩ

µA

V

V_IN= +3V, R_EXT= 82kΩ

150

-30

+3.5

V - = -5V

-0.5

-

V

On-chip reference

Output voltage

ZN448

ZN449

2.520

-

4

2.550

0.5

50

-

2.580

2.600

2

-

15

V

R_REF= 390Ω

C_REF= 4µ7

Slope resistance

Ω

V_REFtemperature coefficient

ppm/°C

mA

Reference current

2

ZN448/9

ELECTRICAL CHARACTERISTICS (Cont.)

Min.

Typ.

Max.

Parameter

Units

Conditions

Clock

On-chip clock frequency

Clock frequency temperature coefficient

Clock resistor

Maximum external clock frequency

Clock pulse width

High level input voltage V^IH

Low level input voltage VIL

High level input current IIH

Low level input current IIL

-

1

-

2

1

-

MHz

%/°C

kΩ

MHz

ns

V

µA

+0.5

-

0.9

500

4

-

0.8

800

-500

V_IN= +4V, V_CC= MAX

V_IN= +0.8V, V_CC= MAX

-

Logic (over operating temperature range)

Convert input

High level input voltage VIH

Low level input voltage VIL

High level input current IIH

Low level input current IIL

2

-

0.8

-

V

µA

300

±10

V_IN= +2.4V, V_CC= MAX

V_IN= +0.4V, V_CC= MAX

-

RD input

High level input voltage V^IH

2

-

2.4

-

0.8

-

0.4

-100

1.6

2

-1.5

250

260

100

140

100

-

V

µA

V

Low level input voltage VIL

High level input current IIH

Low level input current IIL

High level output voltage VOH

Low level output voltage VOL

High level output current IOH

Low level output current IOL

Three-state disable output leakage

Input clamp diode voltage

RD input to data output

Enable/disable delay times T^E1

TE0

+150

-300

-

V_IN= +2.4V, V_CC= MAX

V_IN= +0.4V, V_CC= MAX

I_OH= +2.4V, V_CC= MAX

V

I_OL= +0.4V, V_CC= MAX

µA

mA

µA

V

ns

-

V_OUT= +2V

-

180

210

80

110

80

-

180

60

80

60

200

-

TD1

TD0

Convert pulse width tWR

WR input to BUSY output

-

250

GENERAL CIRCUIT OPERATION

The ZN448/9 utilises the successive approximation

technique. Upon receipt of a negative-going pulse at the WR

input the BUSY output goes low, the MSB is set to 1 and all

other bits are set to 0, which produces an output voltage of

V_REF/2from the DAC. This is compared to the input voltage V_IN;

adecisionismadeonthenextnegativeclockedgetoresetthe

During a conversion the RD input will normally be held high to

keep the three-state buffers in their high impedance state.

Data can be read out by taking RD low, thus enabling the

three-state output. Readout is non-destructive.

CONVERSION TIMING

The ZN448/9 will accept a low-going CONVERT pulse, which

can be completely asynchronous with respect to the clock,

and will produce valid data between 7.5 and 8.5 clock pulses

later depending on the relative timing of the clock and

CONVERT signals. Timing diagrams for the conversion are

shown in Fig.3.

V_REF

2

V_REF

2

MSB to 0 if

< V_INor leave it set to 1 if

< V_IN.

Bit 2 is set to 1 on the same clock edge, producing an output

V

V_REF

2

V

from the DAC of ^REFor

4

+

^REFdepending on the state

4

of the MSB. This voltage is compared to V_INand on the next

clock edge a decision is made regarding bit 2, whilst bit 3 is set

to1. Thisprocedureisrepeatedforalleightbits. Ontheeighth

negative clock edge BUSY goes high indicating that the

conversion is complete.

The converter is cleared by a low-going CONVERT pulse,

which sets the most significant bit and results all the other bits

andtheBUSYflag. WhilsttheCONVERTinputislowtheMSB

outputoftheDACiscontinuouslycomparedwiththeanalogue

input, but otherwise the converter is inhibited.

3

ZN448/9

clockfrequency. TheCONVERTinputisnotlockedoutduring

a conversion and if it is oulsed low at any time the converter

will restart.

After the CONVERT input goes high again the MSB decision

is made and the successive approximation routine runs to

completion.

The BUSY output goes high simultaneously with the LSB

decision, attheendofaconversionindicatingdatavalid. Note

that if the three-state data outputs are enabled during a

conversion the valid data will be available at the outputs after

therisingedgeoftheBUSYsignal. If, howevertheoutputsare

not enabled until after BUSY goes high then the data will be

subject to the propagation delay of the three-state buffers.

(See under DATA OUTPUTS).

The CONVERT pulse can be as short as 200ns; however the

MSB must be allowed to settle for at least 550ns before the

MSB decision is made. To ensure that this criterion is met

even with short CONVERT pulses the converter waits, after

theCONVERTinputgoeshigh,forarisingclockedgefollowed

by a falling clock edge, the MSB decision being taken on the

falling clock edge. This ensures that the MSB is allowed to

settle for at least half a clock period, or 550ns at maximum

Fig.3 ZN448/9 timing diagram

4

ZN448/9

Ifafree-runningconversionisrequired,thentheconvertercan

be made to cycle by inverting the BUSY output and feeding it

toWR. Toensurethattheconverterstartsreliablyafterpower-

up an initial start pulse is required. This can be ensured by

using a NOR gate instead of an inverter and feeding it with a

positive-going pulse which can be derived from a simple RC

network that gives a single pulse when power is applied, as

shown in Fig.4a.

whichtimethedatacanbestoredinalatch. Thetimeavailable

for storing data can be increased by inserting delays into the

inverter path.

A timing diagram for the continuous conversion mode is

shown in Fig.3b.

As the BUSY output uses a passive pull-up the rise time of this

output depends on the RC time constant of the pull-up resistor

andloadcapacitance. Inthecontinuousconversionmodethe

use of a 4k7 external pull-up resistor is recommended to

reduce the risetime and ensure that a logic 1 level is reached.

The ADC will complete a conversion on every eighth clock

pulse, with the BUSY output going high for a period

determined by the propagation delay of the NOR gate, during

Fig.4a Circuit for continuous conversion

Fig.4b Timing for continuous conversion

DATA OUTPUTS

Thedataoutputsareprovidedwiththree-statebufferstoallow

connection to a common data bus. An equivalent circuit is

shown in Fig.5. Whilst the RD input is high both output

transistorsareturnedoffandtheZN448/9presentsonlyahigh

impedance load to the bus.

When RD is low the data outputs will assume the logic states

present at the outputs of the successive register.

A test circuit and timing diagram for the output enable/disable

delays are given in Fig.6.

5

ZN448/9

V

CC

500Ω

20k

BITS 1-8

(PINS 11-18)

10k

RD

(PIN 2)

GROUND

Fig.5 Data output

Fig.6 Output enable/disable delays

6

ZN448/9

BUSY OUTPUT

The BUSYoutput, showninFig.7, utilisesapassivepull-upfor

CMOS/TTLcompatibility. ThisallowsuptofourBUSYoutputs

to be wire-ANDed together to form a common interrupt line.

Fig.7 BUSY output

ON-CHIP CLOCK

considerably between devices. For optimum accuracy and

stability of the oscillator frequency, it may be possible to use

a crystal or ceramic resonator with suitable load components,

as shown in Fig.8c. The final option is to overdrive the

oscillator input with an external clock signal from a TTL or

CMOS gate, as shown in Fig.8d.

The on-chip clock operates with only a single external

capacitor connected between pin 3 and ground, as shown in

Fig.8a. A graph of typical oscillator frequency versus

capacitance is given in Fig.9. The oscillator frequency may be

trimmed by means of an external resistor in series with the

capacitor, as shown in Fig.8b. However, due to processing

tolerance, the absolute clock frequency may vary

3

OSC

2kΩ

MAX

9

GND

b) Fixed capacitor + variable resistor

a) Fixed/variable capacitor

V

CC

1.2k

3

4.7k ✱

1MHz

Xtal

2200pF ✱

✱56pF

9

✱

Load circuit to suit

device used

c) Crystal or resonator

d) External TTL or CMOS drive

Fig.8 Clock circuit external components

7

ZN448/9

1MHz

100kHz

10kHz

1kHz

10p

100p

1n

10n

100n

Fig.9 Typical clock frequency v C_CK(R_CK= 0)

ANALOG CIRCUITS

D-A converter

The converter is of the voltage switching type and uses an R-

2R ladder network as shown in Fig.10. Each element is

connected to either 0V or V_{REF IN}by transistor voltage switches

specially designed for low offset voltage (1mV).

V_OSis a small offset voltage that is produced by the device

supply current flowing in the package lead resistance. The

offset will normally be removed by the setting up procedure

and since the offset temperature coefficient is low (8µV/°C)

the effect on accuracy will be neglible.

A binary weighted voltage is produced at the output of the R-

2R ladder.

The D-A output range can be considered to be 0 - V_{REF IN}

through an output resistance R (4k).

D to A output = n (V_{REF IN}-V_OS) + V_OS

256

where n is the digital input to the D-A from the successive

approximation register.

R(4k)

2R

R

D TO A OUTPUT

2R

V

REF IN

(PIN 7)

VOLTAGE

SWITCHES

0 VOLTS

(PIN 9)

V

DB0

DB1

DB6

DB7

OS

Fig.10 R-2R ladder network

8

ZN448/9

REFERENCE

(a) Internal reference

The internal reference is an active bandgap circuit which is

equivalent to a 2.5V Zener diode with a very low slope

impedance (Fig.11). A Resistor (R_REF) should be connected

between pins 8 and 10.

feature saves power and gives excellent gain tracking

between the converters.

Alternatively the internal reference can be used as the

reference voltage for other external circuits and can source or

sink up to 3mA.

The recommended value of 390Ω will supply a nominal

reference current of (5 - 2.5)/0.39=6.4mA. A stabilising/

decoupling capacitor, C_REF(4µ7), is required between pins 8

and 9. For internal reference operation V_{REF OUT}(pin 8) is

connected to V_{REF IN}(pin 7).

(b) External reference

If required an external reference in the range +1.5 to +3.0V

may be connected to V_{REF IN}. The slope resistance of such a

reference source should be less than 2.5Ω, where n is the

n

UP to five ZN448/9's may be driven from one internal

reference, there being no need to reduce R_REF. This useful

number of converters supplied.

V

+5V

CC

(PIN 10)

R

REF

(390)

V

REFOUT

(PIN 8)

C

REF

(0.47µ)

GROUND

(PIN 9)

Fig.11 Internal voltage reference

RATIOMETRIC OPERATION

COMPARATOR

If the output from a transducer varies with its supply then an

external reference for the ZN4448/9 should be derived from

the same supply. The external reference can vary from +1.5

to +3.0V. The ZN448/9 will operate if V_{REF IN}is less than +1.5V

but reduced overdrive to the comparator will increase its delay

and so the conversion time will need to be increased.

The ZN448/9 contains a fast comparator, the equivalent input

circuit of which is shown in Fig.12. A negative supply voltage

is required to supply the tail current of the comparator.

However as this is only 25 to 150µA and need not be well

stabilised it can be supplied by a simple diode pump circuit

driven from the BUSY output.

9

ZN448/9

+5V PIN 10

6k

-

TO LOGIC

HIGH = 'RETAIN BIT'

+

R

IN

A

V

IN

D TO A OUTPUT

(O - V

)

REFIN

PIN 6

4k

PIN 5

R

EXT

I

EXT

V -

Fig.12 Comparator equivalent circuit

Fig.13 Diode pump circuits to supply comparator tail current

10

ZN448/9

Several suitable circuits are shown in Fig.13. The principle of

operation is the same in each case. Whilst the BUSY output

is high, capacitor C1 is charged to about 4-4.5V. During a

conversiontheBUSYoutputgoeslowandtheupperendofC1

is thus also pulled low. The lower end of C1 therefore applies

about -4V to R2, thus providing the tail current for the

comparator. The time constant R2. C1 is chosen according

to the clock frequency so that droop of the capacitor voltage is

not significant during a conversion.

is high for greater than one converter clock period then the

circuitofFig.13awillsuffice. Ifthisisnotthecase,forexample,

in the continuous conversion mode, then the circuits of Figs.

13b and 13c are recommended, since these can pump more

current into the capacitor.

Where several ZN448/9's are used in a system the self-

oscillating diode pump circuit Fig.14 is recommeded.

Alternatively, if a negative supply is available in the system

then this may be utilised. A list of suitable resistor values for

different supply voltages is given in Table 1.

The constraint on using this type of circuit is that C1 must be

recharged whilst the BUSY output is high. If the BUSY output

330

5V

470

IN914

100n

-3.5V

100n

22n

IN914

Fig.14 Diode pump circuit to supply comparator tail current for up to five ZN448/9's

V – (volts)

R_EXT(kΩ)

3

5

47

82

10

12

15

20

25

30

150

180

220

330

390

470

Table 1

11

ZN448/9

ANALOG INPUT RANGES

The basic connection of the ZN448/9 shown in Fig.15 has an

analogue input range 0 to V_{REF IN}which, in some applications,

may be made available from previous signal conditioning/

scaling circuits. Input voltage ranges greater than this are

accommodated by providing an attenuator on the comparator

input, whilst for smaller input ranges the signal must be

amplified to a suitable level.

Bipolar input ranges are accommodated by off-setting the

analogue input input range so that the comparator always

sees a positive input voltage.

DIGITAL OUTPUTS

LSB

MSB

DB7

V

CC

(+5V)

1

2

3

4

5

6

DB0

18

17

16

15

14

13

12

11

10

R

REF

(390Ω)

1

2

3

4

5

6

7

8

9

V

IN

R

(4k)

EXT

(82k)

IN

C

REF

(4µ7)

BUSY

RD

CK

WR

V-

(-5V)

A

V

REFIN REFOUT

GND

(0V)

IN

NOMINAL A RANGE = 0 TO V

IN

REFIN

Fig.15 External components for basic operation

12

ZN448/9

UNIPOLAR OPERATION

The general connection for unipolar operation is shown in

Fig.16.

R₁

R₂

A_INFS = 1 +

, V_{REF IN}= G.V_{REF IN}.

To match the ladder resistance R₁/R₂(R_IN) = 4k.

The values of R₁and R₂are chosen so that V_IN= V_{REF IN}when

the analog input (A_IN) is at full-scale.

The required nominal values of R₁and R₂are given by R₁=

4Gk, R₂= 4G k

G-1

The resulting full-scale range is given by:

A

V

REF IN

IN

1M

ZERO

ADJUST

R1

680k

7

V

IN

6

ZN448/9

9

GROUND

R2

Fig.16 General unipolar input connections

Zero adjustment

Using these relationships a table of nominal values of R₁and

R₂can be constructed for V_{REF IN}= 2.5V.

Due to offsets in the DAC and comparator the zero (0 to 1)

code transition would occur with typically 15mV applied to the

comparator input, which correpsonds to 1.5LSB with a 2.56V

reference.

Input range

R₁

R₂

G

+5V

+10V

8k

16k

8k

5.33k

2

4

Zero adjustment must therefore be provided to set the zero

transition to its correct value of +0.5LSB or 5mV with a 2.56V

reference. Thisisachievedbyapplyinganadjustablepositive

offset to the comparator input via P2 and R3. The values

shown are suitable for all input ranges greater than 1.5 times

Gain adjustment

Due to tolerance in R₁and R₂, tolerance in V_REFand the gain

(full-scale) error of the DAC, some adjustment should be

incorporated into R₁to calibrate the full-scale of the converter.

When used with the internal reference and 2% resistors a

preset capable of adjusting R₁by at least ±5% of its nominal

value is suggested.

V_{REF IN}

.

Practical circuit values for +5 and +10V input ranges are given

in Fig.17, which incorporates both zero and gain adjustments.

13

ZN448/9

A

V

A

V

REF IN

IN

REF IN

IN

P2

P1 5k

GAIN

1M

ZERO

P1 10k

GAIN

1M

ZERO

ADJUST

R1 5k6

680k

R1 11k

R2 5k6

680k

R3

TO PIN 6

± 2% RESISTORS

R2 8k2

±20% POTENTIOMETERS

+5V FULL-SCALE

+10V FULL-SCALE

Fig.17 Unipolar operation component values

Unipolar adjustment prodedure

(iii) Apply 0.5LSB to A_INand adjust zero until 8 bit just flickers

between 0 and 1 with all other bits at 1.

(i) Apply continuous convert pulses at intervals long enough

to allow a complete conversion and monitor the digital

outputs.

(ii) Applyfull-scaleminus1.5LSB toA_INandadjustoff-setuntil

the bit 8 (LSB) output just flickers between 0 and 1 with all

other bits at 0.

Unipolar setting up points

FS - 1.5LSB

0.5LSB

Input range, +FS

4.9707V

9.9414V

9.8mV

19.5mV

+5V

+10V

1LSB = FS

256

Bipolar logic coding

Output code

Analogue input (A_IN)

(offset binary)

(Nominal code centre value)

11111111

11111110

11000000

10000001

10000000

01111111

01000000

00000001

00000000

FS - 1LSB

FS - 2LSB

0.75FS

0.5FS + 1LSB

0.5FS

0.5FS - 1LSB

0.25FS

1LSB

0

14

ZN448/9

BIPOLAR OPERATION

For bipolar operation the input to the ZN448/9 is offset by half

full-scale by connecting a resistor R₃between V_{REF IN}and V_IN

(Fig.18).

A

V

REF IN

IN

R1

R3

7

V

IN

6

ZN448/9

9

GROUND

R2

Fig.18 Basic bipolar input connection

When A_IN= -FS, V_INneeds to be equal to zero.

When A_IN= +FS, V_INneeds to be equal to V_{REF IN}

Thus the nominal values of R₁, R₂, R₃are given by R₁= 8 Gk,

R₂= 8G/(G - 1)k, R₃= 8k.

.

A bipolar range of ±V_{REF IN}(which corresponds to the basic

unipolar range 0 to +V_{REF IN}) results if R₁= R₃= 8k and R₂= ∞.

If the full-scale range is ± G. V_{REF IN}then R₁= (G - 1). R₂and

R₁= G. R₃fulfil the required conditions.

Assuming the V_{REF IN}= 2.5V the nominal values of resistors for

To match the ladder resistance, R₁/R₂/R₃(=R_IN) = 4k.

±5 and ±10V input ranges are given in the following table.

R₃

Input range

R₁

R₂

G

8k

+5V

+10V

16k

32k

16k

10.66k

2

4

Minusfull-scale(offset)issetbyadjustingR₁aboutitsnominal

value relative to R₃. Plus full-scale (gain) is set by adjusting R₂

relative to R₁.

Note that in the±5V case R₃has been chosen as 7.5k (instead

of 8.2k) to obtain a more symmetrical range of adjustment

using standard potentiometers.

Practical circuit realisations are given in Fig.19.

15

ZN448/9

A

V

A

V

IN

REF

IN

REF

5k

OFFSET

ADJUST

10k

OFFSET

ADJUST

7k5

8k2

13k

27k

TO PIN 6

5k

GAIN

ADJUST

± 2% RESISTORS

±20% POTENTIOMETERS

13k

8k2

±5VOLTS FULL SCALE

±10VOLTS FULL SCALE

Fig.19 Bipolar operation component values

Bipolar adjustment prodedure

(iii) Apply +(FS -1.5LSB) to A_INand adjust gain until the 8 bit

just flickers between 0 and 1 with all other bits at 1.

(i) Apply continuous SC pulses at intervals long enough to

allow a complete conversion and monitor the digital

outputs.

(iv) Repeat step (ii).

(ii) Apply -(FS -0.5LSB) to A_INand adjust off-set until the bit 8

(LSB)outputjustflickersbetween0and1withallotherbits

at 0.

Bipolar setting up points

+(FS -1.5LSB)

-(FS -0.5LSB)

Input range, ±FS

+4.9414V

+9.8828V

-4.9805V

-9.9609V

+5V

+10V

1LSB =2FS

256

Bipolar logic coding

Output code

Analogue input (A_IN)

(offset binary)

(Nominal code centre value)

11111111

11111110

11000000

10000001

10000000

01111111

01000000

00000001

00000000

+(FS - 1LSB)

+(FS - 2LSB)

+0.5FS

+1LSB

0

-1LSB

-0.5FS

-(FS - 1LSB)

-FS

16

ZN448/9

17

For more information about all Zarlink products

visit our Web Site at

www.zarlink.com

Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”)

is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or

use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from

such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or

other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use

of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned

by Zarlink.

This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part

of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other

information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability,

performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee

that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any

equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily

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2

Purchase of Zarlink s I C components conveys a licence under the Philips I C Patent rights to use these components in and I C System, provided

2

that the system conforms to the I C Standard Specification as defined by Philips.

Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

TECHNICAL DOCUMENTATION - NOT FOR RESALE

型号:	ZN448D
生命周期：	Transferred
IHS 制造商：	PLESSEY SEMICONDUCTORS
包装说明：	,
Reach Compliance Code：	unknown
风险等级：	5.81
Base Number Matches：	1

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