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Advanced Differential

ZSC31050

Sensor Signal Conditioner

Datasheet

Brief Description

Features

ZSC31050 is a CMOS integrated circuit for highly accurate amp-

lification and sensor-specific correction of bridge sensor and

temperature sensor signals. The device provides digital com-

pensation of sensor offset, sensitivity, temperature drift, and non-

linearity via a 16-bit RISC microcontroller running a polynomial

correction algorithm.

.

Digital compensation of sensor offset, sensitivity, temperature

drift, and nonlinearity

.

Accommodates nearly all resistive bridge sensor types (signal

spans from 1mV/V up to 275mV/V)

.

Digital one-pass calibration: quick and precise

Selectable compensation temperature source: bridge,

thermistor, or internal or external diode

The ZSC31050 accommodates virtually any bridge sensor type

(e.g., piezo-resistive, ceramic thick-film, or steel membrane

based). In addition, it can interface to a separate temperature

sensor. The bi-directional digital interfaces (I²C, SPI, and

ZACwire™) can be used for a simple PC-controlled one-pass

calibration procedure to program a set of calibration coefficients

into an on-chip EEPROM. A specific sensor and a ZSC31050 can

be mated digitally: fast, precise, and without the cost overhead

associated with trimming by external devices or laser. The

ZACwire™ interface enables an end-of-line calibration of the

sensor module.

.

Output options: voltage (0 to 5V), current (4 to 20mA), PWM,

I²C, SPI, ZACwire™ (one-wire interface), alarm

Adjustable output resolution (up to 15 bits) versus sampling

rate (up to 3.9kHz)

.

Current consumption: 2.5mA (typical)

Selectable bridge excitation: ratiometric voltage, constant

voltage, or constant current

.

Input channel for separate temperature sensor

Sensor connection and common mode check (sensor aging

detection)

Typical applications for the ZSC31050 include industrial, medical,

and consumer products. It is specifically engineered for most

resistive bridge sensors; e.g., sensors for measuring pressure,

force, torque, acceleration, angle, position, and revolution.

.

AEC-Q100 qualification (temperature grade 0)

Physical Characteristics

.

Operation temperature -40°C to +125°C (-40°C to +150°C

de-rated, depending on product version)

Benefits

.

No external trimming components required

Supply voltage: 2.7V to 5.5V;

with external JFET: 5V to 48 V

.

PC-controlled configuration and calibration via digital bus

interface – simple, low cost

Available in 16-SSOP package or as die

.

High accuracy (±0.1% FSO @ –25 to 85°C;

±0.25% FSO @ –40 to 125°C) *

Basic Circuit Diagram

Available Support

VCC

OUT

.

Evaluation kit available

Support for industrial mass calibration available

Sensor

Module

Quick circuit customization possible for large production

volumes

ZSC31050

GND

* Digital output signal.

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February 13, 2017

ZSC31050 Datasheet

ZSC31050 Block Diagram

Ext. Temp. Sens.

IR_TEMP

VBR

SCL

SDA

CTRL-REGS

SIF

+

PCOMP

ADC Mode

Offset

Shift

Gain

Factor

Temp. Sens.

Select

RAM

VINP

VINN

OUT /

OWI



PGA

MUX

ADC

CMC

DAC

FIO1

FIO2

Analog Front-End (AFE)

Int. Temp. Sensor

IO1

IO2

EEPROM

PWM

Digital Section

Interfaces

External

Sensor Bridge

Temperature

Sensor

IN3

Analog

Digital

Interface

Typical Applications:

Consumer Goods

Industrial Applications

Portable Devices

Automotive Sensors *

.

Weight scales

Flow meters

Strain gauges

Load meters

HVAC

.

4-20mA transmitters

Intelligent sensor networks

Process automation

Factory automation

.

Altimeters

.

Oil pressure

.

Blood pressure

monitors

.

Temperature sensing

Strain gauges

* AEC-Q100 qualified

Ordering Information(See section 8 in the data sheet for additional options.)

Product Sales Code

Description

Package

ZSC31050FEB

ZSC31050 Die — Temperature range: -40°C to +150°C

Unsawn on Wafer

Sawn on Wafer Frame

ZSC31050FEC

ZSC31050FEG1

ZSC31050KITV3P1

ZSC31050 16-SSOP — Temperature range: -40°C to +150°C Add “-T” for tube or “-R” for reel to sales code

ZSC31050 SSC Evaluation Kit V3.1: ZSC31050 Evaluation Board, SSC Communication Board, SSC Sensor

Replacement Board, five ZSC31050 16-SSOP samples. Software is downloadable.

ZSC31050MCSV1P1 Modular Mass Calibration System (MSC) V1.1 for ZSC31050: Four Mass Calibration Boards; SSC

Communication Board; four ZSC31050 Mass Calibration Reference Boards, each with a ZSC31050 sample

mounted; 30m 10-wire flat cable; 100 connectors. Software is downloadable.

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138

Sales

Tech Support

www.IDT.com/go/support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

www.IDT.com

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance

specifications and operating parameters of the described products are determined in an independent state and are not guarante ed to perform the same way when installed in customer products. The

information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitab ility of IDT's products for any particular purpose,

an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual

property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be

reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the

property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of

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February 13, 2017

ZSC31050 Datasheet

Contents

1. Electrical Characteristics ..............................................................................................................................................................................5

1.1 Absolute Maximum Ratings ...............................................................................................................................................................5

1.2 Operating Conditions .........................................................................................................................................................................5

1.3 Inherent Characteristics .....................................................................................................................................................................7

1.3.1

1.3.2

Cycle Rate versus ADC Resolution ....................................................................................................................................8

PWM Frequency .................................................................................................................................................................8

1.4 Electrical Parameters.........................................................................................................................................................................9

1.4.1

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.4.7

Supply/Regulation..............................................................................................................................................................9

Analog Front End................................................................................................................................................................9

DAC and Analog Output (OUT Pin) ....................................................................................................................................9

PWM Output (OUT Pin, IO1 Pin) ........................................................................................................................................9

Temperature Sensors (IR_TEMP Pin) ................................................................................................................................9

Digital Outputs (IO1, IO2, OUT Pins in Digital Mode) .......................................................................................................10

System Response.............................................................................................................................................................10

1.5 Interface Characteristics ..................................................................................................................................................................11

1.5.1

1.5.2

Multiport Serial Interfaces (I²C, SPI) .................................................................................................................................11

One-Wire Serial Interface (ZACwire™).............................................................................................................................11

2. Circuit Description ......................................................................................................................................................................................12

2.1 Signal Flow ......................................................................................................................................................................................12

2.2 Application Modes............................................................................................................................................................................13

2.3 Analog Front-End (AFE)...................................................................................................................................................................14

2.3.1

2.3.2

2.3.3

2.3.4

Programmable Gain Amplifier (PGA)................................................................................................................................14

Extended Zero Point Compensation (XZC).......................................................................................................................14

Measurement Cycle Performed by Multiplexer .................................................................................................................16

Analog-to-Digital Converter...............................................................................................................................................16

2.4 System Control ................................................................................................................................................................................18

2.5 Output Stage....................................................................................................................................................................................18

2.5.1

2.5.2

2.5.3

Analog Output...................................................................................................................................................................20

Comparator Module (ALARM Output)...............................................................................................................................20

Serial Digital Interface.......................................................................................................................................................20

2.6 Voltage Regulator ............................................................................................................................................................................21

2.7 Watchdog and Error Detection.........................................................................................................................................................21

3. Application Circuit Examples......................................................................................................................................................................22

4. ESD/Latch-Up-Protection ...........................................................................................................................................................................23

5. Pin Configuration and Package..................................................................................................................................................................24

6. Reliability ....................................................................................................................................................................................................25

7. Customization.............................................................................................................................................................................................25

8. Ordering Information...................................................................................................................................................................................26

9. Related Documents....................................................................................................................................................................................26

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February 13, 2017

ZSC31050 Datasheet

10. Glossary .....................................................................................................................................................................................................27

11. Document Revision History ........................................................................................................................................................................28

List of Figures

Figure 1. Block Diagram of the ZSC31050.......................................................................................................................................................12

Figure 2. Measurement Cycle ZSC31050 ........................................................................................................................................................16

Figure 3. Application Example 1.......................................................................................................................................................................22

Figure 4. Application Example 2.......................................................................................................................................................................22

Figure 5. Application Example 3.......................................................................................................................................................................22

Figure 6. Application Example 4.......................................................................................................................................................................22

Figure 7. Application Example 5.......................................................................................................................................................................23

Figure 8. Pin Configuration...............................................................................................................................................................................25

List of Tables

Table 1. Adjustable Gains, Resulting Sensor Signal Spans, and Common Mode Ranges .............................................................................14

Table 2. Extended Zero Point Compensation (XZC) Range............................................................................................................................15

Table 3. Output Resolution versus Sample Rate.............................................................................................................................................17

Table 4. Output Configurations Overview........................................................................................................................................................18

Table 5. Analog Output Configuration .............................................................................................................................................................20

Table 6. Pin Configuration...............................................................................................................................................................................24

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February 13, 2017

ZSC31050 Datasheet

1. Electrical Characteristics

1.1 Absolute Maximum Ratings

The absolute maximum ratings are stress ratings only. The ZSC31050 might not function or be operable above the recommended operating

conditions. Stresses exceeding the absolute maximum ratings might also damage the device. In addition, extended exposure to stresses

above the recommended operating conditions might affect device reliability. IDT does not recommend designing to the “Absolute Maximum

Ratings.”

No.

Parameter

Digital supply voltage

Analog supply voltage

Symbol

VDD_MAX

VDDA_MAX

Conditions

Min

-0.3

Max

6.5

Unit

V DC

1.1.1

To VSS

1.1.2

1.1.3

6.5

Voltage at all analog and digital I/O

pins except FBP, SDA, SCL (see

1.1.4, 1.1.5, and 1.1.6)

V_{A_I/O}

,

VDDA+0.3

V_{D_I/O}

1.1.4

1.1.5

1.1.6

1.1.7

Voltage at FBP pin

Voltage at SDA pin

Voltage at SCL pin

Storage temperature

V_{FBP_MAX}

V_{SDA_MAX}

V_{SCL_MAX}

T_STG

4mA to 20mA – Interface

I²C mode only

-1.2

-0.3

-45

VDDA+0.3

5.5

V DC

C

I²C mode only

5.5

150

1.2 Operating Conditions

Unless otherwise noted, voltages are relative to VSS and analog-to-digital conversion = 2^ndorder, resolution = 13 bits, gain  210,

f_clk 2.25MHz.

For specifications marked with an asterisk (*), there is no measurement in mass production—the parameter is guaranteed by design and/or

quality observations.

Note: See important notes at the end of the table.

No.

Parameter

Symbol

Conditions

Min

Typical

Max

Unit

1.2.1.1 TQE ambient

temperature range for part

numbers ZSC31050xExx

1.2.1.2 TQA ambient

temperature range for part

numbers ZSC31050xAxx

1.2.1.3 TQI ambient

T_{AMB_TQE}

Operation life time < 1000h

@ 125C to 150C

-40

150

C

T_{AMB_TQA}

T_{AMB_TQI}

T_{AMB_EEP}

-40

-25

125

85

C

1.2.1

temperature range for part

numbers ZSC31050xIxx

1.2.2

1.2.3

1.2.4

Ambient temperature

EEPROM programming

85

EEPROM programming

cycles

100

Data retention (EEPROM)

15

years

Average temp. < 85C

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February 13, 2017

ZSC31050 Datasheet

No.

Parameter

Symbol

VDDA

Conditions

Ratiometric mode

Min

2.7

4.5

Typical

Max

5.5

Unit

V DC

1.2.5

Analog supply voltage

1.2.6

Analog supply voltage

advanced performance

VDDA_ADV

5.5

1.2.7

Digital supply voltage

VDD

Externally powered

1.05

VDDA

V DC

2.7

1.2.8

1.2.9

External supply voltage

Common mode input range^[b]

Input voltage FBP pin

V_SUPP

Voltage Regulator Mode

with external JFET ^[a]

VDDA +

2V

V_{IN_CM}

Depends on gain adjust;

refer to section 2.3.1

0.21

0.76

V_{ADC_REF}

1.2.10

1.2.11

V_{IN_FBP}

R_BR

-1

VDDA

25.0

V DC

k

Sensor bridge resistance ^[c]

(over full temperature range)

3.0

5.0

R_{BR_CL}

Current loop interface,

4 to 20mA

25.0

k

1.2.12

1.2.13

1.2.14

1.2.15

1.2.16

1.2.17

Reference resistor for bridge

current source *

R_{BR_REF}

C_VDDA

Bridge current

I_BR= VDDA / (16·R_{BR_REF}

0.07

50

0

R_BR

nF

)

Stabilization capacitor *

External capacitor between

VDDA and VSS

100

470

50

VDD stabilization capacitor*^{, [d]}

C_VDD

Between VDD and VSS,

external

nF

Maximum load capacitance

allowed at OUT ^[e]

C_{L_OUT}

R_{L_OUT}

C_{L_VGATE}

Output Voltage Mode

nF

Minimum load resistance

allowed

Output Voltage Mode

2

k

Maximum load capacitance

allowed at VGATE

Total capacitance relative to

all potentials

10

nF

[a] Maximum depends on the breakdown voltage of the external JFET; refer to the application recommendations in the ZSC31050 Application

Note—0-10V Output.

[b] V_{ADC_REF}: reference voltage of the analog-to-digital converter (VBR or VDDA).

[c] No minimum limitation with an external connection between VDDA and VBR.

[d] Lower stabilization capacitors can increase noise level at the output.

[e] If the maximum is used, take into consideration the special requirements of the ZACwire™ interface stated in the ZSC31050 Functional

Description, section 4.3.

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February 13, 2017

ZSC31050 Datasheet

1.3 Inherent Characteristics

For specifications marked with an asterisk (*), there is no measurement in mass production—the parameter is guaranteed by design and/or

quality observations.

No.

1.3.1

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Selectable input span, bridge

sensor measurement

V_{IN_SP}

Refer to section 2.3.1.

2

280

mV/V

1.3.2

1.3.3

Analog offset comp range

(6 bit setting)

-20

-25

9

20

25

15

Counts

Bits

Maximum bias current ^[a]

3-bit setting ^[b]

Analog-to-digital conversion

(ADC) resolution

r_ADC

1.3.4

1.3.5

ADC input range

Range

r_DAC

10

90

%VDDA

Bits

Digital-to-analog conversion

(DAC) resolution

At analog output

11

1.3.6

1.3.7

PWM resolution

r_PWM

I_TS

9

8

12

40

Bits

Bias current for external

temperature diodes

18

3200

2

A

1.3.8

1.3.9

Sensitivity internal temperature

diode ^[c]

ST_{T_SI}

f_CLK

Raw values without conditioning

Guaranteed adjustment range

2800

1

3600

4

ppm

FS/K

Clock frequency*

MHz

[a] Set configuration word ADJREF:BCUR ( bits 4-6) to 111 (for details, see the ZSC31050 Functional Description).

[b] 15-bit resolution is not applicable for 1^storder ADC and not recommended for sensors with high nonlinearity behavior.

[c] FS = Full scale.

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February 13, 2017

ZSC31050 Datasheet

1.3.1 Cycle Rate versus ADC Resolution

The following specifications are guaranteed by design and/or quality observations.

Important note: Combining first-order configuration of the ADC with 15-bit resolution is not allowed.

Conversion Cycle f_CYC

Resolution

r_ADC

ADC Order

f_CLK=2MHz

[Hz]

f_CLK=2.25MHz

(O_ADC

)

[Bit]

9

[Hz]

1465

879

1302

781

10

11

12

13

14

11

12

13

14

15

434

488

1

230

259

115

129

59

67

3906

1953

977

4395

2197

1099

2

1.3.2 PWM Frequency

The following specifications are not measured in mass production; they are guaranteed by design and/or quality observations.

PWM Frequency in Hz at 2MHz Clock ^[a]

Clock Divider

PWM Frequency in Hz at 2.25MHz Clock ^[b]

Clock Divider

PWM

Resolution

r_PWM[Bit]

1

0.5

1953

977

488

244

0.25

977

488

244

122

0.125

488

244

122

61

1

0.5

2197

1099

549

0.25

1099

549

0.125

549

275

137

69

9

3906

1953

977

4395

2197

1099

549

10

11

12

275

488

275

137

[a] Internal RC oscillator: coarse adjustment to 1MHz, 2MHz, and 4MHz, fine-tuning +/- 25%; external clock is also possible.

[b] Internal RC oscillator: coarse adjustment to 1.125MHz, 2.25MHz, and 4.5MHz, fine-tuning +/- 25%; external clock is also possible.

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February 13, 2017

ZSC31050 Datasheet

1.4 Electrical Parameters

Unless otherwise noted, voltages are relative to VSS and analog-to-digital conversion = 2^ndorder, resolution = 13 bits, gain 210,

f_clk2.25MHz.

Note: See important notes at the end of the table.

No.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

1.4.1 Supply/Regulation

1.4.1.1

Supply current

I_SUPP

Without bridge and load current,

bias adjustment  4, f_CLK 2.4MHz

2.5

2.0

4

mA

1.4.1.2

Supply current for current

loop

I_{SUPP_CL}

Without bridge current,

f_CLK 1.2MHz,

bias ^[a]adjustment  1

2.75

1.4.1.3

Temperature coefficient

voltage reference *

TC_REF

-200

-2 to -10

0.025

±50

200

ppm/K

nA

1.4.2 Analog Front End

1.4.2.1

Parasitic differential input

offset current *

I_{IN_OFF}

Temperature range =

T_{AMB_TQI}(-40 to 85C)

2 to 10

0.975

1.4.3 DAC and Analog Output (OUT Pin)

1.4.3.1

Output signal range ^[b]

V_{OUT_SR}

Voltage Mode, R_LOAD> 2KΩ

VDDA_ADV

VDDA

LSB

Temperature range = T_{AMB_TQI}

1.4.3.2

Output DNL

DNL_OUT

VDDA_ADV

0.95

4

Temperature range = T_{AMB_TQI}

1.4.3.3

1.4.3.4

Output INL ^[c]

INL_OUT

SR_OUT

LSB

Output slew rate *

Voltage Mode

0.1

V/s

Load capacitance < 20nF

Using conditions of 1.4.3.1

1.4.3.5

1.4.3.6

Short circuit current *

I_{OUT_max}

5

0

10

20

1

mA

Addressable output signal

range *

V_{OUT_ADR}

2048 steps

VDDA

1.4.4 PWM Output (OUT Pin, IO1 Pin)

1.4.4.1

PWM high voltage

V_{PWM_H}

V_{PWM_L}

SR_PWM

0.9

15

VDDA

V/s

Load resistance > 10k

Load capacitance < 1nF

1.4.4.2

PWM low voltage

0.1

1.4.4.3

PWM output slew rate *

1.4.5 Temperature Sensors (IR_TEMP Pin)

1.4.5.1

Sensitivity external diode /

resistor measurement

ST_{TS_E}

At r_ADC= 13 bits

75

210

µV/LSB

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February 13, 2017

ZSC31050 Datasheet

No.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

1.4.6 Digital Outputs (IO1, IO2, OUT Pins in Digital Mode)

1.4.6.1

Output high level

Output low level

Output current *

V_{DOUT_H}

V_{DOUT_L}

I_DOUT

0.9

4

VDDA

mA

Load resistance > 1 k

1.4.6.2

1.4.6.3

0.1

1.4.7 System Response

1.4.7.1

1.4.7.2

1.4.7.3

Startup time ^[d]

t_STA

t_RESP

Power-on to 1^stmeasurement result at

output

2

5

ms

Response time *

66% change in input signal; refer to

Table 3 for f_CON

1.66

2.66

3.66

1/f_CON

Overall accuracy

AC_OUT

0.10

0.25

0.50

10

%

T_{AMB_TQI}(-25 to 85 C) & VDDA_ADV

T_{AMB_TQA}(-40 to 125 C) & VDDA_ADV

T_{AMB_TQE}(-40 to 150 C) & VDDA_ADV

(deviation from ideal line

including INL, gain, and

offset errors) *^{, [e]}

%

1.4.7.4

1.4.7.5

1.4.7.6

Analog output noise:

peak-to-peak *

V_{NOISE, PP}

mV

Shorted inputs, gain  210

bandwidth  10kHz

Analog output noise:

RMS *

V_{NOISE, RMS}

3

mV

Shorted inputs, gain  210

bandwidth  10kHz

Ratiometricity error

RE_{OUT_5V}

RE_{OUT_3V}

±5% respectively 1000ppm ±10% (5V)

±5% respectively 200ppm ±10% (3V)

500

ppm

1000

[a] Recommended bias adjustment  4; note the application recommendations and power consumption adjustment constraints given in the

ZSC31050 Application Note—Current Loop.

[b] De-rated performance in lower part of supply voltage range (2.7 to 3.3V): 2.5 to 5 %VDDA and 95 to 97.5%VDDA.

[c] Output linearity and accuracy can be enhanced by an additional analog output stage calibration.

[d] OWI, start window disabled (depending on resolution and configuration, start routine begins approximately 0.8ms after power-on).

[e] Accuracy better than 0.5% requires offset and gain calibration for the analog output stage; parameter only for ratiometric output. The current

loop application is verified and validated for 5V operation only and external supply > 7V (upper limit is dependent on the external components

used). Accuracy and temperature range should be validated based on the schematic design used. Refer to the ZSC31050 Application Note—

Current Loop for more information.

*

For specifications marked with an asterisk (*), there is no measurement in mass production—the parameter is guaranteed by design and/or quality observations.

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February 13, 2017

ZSC31050 Datasheet

1.5 Interface Characteristics

No.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

1.5.1 Multiport Serial Interfaces (I²C, SPI)

1.5.1.1

Input high level ^[a]

V_{I2C_IN_H}

0.7

-

1

VDDA

V DC

VDDA

pF

5.5

0.3

0.1

400

1.5.1.2

1.5.1.3

1.5.1.4

Input low level

V_{I2C_IN_L}

V_{I2C_OUT_L}

C_SDA

0

Output low level

Load capacitance at the

SDA pin

1.5.1.5

Clock frequency at the

SCL pin ^[b]

f_SCL

f_CLK≥ 2MHz

400

kHz

1.5.1.6

1.5.1.7

Pull-up resistor

R_{I2C_PU}

C_{I2C_IN}

500



Input capacitance

(each pin)

Also valid for SPI.

10

pF

1.5.2 One-Wire Serial Interface (ZACwire™)

1.5.2.1

OWI start window

t_{OWI_start}

20

ms



1.5.2.2

1.5.2.3

Pull-up resistance master

OWI load capacitance

R_{OWI_PU}

330

C_{OWI_LOAD}

0.08

0.2

t_{OWI_BIT}/

20s < t_{OWI_BIT}< 100s

R_{OWI_PU}

VDDA

1.5.2.4

1.5.2.5

Voltage level low

Voltage level high

V_{OWI_L}

V_{OWI_H}

0.75

[a] The maximum value in V DC is independent from VDDA in I²C Mode.

[b] Internal clock frequency f_CLKmust be at least 5 times higher than the communication clock frequency.

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February 13, 2017

ZSC31050 Datasheet

2. Circuit Description

Note: This data sheet provides specifications and a general overview of ZSC31050 operation. For details of operation, including configuration

settings and related EEPROM registers, refer to the ZSC31050 Functional Description.

2.1 Signal Flow

The ZSC31050’s signal path includes both analog (shown in pink in Figure 1) and digital (blue) sections. The analog path is differential; i.e.,

the differential bridge sensor signal is handled internally via two signal lines that are symmetrical around a common mode potential (analog

ground = VDDA/2), which improves noise rejection.

Therefore it is possible to amplify positive and negative input signals, which are located in the common mode range of the signal input.

Figure 1. Block Diagram of the ZSC31050

Ext. Temp. Sens.

IR_TEMP

VBR

SCL

SDA

CTRL-REGS

SIF

+

PCOMP

ADC Mode

Offset

Shift

Gain

Factor

Temp. Sens.

Select

RAM

VINP

VINN

OUT /

OWI



PGA

MUX

ADC

CMC

DAC

FIO1

FIO2

Analog Front-End (AFE)

Int. Temp. Sensor

IO1

IO2

EEPROM

PWM

Digital Section

Interfaces

External

Sensor Bridge

Temperature

Sensor

IN3

Analog

Digital

Interface

PGA

Programmable Gain Amplifier

Multiplexer

MUX

ADC

CMC

DAC

FIO1

FIO2

SIF

Analog-to-Digital Converter

Calibration Microcontroller

Digital-to-Analog Converter

Flexible I/O 1: Analog Out (voltage/current), PWM2, ZACwire™ (one-wire-interface)

Flexible I/O 2: PWM1, SPI Data Out, SPI Slave Select, Alarm1, Alarm2

Serial interface: I²C Data I/O, SPI Data In, Clock

PCOMP

Programmable Comparator

EEPROM Nonvolatile Memory for Calibration Parameters and Configuration

TS

On-Chip Temperature Sensor (pn-junction)

Memory for Correction Formula and Algorithm

PWM Module

ROM

PWM

The differential signal from the bridge sensor is pre-amplified by the programmable gain amplifier (PGA). The multiplexer (MUX) transmits the

signals from the bridge sensor, external diode, or separate temperature sensor to the ADC in a specific sequence (the internal pn-junction

(TS) can be used instead of the external temperature diode). Next, the ADC converts these signals into digital values.

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ZSC31050 Datasheet

The digital signal correction takes place in the calibration microcontroller (CMC). It is based on a special correction formula located in the

ROM and sensor-specific coefficients (stored in the EEPROM during calibration). Depending on the programmed output configuration, the

corrected sensor signal is output as an analog value, a PWM signal, or a digital value in the format of SPI, I²C, or ZACwire™. The output

signal is provided at two flexible I/O modules (FIO) and at the serial interface (SIF). The configuration data and the correction parameters can

be programmed into the EEPROM via the digital interfaces.

The modular circuit concept used in the design of the ZSC31050 allows fast customization of the IC for high-volume applications if needed.

Circuit blocks and functions can be added or removed, which can reduce the die size (see section 7 for more details).

2.2 Application Modes

For each application, a configuration set must be established (generally prior to calibration) by programming the on-chip EEPROM regarding

to the following modes:

.

Sensor channel

—

Sensor mode: ratiometric voltage or current supply mode.

Input range: the gain of the analog front end must be chosen with respect to the maximum sensor signal span, which also requires

adjusting the zero point of the ADC.

—

Additional offset compensation, the Extended Zero-Point Compensation (XZC), must be enabled if required; e.g., if the sensor offset

voltage is close to or larger than the sensor span.

Resolution/response time: The ADC must be configured for resolution and conversion settings (1st or 2nd order). These settings

influence the sampling rate, signal integration time, and, as a result, the noise immunity.

Polarity of the sensor bridge inputs: this allows inverting the sensor bridge inputs

.

Analog output

—

Choice of output type (voltage value, current loop, or PWM) for output register 1.

Optional additional output register 2: PWM via IO1 pin or alarm out module via IO1 or IO2 pin.

.

Digital communication: The protocol and its parameters must be selected.

Temperature

—

The temperature sensor type for the temperature correction must be chosen (only main channel (T1) is usable for correction).

Optional: a secondary temperature sensor (T2) can be chosen as a second sensor output.

.

Supply voltage: For non-ratiometric output, the voltage regulation must be configured.

Note: Not all possible combinations of settings are allowed (see section 2.5).

The calibration procedure must include establishing the coefficients for calibration calculation and the following steps depending on

configuration:

.

Adjustment of the extended offset compensation

Zero compensation of temperature measurement

Adjustment of the bridge current

Settings for the reference voltage if using the reference voltage

Settings for the thresholds and delays for the alarms if using the alarms

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ZSC31050 Datasheet

2.3 Analog Front-End (AFE)

The analog front-end consists of the programmable gain amplifier (PGA), the multiplexer (MUX), and the analog-to-digital converter (ADC).

2.3.1 Programmable Gain Amplifier (PGA)

The following tables show the adjustable gains, the sensor signal spans that can be processed, and the common mode range allowed.

Table 1.

Adjustable Gains, Resulting Sensor Signal Spans, and Common Mode Ranges

Max. Span

V_{IN_SP}in mV/V

Input Range

V_{IN_CM}in % VDDA^‡

No.

PGA Gain a_IN

Gain Amp1

Gain Amp2

Gain Amp3

1

2

420

280

210

140

105

70

30

15

7.5

3.75

1

7

2

3

43 to 57

40 to 59

43 to 57

40 to 59

38 to 62

40 to 59

38 to 62

40 to 59

38 to 62

43 to 57

40 to 59

38 to 62

21 to 76

4.66

7

3

4

4.66

3.5

4.66

3.5

4.66

3.5

7

6

5

8

6

12

16

24

32

50

80

100

280

7

52.5

35

8

9

26.3

14

10

11

12

13

9.3

7

1

4.66

3.5

1.4

1

2.8

1

2.3.2 Extended Zero Point Compensation (XZC)

The ZSC31050 supports two methods of sensor offset cancellation (zero shift):

.

Digital offset correction

XZC – an analog cancellation for large offset values (up to approximately 300% of span)

The digital sensor offset correction is processed at the digital signal correction/conditioning by the CMC. The XZC analog sensor offset pre-

compensation is needed for compensation of large offset values, which would overdrive the analog signal path due to uncompensated

amplification. For analog sensor offset pre-compensation, a compensation voltage is added in the analog pre-gaining signal path (coarse

offset removal). The analog offset compensation in the AFE can be adjusted by six EEPROM bits as described in the ZSC31050 Functional

Description. It allows an analog zero-point shift of up to 300% of the segment of the signal span that can be processed.

‡

Bridge in voltage mode; refer to the ZSC31050 Functional Description for the usable input signal / common mode range at the bridge in current mode.

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ZSC31050 Datasheet

The zero-point shift Z_XZCof the temperature measurements can also be adjusted by six EEPROM bits (recommended Z_XZC= -20 to +20). It is

calculated by equation (1):

V_XZC

k Z_XZC



(1)

VDD_BR20 a_IN

Where

V_XZC

= Extended zero compensation voltage

VDD_BR= Bridge voltage

k

= Calculation factor

= Input gain

a_IN

Table 2.

Extended Zero Point Compensation (XZC) Range

PGA Gain

Max. Span

V_{IN_SP}

Calculation

Factor k

Offset Shift per Step

(% Full Span)

Approx. Maximum

Offset Shift

Approx. Maximum Shift

(% V_{IN_SP}

)

a_IN

(mV/V)

(@ ± 20 Steps)

420

280

210

140

105

70

2

3.0

1.833

3.0

15%

9%

15%

9%

6%

9%

6%

9%

6%

15%

9%

6%

1%

+/- 7

330

200

330

200

140

200

140

200

140

330

200

140

22

3

+/- 6

4

+/- 14

+/- 12

+/- 24

+/- 22

+/-48

6

1.833

1.25

1.833

1.25

1.833

1.25

3.0

8

12

16

24

32

50

80

100

280

52.5

35

26.3

14

+/- 45

+/- 180

+/- 160

+/- 140

+/- 60

9.3

7

1.833

1.25

0.2

2.8

Note: Z_XZCcan be adjusted in the range of –31 to 31; however, parameters are guaranteed only for -20 to 20.

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ZSC31050 Datasheet

2.3.3 Measurement Cycle Performed by Multiplexer

Depending on EEPROM settings, the multiplexer selects the following inputs in a set sequence as shown in Figure 2.

Refer to the ZSC31050 Functional Description for EEPROM details.

Figure 2.

Measurement Cycle ZSC31050

.

Internal offset of the input channel (auto-zero) measured by short circuiting

the input

Start Routine

.

Bridge temperature signal measured by external and internal diode (pn-

junction)

n

Bridge sensor measurement

Temp 1 auto-zero

.

Bridge temperature signal measured by bridge resistors

Temperature measured by external thermistor

Pre-amplified bridge sensor signal

1

n

Bridge sensor measurement

Temp 1 measurement

1

The complete measurement cycle is controlled by the CMC. The cycle

diagram at the right shows its principle structure.

n

Bridge sensor measurement

Bridge sensor auto-zero

Bridge sensor measurement

Temp 2 auto-zero

1

The EEPROM adjustable parameters are

n _*T2E

T2E

n _*T2E

T2E

n

.

Measurement count n (bits 9:7 in configuration word CFGCYC):

n =<1, 2, 4, 8, 16, 32, 64, 128>

Bridge sensor measurement

Temp 2 measurement

.

Temperature 2 measurement enable, T2E=<0, 1>

After power-on, the start routine is called. It includes the bridge sensor and

auto-zero measurement. It also measures the main temperature channel and

its auto-zero if enabled.

Bridge sensor measurement

Common mode voltage

1

2.3.4 Analog-to-Digital Converter

The ADC is a charge-balancing converter using full differential switched capacitor technique. It can be used as a first or second order

converter:

In the first order mode, the ADC is inherently monotone and insensitive against short and long term instability of the clock frequency. The

conversion cycle time depends on the desired resolution and can be roughly calculated by equation (2):

r

ADC

(2)

t_{CYC_1} 2

s

 

The available ADC resolutions are r_ADC= <9, 10, 11, 12, 13, 14>.

In the second order mode, two conversions are stacked with the advantage of a much shorter conversion cycle time but with the drawback of

a lower noise immunity caused by the shorter signal integration period. The conversion cycle time in this mode is roughly calculated by

equation (3):

r

3







ADC



t_{CYC_ 2} 2^^

s

 

(3)

2



The available ADC resolutions are r_ADC= <11, 12, 13, 14, 15>.

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ZSC31050 Datasheet

The result of the AD conversion is a relative counter result corresponding to equation (4):













V_{ADC_DIFF}V_{ADC_OFF}

r

ADC

Z_ADC 2



1 RS_ADC

(4)

V_{ADC_REF}

Z_ADC

Number of counts; i.e., the result of the conversion)

V_{ADC_DIFF}

V_{ADC_REF}

V_{ADC_OFF}

RS_ADC

Differential input voltage of ADC: (a_IN* V_{IN_DIFF}

)

Reference voltage of ADC: (VBR or VDDA)

Residual offset voltage of analog front-end to ADC

Digital ADC range shift (RS_ADC= ¹/₂, ³/₄, ⁷/₈, ¹⁵/₁₆, controlled by EEPROM setting)

A sensor input signal can be shifted via the RS_ADCvalue into the optimal input range of the ADC.

The potential at the VBR pin is used as the ADC’s reference voltage V_{ADC_REF}in “V_{ADC_REF}= VBR” mode. The mode is determined by the

CFGAPP:ADCREF configuration register in EPPROM as described in the ZSC31050 Functional Description. Sensor bridges with no

ratiometric behavior (e.g., temperature-compensated bridges) that are supplied by a constant current, require the VDDA potential as V_{ADC_REF}

and this can be adjusted in the configuration. If this mode is enabled, XZC cannot be used (adjustment=0), but it must be enabled (refer to the

calculation spreadsheet ZSC31050_Bridge_Current_Excitation_Rev*.xls for details).

Note: The AD conversion time (sample rate) is only part of the complete signal conditioning cycle.

Table 3.

Output Resolution versus Sample Rate

Maximum Output Resolution

Sample Rate f_CON

ADC

Order

§

r_ADC

(Bit)

9

Digital OUT

Analog OUT

r_PWM

(Bit)

9

f_CLK=2MHz

f_CLK=2.25MHz

(Hz)

(O_ADC

)

(Bit)

9

(Bit)

9

(Hz)

1302

781

1465

879

10

11

12

13

14

10

11

12

13

14

15

10

11

12

13

14

10

11

12

13

14

15

10

11

10

11

10

11

12

10

11

12

434

488

1

230

259

115

129

59

67

3906

1953

977

4395

2197

1099

2

§

ADC resolution should be 1 to 2 bits higher than applied output resolution

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ZSC31050 Datasheet

2.4 System Control

The system control is started by the internal power-on reset (POR) using the internal clock generator or an external clock. It has the following

features:

.

Control of the I/O functions and the measurement cycle using the EEPROM-stored configuration settings.

16-bit correction calculation for each measurement signal using the EEPROM-stored calibration coefficients and ROM-based algorithms.

Error checking: To increase safety, the EEPROM data are verified via an EEPROM signature during the initialization procedure and the

registers of the CMC are continuously observed with a parity check. If an error is detected, the error flag of the CMC is set and the outputs

are driven to a diagnostic value. See section 2.7.

Note: Conditioning options include up to third-order sensor input correction (de-rated). The available adjustment ranges depend on the

specific calibration parameters; basically, offset compensation and linear correction are only limited by the loss of resolution the compensation

will cause. The second-order correction is possible up to approximately 20% of the full-scale difference from a straight line; third-order is

possible up to approximately 10% (ADC resolution = 13 bits). The temperature calibration includes first and second order correction, which

should be sufficient in almost all applications. ADC resolution also affects calibration options – each additional bit of resolution reduces the

calibration range by approximately 50%.

2.5 Output Stage

The ZSC31050 provides the following I/O pins: OUT, IO1, IO2, and SDA. The signal formats listed in Table 4 can be output via these pins:

analog (voltage or current), PWM, data (SPI/I²C), alarm. The following values can be provided at the I/O pins: bridge sensor signal,

temperature signal 1, temperature signal 2, and alarms.

Note: The alarm signals (Alarm 1 and Alarm 2) only apply to the bridge sensor signal; they cannot be used as an alarm for the temperature

signal.

Because some pins are dual-purpose, there are restrictions on the possible combinations for outputs and interface connections. Table 4 gives

an overview of valid combinations. For some combinations in the SPI Mode, pin assignments depend on whether the ZSC31050 is in the

Command Mode (CM) or the Normal Operation Mode (NOM) as indicated in the “Mode” column (refer to the ZSC31050 Functional

Description for more details).

Note: In the SPI Mode, the IO2 pin is used as the Slave Select, so no Alarm 2 can be output in this mode.

Table 4.

Output Configurations Overview

SIF

I/O Pins Used

Configuration

Number

Mode

I²C



SPI

OUT

IO1

IO2

SDA

1

2

Data I/O

ALARM1

3

ALARM2

4

ALARM1

PWM1

5

6

PWM1

ALARM2

7

Analog

8

ALARM1

9

ALARM2

10

11

ALARM1

PWM1

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ZSC31050 Datasheet

SIF

I/O Pins Used

Configuration

Number

Mode

I²C



SPI

OUT

IO1

IO2

SDA

12

13

14

15

16

17

18

Analog

PWM2

PWM1

ALARM2

Data I/O

ALARM1

ALARM2

ALARM1

PWM1

ALARM2

Data out

(SDO)

19



Slave select

Data in

Data out

(SDO)

Slave select

CM

20

ALARM1

Data out

PWM1

-

NOM

CM

Slave select

Data in

21

22

23



-

NOM

Analog

Data out

ALARM1

Data out

PWM1

Slave select

Data in

Slave select

Data in

CM

NOM

CM

-

Slave select

Data in

24

25

26



Analog

PWM2

-

NOM

Data out

ALARM1

Data out

PWM1

Slave select

Data in

-

Slave select

CM

NOM

CM

-

Slave select

-

Data in

-

27



PWM2

NOM

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ZSC31050 Datasheet

2.5.1 Analog Output

For analog output, three 15-bit registers store the compensated measurement results for the bridge sensor signal and temperature measure-

ments 1 and 2. Each register can be independently switched to either the digital-to-analog converter module (DAC) or the PWM module (see

Figure 1) and then output via the FIO1 or FIO2 output module connected to the OUT or IO1 pin respectively according to Table 5. Refer to the

ZSC31050 Functional Description for details.

Table 5.

Analog Output Configuration

Output Module

Voltage (DAC)

PWM

OUT



IO1



The voltage output module consists of an 11-bit resistor string DAC with a buffered output and a subsequent inverting amplifier with a class

AB rail-to-rail operational amplifier. The two internal feedback networks are connected to the FBN and FBP pins. This structure offers wide

flexibility for the output configuration; for example, voltage output and 4mA to 20mA current loop output. Accidentally short-circuiting the

analog output to VSS or VDDA does not damage the ZSC31050.

The PWM module outputs the analog measurement value via a stream of pulses with a duty cycle that is determined by the analog value. The

PWM frequency depends on the resolution and clock divider settings. The maximum analog output resolution is 12 bits; however the

maximum PWM frequency is 4kHz (9 bits). If both PWM2 and SPI protocol are activated (configuration numbers 25, 26, and 27 in Table 4),

the output IO1 pin is shared between the PWM output and the SPI SDO output of the serial interface, and SPI interface communication

(Command Mode) interrupts the PWM output.

2.5.2 Comparator Module (ALARM Output)

The comparator module consists of two comparator channels that can be connected to IO1 and IO2. Each can be independently programmed

for threshold, hysteresis, switching direction, and on/off delay. A window comparator mode is also available.

2.5.3 Serial Digital Interface

The ZSC31050 includes a serial digital interface that is able to communicate in three different communication protocols: I²C, SPI, and

ZACwire™ (one-wire communication). In SPI mode, the IO2 pin operates as the slave-select input, and the IO1 pin is the data output (SDO).

Initializing Communication

After power-on for approximately 20ms (the start window), the ZSC31050 interface is in the ZACwire™ mode, which allows communication

via the one-wire interface (the OUT pin).

If a proper communication request is detected during the start window, the interface stays in the ZACwire™ mode (the Command Mode). This

state can be left by set commands or a new power-on.

If no request is received during the start window, then the serial interface switches to communication via either I²C or SPI mode depending on

EEPROM settings. The OUT pin can be used as an analog output or as a PWM output depending on EEPROM settings. The start window

can be disabled (or enabled) by a special EEPROM setting.

For a detailed description of the serial interfaces, see the ZSC31050 Functional Description.

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ZSC31050 Datasheet

2.6 Voltage Regulator

For 3V to 5V (±10%) ratiometric output applications, the external supply voltage can be used for sensor element biasing. If an absolute

analog output is required, then the internal voltage regulator with an external power regulation element (JFET) can be used. The regulation is

bandgap-reference-based and designed for an external supply voltage V_SUPPin the range of 7V to 48V DC. The internal supply and sensor

bridge voltage can be varied between 3V and 5.5V in four steps with the voltage regulator as determined by a configuration word in

EEPROM.

2.7 Watchdog and Error Detection

The ZSC31050 detects various possible errors. A detected error is signaled by changing to a diagnostic mode. In this case, the analog output

is set to the high or low level (maximum or minimum possible output value) depending on the error and the output registers of the digital serial

interface are set to a correlated error code.

A watchdog continuously monitors the operation of the CMC and the progress of the measurement loop.

A continuous check of the sensor bridge for broken wires is done by two comparators monitoring the input voltage of each input [(VSSA +

0.5V) to (VDDA – 0.5V)]. The common mode voltage of the sensor is continuously monitored to detect sensor aging.

Different functions and blocks in the digital section are continuously monitored, including the RAM, ROM, EEPROM, and register contents.

See section 1.3.4 in the ZSC31050 Functional Description for a detailed description of all monitored blocks and methods of indicating errors.

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ZSC31050 Datasheet

3. Application Circuit Examples

Figure 3. Application Example 1

Figure 4. Application Example 2

Typical ratiometric measurement with voltage output, temperature

compensation via external diode, internal VDD regulator, and active

sensor connection check (bridge must not be at VDDA)

0V to 10V output configuration with supply regulator (external

JFET), temperature compensation via internal diode, and bridge

in voltage mode

VDDA = 5V

+7V to +48V

+2.7V to +5.5V

V_SUPP

C1

C2

R3

390Ω

0.1µF

9

8

7

6

5

4

3

2

1

FBN

VDD

SDA

C2

C3

9

8

7

6

5

4

3

2

1

FBN

VDD

SDA

0.1µF 0.1µF

10

11

12

13

14

15

16

OUT

SDA

SCL

IO2

10

11

12

13

14

15

16

OUT

SDA

Serial Interface

Flexible I/Os

Out: 0 to 10V

FBP

SCL

FBP

SCL

IO1

IO2

R1

ZD

6.8V

2.2kΩ

IR_TEMP

VBR

IO2

IR_TEMP

VBR

IO2

IO1

C1

0.1µF

IO1

VINP

VSS

VGATE

IN3

VINP

VSS

VGATE

IN3

R4

R2

1kΩ 2kΩ

VINN

VDDA

VINN

VDDA

C2

< 15nF

Sensor Bridge

Out / OWI

GND

Figure 5. Application Example 3

Figure 6. Application Example 4

Absolute voltage output, supply regulator (external JFET), constant

current excitation of the sensor bridge, temperature compensation

by bridge voltage drop measurement, internal VDD regulator

without external capacitor

Ratiometric bridge differential signal measurement, 3–wire

connection for end-of-line calibration at OUT pin (ZACwire™),

additional temperature measurement with external thermistor,

and PWM output at IO1 pin

VDDA = 5V

+7V to +48V

+2.7V to +5.5V

V_SUPP

C1

0.1µF

C1

0.1µF

C2

0.1µF

C2

0.1µF

R_{BR_REF}

9

8

7

6

5

4

3

2

1

R_T

FBN

VDD

SDA

9

8

7

6

5

4

3

2

1

FBN

VDD

SDA

ZD

6.8V

10

11

12

13

14

15

16

OUT

SDA

SCL

IO1

10

11

12

13

14

15

16

OUT

SDA

SCL

Serial Interface

Flexible I/Os

FBP

SCL

FBP

SCL

IR_TEMP

VBR

IO2

IR_TEMP

VBR

IO2

IO1

PWM OUT

IO1

IO2

VINP

VSS

VGATE

IN3

VINP

VSS

VGATE

IN3

PTC

VINN

VDDA

VINN

VDDA

C2

< 15nF

Sensor Bridge

< 15nF

Sensor Bridge

Out / OWI

GND

Out / OWI

GND

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February 13, 2017

ZSC31050 Datasheet

Figure 7. Application Example 5

Two-wire 4mA to 20mA configuration (7 to 48 V), temperature compensation via internal diode

VDDA = 5V

+7V to +48V

V_SUPP

ZD

7.5V

(Current Loop+)

C1

0.1µF

C2

0.1µF

9

8

7

6

5

4

3

2

1

FBN

VDD

SDA

C3

10nF

10

11

12

13

14

15

16

OUT

SDA

SCL

IO2

Serial Interface

Flexible I/Os

FBP

SCL

IR_TEMP

VBR

IO2

IO1

VINP

VSS

VGATE

IN3

C4

220pF

R_e

VINN

VDDA

150Ω

R_B

2.2kΩ

R_sens

50Ω

Sensor Bridge

(Current Loop)

GND

Note: It is possible to combine or separate connectivity of different application examples. For VDD generation, IDT recommends using the

internal supply voltage regulator with an external capacitor. Refer the ZSC31050 Application Note—Current Loop for use of supply voltage

regulation features (non-ratiometric mode) and current loop output mode.

4. ESD/Latch-Up-Protection

All pins have an ESD protection of >2000V, except the VINN, VINP, and FBP pins, which have an ESD protection >1200V. All pins have a

latch-up protection of 100mA or +8V/ –4V (relative to VSS/VSSA). Refer to section 5 for details and restrictions. ESD protection referenced

to the Human Body Model is tested with devices in 16-SSOP packages during product qualification. The ESD test follows the Human Body

Model with 1.5kOhm/100pF based on MIL 883, method 3015.7.

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ZSC31050 Datasheet

5. Pin Configuration and Package

Table 6.

Pin Configuration

Latch-up Related Application Circuit

1

Name

Description

Remarks

Supply

Restrictions and/or Remarks

VDDA

IN3

Positive analog supply voltage

2

Resistive temperature sensor IN and Analog IN

external clock IN

Freely accessible by application (vulnerable to latch-

up if specifications in section 4 are exceeded)

3

4

VGATE

IO1

Gate voltage for external regulator

FET

Analog OUT

Only connection to external JFET

SPI data out or ALARM1 or PWM1

Output

Digital IO

Freely accessible by application

5

6

7

8

IO2

SCL

SDA

VDD

SPI slave select or ALARM2

I²C clock or SPI clock

Digital IO

Freely accessible by application

Digital IN, pull-up

Digital I/O, pull-up

Supply

Data I/O for I²C or data IN for SPI

Positive digital supply voltage

Only capacitor to VSS is allowed; otherwise no

application access

9

FBN

OUT

FBP

Negative feedback connection

output stage

Analog I/O

Freely accessible by application

10

11

Analog output or PWM2 output or

one-wire interface I/O

Analog OUT or

Digital I/O

Positive feedback connection output Analog I/O

stage

12

13

IR_TEMP Current source resistor I/O and

temperature diode in

Analog I/O

Circuitry secures potential is within VSS-VDDA

range; otherwise no application access

VBR

Bridge top sensing in bridge current

out

Analog I/O

Only short to VDDA or connection to sensor bridge;

otherwise no application access

14

15

16

VINP

VSS

Positive input from sensor bridge

Negative supply voltage

Analog IN

Ground

Freely accessible by application

VINN

Negative input from sensor bridge

Analog IN

Freely accessible by application

24

February 13, 2017

ZSC31050 Datasheet

The standard package for the ZSC31050 is a 16-SSOP (5.3mm body width) with lead-pitch 0.65mm:

Figure 8. Pin Configuration

Pin Name

9

10

11

12

13

14

15

16

8

7

6

5

4

3

2

1

FBN

OUT

VDD

SDA

SCL

IO2

FBP

IR_TEMP

VBR

IO1

VINP

VGATE

IN3

VDDA

VSS

VINN

6. Reliability

The ZSC31050 is qualified according to the AEC-Q100 standard, operating temperature grade 0. A fit rate < 5fit (temp=55°C, S=60%) is

guaranteed. A typical fit rate of the C7A technology that is used for the ZSC31050 is 2.5fit.

7. Customization

For high-volume applications that require an upgraded or downgraded functionality compared to the ZSC31050, IDT can customize the circuit

design by adding or removing certain functional blocks.

IDT has a considerable library of sensor-dedicated circuitry blocks that enable IDT to provide a custom solution quickly. Please contact IDT

for further information.

25

February 13, 2017

ZSC31050 Datasheet

8. Ordering Information

Product Code

Description

Package

ZSC31050FEB

ZSC31050FEC

ZSC31050FEG1

ZSC31050 Die — Temperature range: -40°C to +150°C

ZSC31050 16-SSOP — Temperature range: -40°C to +150°C

Unsawn on Wafer

Sawn on Wafer Frame

Tube: add “-T” to sales code

Reel: add “-R”

ZSC31050FAB

ZSC31050FAC

ZSC31050FAG1

ZSC31050 Die — Temperature range: -40°C to +125°C

ZSC31050 16-SSOP — Temperature range: -40°C to +125°C

Unsawn on Wafer

Sawn on Wafer Frame

Tube: add “-T” to sales code

Reel: add “-R”

ZSC31050FIB

ZSC31050FIC

ZSC31050FIG1

ZSC31050 Die — Temperature range: -25°C to +85°C

ZSC31050 16-SSOP — Temperature range: -25°C to +85°C

Unsawn on Wafer

Sawn on Wafer Frame

Tube: add “-T” to sales code

Reel: add “-R”

ZSC31050KITV3P1

ZSC31050MCSV1P1

ZSC31050 SSC Evaluation Kit V3.1: ZSC31050 Evaluation Board, SSC Communication Board, SSC Sensor

Replacement Board, five ZSC31050 16-SSOP samples. Software is downloadable.

Modular Mass Calibration System (MSC) V1.1 for ZSC31050: Four Mass Calibration Boards; SSC

Communication Board; four ZSC31050 Mass Calibration Reference Boards, each with a ZSC31050 sample

mounted; 30m 10-wire flat cable; 100 connectors. Software is downloadable.

9. Related Documents

Visit the ZSC31050 product page (www.IDT.com/ZSC31050) or contact your nearest sales office for the latest version of this document and

型号:	ZSC31050FIG1-R
Brand Name：	Integrated Device Technology
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Active
零件包装代码：	SSOP
包装说明：	SOP,
针数：	16
制造商包装代码：	PYG16
Reach Compliance Code：	compliant
HTS代码：	8542.31.00.01
风险等级：	1.55
模拟集成电路 - 其他类型：	ANALOG CIRCUIT
JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3
湿度敏感等级：	1
功能数量：	1
端子数量：	16
最高工作温度：	85 °C
最低工作温度：	-25 °C
封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260
最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	2.7 V
表面贴装：	YES
技术：	CMOS
温度等级：	OTHER
端子面层：	Tin (Sn)
端子形式：	GULL WING
端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

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