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Understanding bug fix patterns in verilog

Published: 10 May 2008 Publication History

Abstract

Today, many electronic systems are developed using a hardware description language, a kind of software that can be converted into integrated circuits or programmable logic devices. Like traditional software projects, hardware projects have bugs, and significant developer time is spent fixing them. A useful first step toward reducing bugs in hardware is developing an understanding of the frequency of different types of errors. Once the most common types are known, it is then possible to focus attention on eliminating them. As most hardware projects use software configuration management repositories, these can be mined for the textual bug fix changes. In this project, we analyze the bug fix history of four hardware projects written in Verilog and manually define 25 bug fix patterns. The frequency of each bug type is then computed for all projects. We find that 29 -- 55% of the bug fix pattern instances in Verilog involve assignment statements, while 18 -- 25% are related to if statements.

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cover image ACM Conferences
MSR '08: Proceedings of the 2008 international working conference on Mining software repositories
May 2008
162 pages
ISBN:9781605580241
DOI:10.1145/1370750
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 10 May 2008

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Author Tags

  1. VHDL
  2. error classification
  3. verilog

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Cited By

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  • (2024)Strider: Signal Value Transition-Guided Defect Repair for HDL Programming AssignmentsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334175043:5(1594-1607)Online publication date: May-2024
  • (2023)Validating the Redundancy Assumption for HDL from Code Clone's PerspectiveProceedings of the 2023 International Symposium on Physical Design10.1145/3569052.3571872(247-255)Online publication date: 26-Mar-2023
  • (2023)CirFix: Automated Hardware Repair and its Real-World ApplicationsIEEE Transactions on Software Engineering10.1109/TSE.2023.326989949:7(3736-3752)Online publication date: Jul-2023
  • (2023)Mantra: Mutation Testing of Hardware Design Code Based on Real Bugs2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247962(1-6)Online publication date: 9-Jul-2023
  • (2022)CirFix: automatically repairing defects in hardware design codeProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3503222.3507763(990-1003)Online publication date: 28-Feb-2022
  • (2022)Programming Hints Generation based on Abstract Syntax Tree Retrieval2022 IEEE Frontiers in Education Conference (FIE)10.1109/FIE56618.2022.9962631(1-5)Online publication date: 8-Oct-2022
  • (2021)What changes in where?ACM SIGAPP Applied Computing Review10.1145/3447332.344733420:4(18-34)Online publication date: 12-Jan-2021
  • (2017)Detecting and analyzing code clones in HDL2017 IEEE 11th International Workshop on Software Clones (IWSC)10.1109/IWSC.2017.7880501(1-7)Online publication date: 21-Feb-2017
  • (2014)Pre-Silicon Bug ForecastIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.228868833:3(451-463)Online publication date: 1-Mar-2014
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