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Pull requests: Digilent/vivado-boards

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Pull requests list

@mohanex correcting uart pins on nexys video
#42 opened Jun 1, 2023 by mohanex Loading…
nexys video: fix on-board led io standard config
#40 opened Mar 19, 2023 by Headcrabed Loading…
added 2 mig modes, added ddr3 interface to board, fixed clk_wiz probl…
#37 opened Apr 20, 2022 by ColdfireMC Loading…
1
Added board files for the NetFPGA 1G CML
#33 opened Jun 17, 2021 by bkzshabbaz Loading…
The part number syntax was updated for Arty-A7-100. Previously, with …
#28 opened Sep 19, 2020 by timothystotts Loading…
1
zybo: fix PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY error in Vivado.
#25 opened Apr 22, 2020 by svet-am Loading…
1
Fixed Zybo preset for Eth0 MDIO pins
#17 opened Feb 11, 2019 by vengin Loading…
1
Zybo: ENET0 MDIO mapped to EMIO instead of MIO
#15 opened Nov 29, 2018 by Jiware Loading…
ProTip! What’s not been updated in a month: updated:<2024-10-18.