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SoCo (Sonos Controller) is a Python project that allows you to programmatically control Sonos speakers.

Python 1,491 231 Updated Oct 13, 2024

A Fully Open-Source Verilog-to-PCB Flow

Python 15 2 Updated Jul 7, 2024

Hardware Description Library

Python 68 16 Updated Sep 6, 2024

Small 2-bit serial 8/16 bit CPU for Tiny Tapeout 7

Verilog 1 Updated Jun 4, 2024

A configurable and approachable tool for FPGA debugging and rapid prototyping.

Python 107 9 Updated Oct 12, 2024

repository for a bandgap voltage reference in SKY130 technology

Python 34 6 Updated Jan 20, 2023

SAR ADC on tiny tapeout

Verilog 31 1 Updated Jul 4, 2024

A set of rules and recommendations for analog and digital circuit designers.

25 Updated Feb 16, 2024

A version of f32c/arduino that works with the SpinalHDL Vexriscv Murax SoC

C 14 2 Updated May 23, 2019

SPI RAM Emulation on Pico

C 14 3 Updated Jul 30, 2023

Electronics Testbench Automation Library

Python 25 5 Updated Jun 15, 2023

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

Python 309 52 Updated Sep 18, 2024
Jupyter Notebook 68 35 Updated Sep 18, 2024

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design

HTML 388 61 Updated Oct 14, 2024

Attempts at recovering SKY130 MPW-ONE chips (December 2020 // March 2022)

Jupyter Notebook 4 Updated Jan 13, 2023

Christmas tree controller (ASIC)

Verilog 7 1 Updated Mar 28, 2023

Staging repo for Yosys command reference build. The contents of this repository are autogenerated from Yosys source.

TeX 4 2 Updated Aug 14, 2024

Bare-metal software for the Carbon1 RISC-V tape-out

C 4 1 Updated Jul 3, 2022

Fix color space list for Elgato Camlink devices

C 71 16 Updated Mar 26, 2021
Verilog 10 8 Updated Dec 17, 2022

Proof of Concept to learn Amaranth as an entry effort for Supercon's RTL design competition

Python 10 2 Updated Nov 11, 2022

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

Python 108 9 Updated Sep 20, 2023

snaking shiftreg for tinytapout

Verilog 1 1 Updated Sep 25, 2022

Generator for wokwi schematics that implement lookup tables in conjunctive normal form (CNF), i.e. with AND and OR gates

Python 5 4 Updated Feb 26, 2023
Verilog 1 1 Updated Oct 6, 2022

A tiny SoC for TinyTapeout

Verilog 2 Updated Aug 31, 2022

32-bit RISC-V based processor with memory controler

Verilog 15 1 Updated Sep 2, 2022

Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.

Python 45 7 Updated Aug 23, 2020

RISC-V SoC designed for the Efabless Open MPW Program

Verilog 10 1 Updated Jan 28, 2024
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