Bitwarden client apps (web, browser extension, desktop, and cli).

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

A Real Time Clock core for FPGA's

complexpack is a complex arithmetic package written in VHDL.

A Rust crate for cooking up terminal user interfaces (TUIs) 👨‍🍳🐀 https://ratatui.rs

A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog

Control and Status Register map generator for HDL projects

FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)

Set of scripts for Vivado's project handling

Compiler front-end foundation technology.

Путеводитель C++ программиста по неопределенному поведению

Setup configuration used in my videos

The roadmap for learning the C++ programming language for beginners and experienced devs.

UVM components for DSP tasks (MODulation/DEModulation)

Contains source code for sin/cos table verification using UVM

Коллекция вопросов, которые мне задавали на собеседованиях (вакансия программист-разработчик C++)

Animation of the SHA-256 hash function in your terminal.

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

нерегулярный подкаст о жизни ресечеров по обе стороны океана

Python composable command line interface toolkit

Flexible VHDL library