Merge pull request #4510 from rickard-green/rickard/ppc64-membar-impr…

…ovements/OTP-17200 Improved memory barrier usage on 64-bit PowerPC
erlang · Feb 18, 2021 · ca0fe0b · ca0fe0b
2 parents 8e17937 + ceb6000
commit ca0fe0b
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diff --git a/erts/aclocal.m4 b/erts/aclocal.m4
@@ -1539,6 +1539,33 @@ AC_ARG_WITH(with_sparc_memory_order,
 	    AS_HELP_STRING([--with-sparc-memory-order=TSO|PSO|RMO],
 			   [specify sparc memory order (defaults to RMO)]))
 
+AC_ARG_ENABLE(ppc-lwsync-instruction,
+AS_HELP_STRING([--enable-ppc-lwsync-instruction], [enable use of powerpc lwsync instruction])
+AS_HELP_STRING([--disable-ppc-lwsync-instruction], [disable use of powerpc lwsync instruction]),
+[ case "$enableval" in
+    no) enable_lwsync=no ;;
+    *)  enable_lwsync=yes ;;
+  esac ],
+[
+  AC_CHECK_SIZEOF(void *)
+  case $host_cpu-$ac_cv_sizeof_void_p in
+       macppc-8|powerpc-8|ppc-8|powerpc64-8|ppc64-8|powerpc64le-8|ppc64le-8|"Power Macintosh"-8)
+           enable_lwsync=yes;;
+       *)
+           enable_lwsync=undefined;;
+  esac ])
+
+case $enable_lwsync in
+     no)
+       AC_DEFINE(ETHR_PPC_HAVE_NO_LWSYNC, [1], [Define if you do not have the powerpc lwsync instruction])
+       ;;
+     yes)
+       AC_DEFINE(ETHR_PPC_HAVE_LWSYNC, [1], [Define if you have the powerpc lwsync instruction])
+       ;;
+     *)
+       ;;
+esac
+
 LM_CHECK_THR_LIB
 ERL_INTERNAL_LIBS
 
@@ -2850,6 +2877,8 @@ AC_DEFUN([LM_HARDWARE_ARCH], [
     ppc)	ARCH=ppc;;
     ppc64)	ARCH=ppc64;;
     ppc64le)	ARCH=ppc64le;;
+    powerpc64)	ARCH=ppc64;;
+    powerpc64le) ARCH=ppc64le;;
     "Power Macintosh")	ARCH=ppc;;
     arm64)	ARCH=arm64;;
     armv5b)	ARCH=arm;;

diff --git a/erts/include/internal/ethread_header_config.h.in b/erts/include/internal/ethread_header_config.h.in
@@ -76,6 +76,12 @@
 /* Define if x86/x86_64 out of order instructions should be synchronized */
 #undef ETHR_X86_OUT_OF_ORDER
 
+/* Define if you have the powerpc lwsync instruction */
+#undef ETHR_PPC_HAVE_LWSYNC
+
+/* Define if you do not have the powerpc lwsync instruction */
+#undef ETHR_PPC_HAVE_NO_LWSYNC
+
 /* Define if only run in Sparc TSO mode */
 #undef ETHR_SPARC_TSO
 

diff --git a/erts/include/internal/gcc/ethread.h b/erts/include/internal/gcc/ethread.h
@@ -80,6 +80,14 @@
 #elif !ETHR_AT_LEAST_GCC_VSN__(4, 8, 0)
 /* True gcc of version < 4.8, i.e., bug exist... */
 #  define ETHR___atomic_load_ACQUIRE_barrier_bug ETHR_GCC_VERSIONS_MASK__
+#elif ETHR_AT_LEAST_GCC_VSN__(9, 3, 0) \
+    && (defined(__powerpc__) || defined(__ppc__) || defined(__powerpc64__)) \
+    && ETHR_SIZEOF_PTR == 8
+/* Verified not to have this bug */
+#    define ETHR___atomic_load_ACQUIRE_barrier_bug 0
+/* Also trust builtin barriers */
+#    undef ETHR_TRUST_GCC_ATOMIC_BUILTINS_MEMORY_BARRIERS__
+#    define ETHR_TRUST_GCC_ATOMIC_BUILTINS_MEMORY_BARRIERS__ 1
 #else /* True gcc of version >= 4.8 */
 /*
  * Sizes less than or equal to word size have been fixed,