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1. riscv-tlv-core riscv-tlv-core Public

   A simple implementation of a RISC-V core (RV32I) written in TL Verilog.

   Verilog 2

2. des-aes-128bit-verilog des-aes-128bit-verilog Public

   Verilog

3. riscv-ms-soc riscv-ms-soc Public

   A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier

   Verilog 9

4. SHA256_HW_Accelerator SHA256_HW_Accelerator Public

   Verilog

5. Accelerating_Standard_and_Modified_AES128 Accelerating_Standard_and_Modified_AES128 Public

   Forked from BalaDhinesh/Accelerating_Standard_and_Modified_AES128

   Verilog

6. courseraforums courseraforums Public

   Forked from elleros/courseraforums

   [Implementation Updated] Anonymized versions of the discussion threads from the forums of 60 Coursera MOOCs

   Jupyter Notebook