Vitis Libraries

A sorting library for FPGA implementation

Vitis HLS Library for FINN

Machine learning on FPGAs using HLS

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.

PYNQ support and examples for Kria SOMs

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

PYNQ Composabe Overlays

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Project F brings FPGAs to life with exciting open-source designs you can build on.

HeteroCL-MLIR dialect for accelerator design

RISC-V Playground on Nandland Go

Learning FPGA, yosys, nextpnr, and RISC-V

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

Exploring gate level simulation

Graphics demos

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

LLVM based HLS library for HWToolkit (hardware devel. toolkit)

Tutorial notebooks for hls4ml

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.githu…

PandA-bambu public repository

Parallel Programming for FPGAs -- An open-source high-level synthesis book

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

A huge VHDL library for FPGA development