FPGA accelerated TinyYOLO v2 object detection neural network

Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog

Apple II FPGA Co-Processor

⚙️ 基于 Zynq-7 全可编程 SoC 的设计

支持 45 条 MIPS 指令的单周期处理器 -- 计算机组成原理实验 NUAA Spring 2017

A variable FPGA-based QAM transmitter with scalable mixed time and frequency domain signal processing.

a collection of tools made while messing with the Colorlight 5A-75B V7.0 and some notes using ECP5 with Yosys

Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators

The ZipCPU blog

FPGA (Verilog) implementation of the Flip01 8-bit processor.

This repository contains lab assignments done in the course CS220: Computer Organization at IIT Kanpur

Source files Related to WireFrame FPGA Board published on www.circuitvalley.com

Transmitter and Receiver FPGAs connected using the UART Protocol to execute arithmetic operations and display the inputs on the transmitter's 7 Segment Display as well as the result on the Receiver's 7 Segments Display.

8-bit ALU in Verilog.

Gebze Technical University

A Logic Circuit Static Timing Analyzer Implemented in Python 🔌 ⚡ (2018)

My technical notes as bite-sized executable programs

Projeto com objetivo de desenvolver um sistema computacional contendo, ao menos, um processador e seus componentes periféricos.

Verilog Implementation of the LC-3 Processor. DA CS 603

Nexys4FPGA game, verilog, imitate FlappyBird