HDL libraries and projects
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Updated
Nov 23, 2024 - Verilog
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jesd204b
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ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
ddr
dsp
vhdl
xilinx
adc
ddc
altera
dds
digital-signal-processing
fir
jesd204b
analog-signals
serial-interface
cic
dac
adc-configurator
serdes-mode
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Updated
Aug 29, 2018 - VHDL
Python interface and configurator for the ADI JESD204 Interface Framework
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Updated
Nov 18, 2024 - Python
JESD204B ADC and DAC SYZYGY Pod.
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Updated
May 21, 2022
HDL libraries and projects
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Updated
Oct 6, 2022 - Verilog
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