2011-09-22
1
BCR10PN
NPN/PNP Silicon Digital Transistor Array
• Switching circuit, inverter, interface circuit,
driver circuit
• Two (galvanic) internal isolated NPN/PNP
Transistors in one package
• Built in bias resistor NPN and PNP
(R
1
=10 kΩ, R
2
=10 kΩ)
• Pb-free (RoHS compliant) package
• Qualified according AEC Q101
1
6
2
3
5
4
EHA07176
6 54
321
C1 B2 E2
C2B1E1
1
R
R
2
R
1
R
2
TR1
TR2
Tape loading orientation
EHA07193
123
456
W1s
Direction of Unreeling
Top View
Marking on SOT-363 package
(for example W1s)
corresponds to pin 1 of device
Position in tape: pin 1
opposite of feed hole side
Type Marking Pin Configuration Package
BCR10PN W1s 1=E1 2=B1 3=C2 4=E2 5=B2 6=C1
SOT363
Maximum Ratings for NPN and PNP Types
Parameter
Symbol Value Unit
Collector-emitter voltage V
CEO
50 V
Collector-base voltage V
CBO
50
Input forward voltage V
i(fwd)
40
Input reverse voltage V
i(rev)
10
DC collector current I
C
100 mA
Total power dissipation, T
S
= 115 °C P
tot
250 mW
Junction temperature T
j
150 °C
Storage temperature T
st
-65 ... 150
Thermal Resistance
Junction - soldering point
1)
R
thJS
≤ 140 K/W
1
For calculation of R
thJA
please refer to Application Note AN077 (Thermal Resistance Calculation)