BA7078AF/AS
Multimedia ICs
!Pin descriptions
Pin No.
Pin name
Functions
Used to select whether to output the VDRV section of the HDRV output
signal.
High : VDRV section of HDRV is output
Low : VDRV section of HDRV is not output
1
HSCTL
HDRV output
Input either the composite synchronization signal or the horizontal
synchronization signal. Input is clamped, and is initiated by capacitor
coupling.
Composite sync / H SYNC
input
2
3
C / HSYNC IN
VIDEO IN
Inputs the SYNC ON VIDEO signal(green).
Input is sink chip clamped. Input is initiated by capacitor coupling.
SYNC ON VIDEO input
f-V conversion
Converts the horizontal synchronization signal frequency into a voltage.
The voltage generated is proportional to the frequency of the horizontal
synchronization signal. Attach a 0.56µF capacitor between the ground
pins.
4
VSEPA
5
6
VSYNC IN V SYNC input
Inputs the vertical synchronization signal.
Integrates the vertical synchronization signal polarity detection circuit.
Attach a 1.5µF capacitor between this pin and the ground.
CVPOL
CVEXI
Vertical polarity integration
Integrates the vertical synchronization signal existence detection circuit.
Attach a 1µF capacitor between this pin and the ground.
7
Vertical existence integration
Used to set the clamp pulse generation position to either the front or
back edge of HSYNC
High : The front edge is the generation position
8
CPSEL
Setting the clamp position
Open : Composite / H SYNC IN
VIDEO IN
:
:
The front edge is the generation position
The back edge is the generation position
Low : The back edge is the generation position
−
9
GND
Ground
Sets the clamp pulse width according to the attached time constant.
Attach a resistor between this pin and VCC and, a capacitor between
this pin and GND. When R = 3.9kΩ and C = 100pF, pulse width is
approximately 400 ns. Set the resistor to register an abnormality at 1kΩ.
10
CPWID
Setting the clamp pulse width
Outputs the vertical synchronization signal.
The output signal has positive polarity.
11
12
VDRV
CLAMP
HDRV
VDRV output
Clamp output
Outputs the clamp pulse generated from the vertical synchronization
signal. The output signal has a positive polarity.
Outputs the clamp pulse generated from the horizontal synchronization
signal. The output signal has positive polarity.
13
14
15
HDRV output
V
CC
Power supply
−
Indecates whether the vertical synchronization signal exists.
For the output logic, refer to the separate table.
EXIV
POLV
EXIH
POLH
Vertical existence output
Indicates the polarity of the vertical synchronization signal.
For the output logic, refer to the separate table.
16
17
18
Vertical polarity output
Indicates whether the horizontal synchronization signal exists.
For the output logic, refer to the separate table.
Horizontal existence output
Horizontal polarity output
Indicates the polarity of the horizontal synchronization signal.
For the output logic, refer to the separate table.
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