BD7820FPE2原理图各脚功能电路原理芯片引脚定义引脚图及功能-中国IC网-芯三七

Datasheet

Class-AB Speaker Amplifier Series

1.2 W

Monaural Speaker Amplifier for Automotive

BD783xxEFJ-M Series (Including products under development)

General Description

Key Specifications

BD783xxEFJ-M Series are Class-AB monaural speaker

amplifiers designed for automotive. Class-AB amplifiers

have no requirements for care about EMI noise. Adopting

power package HTSOP-J8 achieves high output power.

Low quiescent current can reduce battery consumption.

Shutdown current is also very low (0.1 µA Typ) and pop

noise level when switching to shutdown is very small, so

this device is suitable for applications in which the mode

often changes between “shutdown state” and “active

state”.



Output Power

1.2 W (Typ)

(VDD = 5 V, R_L= 8 Ω, THD+N = 1 %)

Quiescent Current

Shutdown Current



2.5 mA (Typ)

0.1 µA (Typ)

Total Harmonic Distortion + Noise

(R_L= 8 Ω, f = 1 kHz)

Output Noise Voltage

Voltage Gain

0.05 % (Typ)^{(Note 2)}

15 μV_RMS(Typ)^{(Note 2)}

6.0 dB to 26.0 dB (Typ)



Operating Temperature Range -40 ºC to +105 ºC

(Note 2) Characteristic of BD78306EFJ-M

Package

HTSOP-J8

W (Typ) x D (Typ) x H (Max)

4.90 mm x 6.00 mm x 1.00 mm

Features



AEC-Q100 Qualified^{(Note 1)}

Pop Noise Reduction Function

Shutdown Function

Protection Functions

-

Over Current Protection

Thermal Shutdown

Under Voltage Lock Out (UVLO)



Power Package with Thermal Pad HTSOP-J8

(Note 1) Grade2

Applications



Automotive Instruments

HTSOP-J8

Typical Application Circuit

8

1

2

3

SDB

BIAS

INP

OUTN

GND

VDD

From System

Control

C₁

7

6

0.47 µF

C₄

10 µF

C₂

Input

VDD

Signal

0.47 µF

C₃

5

4

OUTP

INN

0.47 µF

Figure 1

〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays.

www.rohm.com

TSZ22111 • 14 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

1/25

BD783xxEFJ-M Series (Including products under development)

Pin Configuration

(TOP VIEW)

1

2

3

4

8

7

6

5

OUTN

GND

SDB

BIAS

EXP-PAD

VDD

INP

INN

OUTP

Caution:

VDD and GND pins adjoin each other. In case that these pins are shorted each other, it may make characteristics of power

supply device worse, or it may damage power supply device.

Considering this point, select power supply device which has protection functions as over current protection.

Pin Description

Pin No.

Pin Name

SDB

Function

1

2

3

4

5

6

7

8

-

Shutdown

Bias

BIAS

INP

Positive differential input

Negative differential input

Positive output

INN

OUTP

VDD

Power supply

GND

Ground

OUTN

EXP-PAD

Negative output

Connect the EXP-PAD to Ground

Control Pin’s Setting

SDB pin

Operating Mode

Active

High

Low

Shutdown

Block Diagram

6

VDD

Ri[kΩ]

(Typ)

Rf[kΩ]

(Typ)

Part Number

Rf

BD78306EFJ-M

BD78308EFJ-M^*1

BD78310EFJ-M

BD78312EFJ-M^*1

BD78314EFJ-M^*1

BD78316EFJ-M^*1

BD78318EFJ-M^*1

BD78320EFJ-M^*1

BD78322EFJ-M^*1

BD78324EFJ-M^*1

BD78326EFJ-M

*1 Under Development

90

80

70

60

50

40

36

30

24

20

16

90

Ri

80

OUTP

5

INP

3

110

120

130

140

144

150

156

160

164

Ri

Rf

Ri

OUTN

8

INN

4

Over Current

Protection

Rf

Thermal

Shutdown

BIAS

2

Bias

SDB

1

Under Voltage

Lock Out

GND

7

Figure 2

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

2/25

BD783xxEFJ-M Series (Including products under development)

Absolute Maximum Ratings (Ta = 25 °C)

Parameter

Supply Voltage

Symbol

Rating

Unit

VDDmax

Vin

7.0

-0.3 to VDD+0.3

-55 to +150

150

V

Input Voltage

Storage Temperature Range

Tstg

°C

Maximum Junction Temperature

Tjmax

Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is

operated over the absolute maximum ratings.

Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the

properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by increasing

board size and copper area so as not to exceed the maximum junction temperature rating.

Thermal Resistance^{(Note 1)}

Thermal Resistance (Typ)

Parameter

Symbol

Unit

1s^{(Note 3)}

2s2p^{(Note 4)}

HTSOP-J8

Junction to Ambient

Junction to Top Characterization Parameter^{(Note 2)}

θ_JA

149.4

11.0

39.8

9.0

°C/W

Ψ_JT

(Note 1) Based on JESD51-2A (Still-Air), using a BD78326EFJ-M Chip.

(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside

surface of the component package.

(Note 3) Using a PCB board based on JESD51-3.

(Note 4) Using a PCB board based on JESD51-5, 7.

Layer Number of

Measurement Board

Material

FR-4

Board Size

Single

114.3 mm x 76.2 mm x 1.57 mmt

Top

Copper Pattern

Thickness

70 μm

Footprints and Traces

Thermal Via^{(Note 5)}

Layer Number of

Measurement Board

Material

FR-4

Board Size

114.3 mm x 76.2 mm x 1.6 mmt

2 Internal Layers

Pitch

Diameter

4 Layers

1.20 mm

Φ0.30 mm

Top

Copper Pattern

Bottom

Thickness

70 μm

Copper Pattern

Thickness

35 μm

Copper Pattern

Thickness

70 μm

Footprints and Traces

74.2 mm x 74.2 mm

(Note 5) This thermal via connects with the copper pattern of all layers.

Use a thermal design that has sufficient margin in consideration of power dissipation under actual operating conditions. This

IC exposes its frame at the backside of package. Note that this part is assumed to be used after providing heat dissipation

treatment to improve heat dissipation efficiency. Try to put heat dissipation pattern as wide as possible not only on the board

surface but also on the backside.

Under the insufficient heat dissipation and excessive large signal input condition, power dissipation (Pdiss) exceeds

maximum power dissipation (Pd) and thermal shutdown function may operate. Thermal design should be considered so that

Pdiss is lower than Pd. Reference data of Pdiss is listed on P.7.

(Tjmax : Maximum Junction Temperature = 150 °C, Ta : Operating Ambient Temperature[°C], θja : Package Thermal

Resistance[°C/W])

Power dissipation:

푃푑 = (푇푗푚푎푥 − 푇푎) / 휃푗푎

[W]

This IC has thermal shutdown function. Thermal shutdown operates when Tj (junction temperature, which is assumed to be

same as chip temperature) rises over about 180 °C (Typ) and be released when Tj fall about 160 °C (Typ) or less.

Thermal shutdown is designed to protect the IC from temperature condition that exceeds Tjmax = 150 °C, not to protect or

warrant application set.

Note that device reliability is affected if it is used under temperature thermal shutdown operates.

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

3/25

BD783xxEFJ-M Series (Including products under development)

Recommended Operating Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Operating Supply Voltage

Operating Temperature

Load Resistance

VDD

Topr

R_L

4.0

-40

3.2

5.0

+25

8.0

5.5

+105

38.4

V

°C

Ω

Caution: Operating supply voltage and operating temperature are the ranges in which the IC is available for basic operation.

(Basic operation means that the IC operates without emitting unexpected noise or stopping signal.)

Characteristics and rating are not warranted in the whole operating supply voltage and operating temperature.

Electrical Characteristics 1

(Unless otherwise specified Ta = -40 °C to +105 °C, VDD = 5.0 V, f = 1 kHz, R_L= 8 Ω, BTL^{(Note 1)}, Active)

Limits

Typ

2.5

Parameter

Quiescent Current

Symbol

I_CC

Unit

mA

µA

Conditions

Min

-

Max

6.0

No load

Shutdown

Shutdown Current

Input Impedance

I_SD

-

0.1

25.0

SDB = Low

Z_IN

x0.4

Z_IN

x1.6

Z_IN

0

kΩ

Refer to the table below

OUTP-OUTN

Output Offset Voltage

Control Pin (SDB)

V_OFS

-30

+30

mV

High Level

Low Level

V_IH

V_IL

2.0

0

-

VDD

0.3

V

Input Voltage

Under Voltage Lock Out (UVLO)

Detection

Release

V_{UVLO_DET}

V_{UVLO_REL}

-

3.43

3.58

3.80

3.95

V

Threshold Supply

Voltage

(Note 1) "BTL" means the state that R_Lis connected between the OUTP pin (pin5) and the OUTN pin (pin8).

Z_IN[kΩ]

(Typ)

Z_IN[kΩ]

(Typ)

Part Number

BD78306EFJ-M

BD78308EFJ-M

BD78310EFJ-M

BD78312EFJ-M

BD78314EFJ-M

BD78316EFJ-M

45

BD78318EFJ-M

BD78320EFJ-M

BD78322EFJ-M

BD78324EFJ-M

BD78326EFJ-M

-

18

15

12

10

8

40

35

30

25

20

-

Electrical Characteristics 2

(Unless otherwise specified Ta = 25 °C, VDD = 5.0 V, f = 1 kHz, R_L= 8 Ω, BTL, Active)

Limits

Typ

Parameter

Symbol

Unit

Conditions

Min

0.9

Max

1.6

THD+N = 1 %,

BW = 400 Hz to 30 kHz

Continuous output time

60 s

Rated Output Power^{(Note 2)}

P_O

1.2

W

THD+N = 10 %,

BW = 400 Hz to 30 kHz

Continuous output time

90 s

Maximum Output Power

P_OMAX

-

1.6

-

W

P_O= 1 W

BW = 400 Hz to 30 kHz

P_O= 0.5 W

G_V= 6 dB to 26 dB

Vin = 0.1 V_RMS

BW = 400 Hz to 30 kHz

Vripple = 0.2 V_P-P, C₁= 0.47 µF

BW = A-Weight

C₁= 0.47 µF

BW = A-Weight

Total Harmonic Distortion + Noise

Voltage Gain^{(Note 2)}

THD+N

G_V

-

0.5

G_V+ 1

-80

%

dB

G_V- 1

G_V

-90

-60

-

Shutdown Attenuation

ATT_SD

PSRR

V_NO

-

dB

Power Supply Rejection Ratio

Output Noise Voltage

-40

dB

100

µV_RMS

(Note 2) The typical performance of device is shown Output Power and Voltage Gain. It largely depends on the board layout, parts, and power supply. The typical

values are measured with the device and parts mounting on surface of ROHM’s board directly and soldering thermal pad backside of package to top

layer cupper pattern of the board.

This IC is applicable to only dynamic speaker, not to other loads.

www.rohm.com

TSZ02201-0C1C0EC00760-1-2

4/25

TSZ22111 • 15 • 001

19.Jul.2019 Rev.001

BD783xxEFJ-M Series (Including products under development)

Typical Performance Curves

2.0

4.0

R_L= 8 Ω

SDB = 0 V

R_L= No Load

1.5

1.0

0.5

0.0

3.0

2.0

1.0

0.0

V_{UVLO_DET}

V_{UVLO_REL}

0

1

2

3

4

5

6

7

3

4

5

6

7

Supply Voltage : VDD [V]

Figure 3. Quiescent Current vs Supply Voltage

Figure 4. Shutdown Current vs Supply Voltage

BD78326EFJ-M

BD78306EFJ-M

10

VDD = 5 V

R_L= 8 Ω

1

0.1

0.01

0.1

VDD = 5 V

R_L= 8 Ω

0.01

f = 100 Hz (30 kHz LPF)

f = 1 kHz (BW = 400 Hz to 30 kHz)

f = 10 kHz (BW = 400 Hz to 80 kHz)

f = 1 kHz (BW = 400 Hz to 30 kHz)

f = 10 kHz (BW = 400 Hz to 80 kHz)

0.001

0.01

0.1

1

10

0.01

0.1

1

10

Output Power : P_O[W]

Figure 5. Total Harmonic Distortion + Noise vs Output Power

Figure 6. Total Harmonic Distortion + Noise vs Output Power

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

5/25

BD783xxEFJ-M Series (Including products under development)

Typical Performance Curves – continued

10

BD78326EFJ-M

VDD = 5 V

P_O= 1 W

R_L= 8 Ω

f = 1 kHz

R_L= 8 Ω

BW = 400 Hz to 30 kHz

80 kHz LPF

1

0.1

BD78326EFJ-M

1

BD78306EFJ-M

0.1

0.01

0.001

BD78306EFJ-M

0.01

10

100

1k

Frequency [Hz]

10k

100k

0.001

0.01

0.1

1

10

Output Power : P_O[W]

Figure 7. Total Harmonic Distortion + Noise vs Output Power

Figure 8. Total Harmonic Distortion + Noise vs Frequency

32

2.0

VDD = 5 V

R_L= 8 Ω

P_O= 0.5 W

BD78326EFJ-M

30

28

26

24

22

20

18

16

14

12

10

8

THD+N = 1 %

1.8

THD+N = 10 %

1.6

1.4

1.2

1.0

R_L= 8 Ω

f = 1 kHz

6

0.8

4

BD78306EFJ-M

2

0.6

10

100

1k

Frequency [Hz]

10k

100k

4.0

4.5

5.0

5.5

Supply Voltage : VDD [V]

Figure 9. Voltage Gain vs Frequency

Figure 10. Output Power vs Supply Voltage

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

6/25

BD783xxEFJ-M Series (Including products under development)

Typical Performance Curves - continued

4.0

3.0

2.0

1.0

0.0

0.8

0.6

0.4

0.2

0.0

VDD = 5 V

f = 1 kHz

THD+N = 1 %

THD+N = 10 %

VDD = 5 V

R_L= 8 Ω

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

Output Power : P_O[W]

0

8

16

24

32

Load Resistor : R_L[Ω]

Figure 11. Power Dissipation vs Output Power

Figure 12. Output Power vs Load Resistor

0

-10

-20

-30

-40

-50

-60

-70

-80

0

VDD = 5 V

R_L= 8 Ω

Vripple = 0.2 V_P-P

VDD = 5 V

R_L= 8 Ω

Vin = 0.1 V_RMS

SDB = 0 V

30 kHz LPF

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

BD78326EFJ-M

BD78306EFJ-M

10

100

1k

Frequency [Hz]

10k

100k

10

100

1k

10k

100k

Frequency [Hz]

Figure 14. Power Supply Rejection Ratio vs Frequency

Figure 13. Shutdown Attenuation vs Frequency

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

7/25

BD783xxEFJ-M Series (Including products under development)

Timing Chart

Power on/power down sequences of the VDD pin and the SDB pin are shown.

Follow the sequences below when power on and power down.

1. Power on sequence

(1) Start up voltage of the VDD pin and the SDB pin in order

V

(1) Start up the VDD pin voltage to 4 V or more.

VDD

t

V

(2) Start up the SDB pin voltage from V_ILto V_IH

V_IH

.

SDB

2.0 V

0.3 V

t

t₁

t₂

V_IL

t₂-t₁≤200 μs

V

BIAS

VDD/2

VDD/2 × 90 %

t

t₃

(Maximum Turn On Time) = t₃-t₂= 540 ms

C₁= 0.47 μF

V

t₄-t₃≥0 s

INP

VDD/2

Start input signal

t

t₄

V

OUTP

VDD/2

t

V

OUTN

VDD/2

t

V

BTL

(OUTP-OUTN)

Figure 15. Power On Sequence

Caution:

Start to input signal after waiting maximum Turn On Time 540 ms (C₁= 0.47 μF) after setting the SDB pin voltage high.

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

8/25

BD783xxEFJ-M Series (Including products under development)

Timing Chart – continued

(2) Start up voltage of the VDD pin and the SDB pin simultaneously

V

Start up the VDD pin and the SDB pin voltage simultaneously from 0.8 V or less to 4.0 V or more.

VDD,SDB

4.0 V

0.8 V

t

t₀

t₁

200 μs≤t₁-t₀≤1 s

V

t₁-t₀

t₂-t₀

BIAS

200 µs

200 ms 600 ms (Max)

1 s 1.35 s (Max)

540 ms (Max)

Turn On Time t₂-t₀depends on time period t₁-t₀in which

the VDD pin and the SDB pin voltage are started up.

VDD/2

VDD/2 × 90 %

t₂

(Turn On Time）= t₂-t₀

C₁= 0.47 μF

V

INP

t₃-t₂≥0 s

Start input signal

VDD/2

t

t₃

V

OUTP

VDD/2

When the VDD pin and the SDB pin voltage are started up simultaneously,

Under Voltage Lock Out is released at VDD = 3.95 V (Max) and outputs are started up.

OUTN

VDD/2

t

BTL

(OUTP-

OUTN)

Caution:

Start up waveforms in the figure above, are described in case the VDD pin and the SDB pin voltage are started up

from 0 V to 5 V in time period of 300 ms as an example.

Figure 16. Power On Sequence

1400

1200

1000

800

600

400

200

0

200 400 600 800 1000

t₁- t₀[ms]

Figure 17. Turn On Time t₂– t₀(Max) vs t₁- t₀

Caution:

Start to input signal after waiting maximum Turn On Time after setting the VDD pin and the SDB pin voltage high.

Turn On Time depends on time period in which the VDD pin and the SDB pin voltage are started up.

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

9/25

BD783xxEFJ-M Series (Including products under development)

Timing Chart – continued

2. Power down sequence

(1) Turn down voltage of the SDB pin and the VDD pin in order

V

(2)Turn down the VDD pin voltage.

VDD

t

t₅

V

(1)Turn down the SDB pin voltage to V_ILafter input signal is stopped.

V_IH

SDB

t₅-t₄≥0 s

2.0 V

0.3 V

t

t₁

t₂t₃

V_IL

V

t₃-t₂≤200 μs

BIAS

VDD/2

VDD/2 × 10 %

t

t₄

t₁-t₀≥0 s

(Maximum Turn Off Time) = t₄-t₃= 660 ms

V

C₁= 0.47 μF

INP

Stop input signal

VDD/2

t₀

V

OUTP

VDD/2

t

V

OUTN

VDD/2

t

V

BTL

(OUTP-OUTN)

Figure 18. Power Down Sequence

Caution:

Turn down the VDD pin voltage after waiting maximum Turn Off Time 660 ms (C₁= 0.47 μF) after setting the SDB pin

voltage low. Output waveform may be clipped if signal is still input after Turn Off starts.

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

10/25

BD783xxEFJ-M Series (Including products under development)

Timing Chart – continued

(2) Turn down voltage of the VDD pin and the SDB pin simultaneously

VDD, SDB

Turn down the VDD pin and the SDB pin voltage simultaneously to 0.8 V or less.

Caution : Unless the VDD pin and the SDB pin voltage are turned down 0.8 V or less,

the state Over Current Protection is started may not be released.

4.0 V

0.8 V

t

t₁t₂

t₃

200 μs≤t₃-t₂≤60 s

BIAS

VDD/2

t

t₁-t₀≥0 s

INP

Stop input signal

VDD/2

t₀

OUTP

VDD/2

t

When the VDD pin and the SDB pin voltage are turned down

simultaneously, Under Voltage Lock Out starts at VDD = 3.80 V

(Max) and outputs are pulled down by 10 kΩ.

OUTN

VDD/2

t

BTL

(OUTP-OUTN)

Caution:

Turn down waveforms in the figure above, are described in case the VDD pin and the SDB pin voltage are turned down

from 5 V to 0 V in time period of 300 ms as an example.

Figure 19. Power Down Sequence

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

11/25

BD783xxEFJ-M Series (Including products under development)

Application Examples

VDD

C₄

10 µＦ

6

VDD

C₂

0.47 µＦ

OUTP

5

Input

INP

3

Signal

C₃

0.47 µＦ

OUTN

8

INN

4

2

Over Current

Protection

Thermal

Shutdown

BIAS

C₁

0.47 µＦ

Bias

SDB

1

Under Voltage

Lock Out

GND

7

From

System Control

Figure 20. Single-ended Input

VDD

C₄

10 µＦ

6

VDD

C₂

0.47 µＦ

OUTP

5

Input

INP

3

Signal

C₃

0.47 µＦ

OUTN

8

Input

Signal

INN

4

2

Over Current

Protection

Thermal

Shutdown

BIAS

C₁

0.47 µＦ

Bias

Under Voltage

Lock Out

SDB

1

GND

7

From

System Control

Figure 21. Differential Input

Parts

Capacitor

Parts Symbol

C₁, C₂, C₃

C₄

Value

0.47 µF

10 µF

Manufacturer

MURATA

Product No.

GCM188R71E474KA64

GRT188C81C106ME13

(This is only example of components externally connected.)

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

12/25

19.Jul.2019 Rev.001

BD783xxEFJ-M Series (Including products under development)

Selection of Components Externally Connected

1. Input Coupling Capacitors (C₂, C₃)

The frequency characteristic of input composes high pass filter (Figure 22. HPF) by input impedance Z_INand input

coupling capacitor C₂, C₃(= C_IN).

Cut off frequency f_Cis determined in following equation, set C_INconsidering it.

1

푓 =

퐶

[Hz]

2휋×푍 ×퐶

퐼푁

In case that Z_IN= 45 kΩ and C_IN= 0.47 µF, f_Cis 7.5 Hz (Typ).

G_V

G_V-3 dB

f_C

Figure 22. HPF

The capacitance of C₂and C₃should be the same at the INP and INN pins.

If the capacitance is different, audio characteristics such as THD+N may get worse and pop noise may be large.

2. Power Supply Decoupling Capacitor (C₄)

Power supply decoupling capacitor influences audio characteristics such as THD+N. Locate low ESR capacitor close

to the VDD pin.

Capacitance of C₄should be 10 µF or more.

3. The BIAS pin Capacitor (C₁)

The BIAS pin capacitor influences audio characteristic such as PSRR and THD+N. Locate low ESR capacitor close to

the BIAS pin.

Determine capacitance of C₁included in the range below, including variation and temperature characteristic also.

Turn On Time and Turn Off Time are also determined by capacitance of the BIAS pin capacitor.

Refer to the following section "Turn On and Turn Off".

Capacitance

Min

Typ

Max

C₁

0.35 µF

0.47 µF

0.59 µF

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

13/25

BD783xxEFJ-M Series (Including products under development)

Turn On and Turn Off

This IC has built-in circuit controls transition time of the OUTP pin and the OUTN pin when the operation mode is switched

between active (SDB = High) and shutdown (SDB = Low). It achieves reducing pop noise.

SDB

5 V/div

SDB

5 V/div

OUTP

1 V/div

OUTN

1 V/div

OUTP

1 V/div

OUTN

1 V/div

OUTP - OUTN

5 V/div

OUTP - OUTN

5 V/div

Turn Off Time

Turn On Time

Figure 23. Turn On Waveform

Figure 24. Turn Off Waveform

Following table shows Turn On Time and Turn Off Time with C₁= 0.47 µF.

C₁

Turn On Time

Turn Off Time

270 ms (Typ)

540 ms (Max)

330 ms (Typ)

660 ms (Max)

0.47 µF

Turn On Time is defined as the time until the BIAS pin voltage rises to 90 % of VDD/2 after the SDB pin voltage is Low to

High.

Turn Off Time is defined as the time until the BIAS pin voltage falls to 10 % of VDD/2 after the SDB pin voltage is High to Low.

Turn On Time and Turn Off Time may vary from typical value as the table above.

Maximum value above is calculated assuming that variation of resistors in IC: ±60 % (-40 °C to +105 °C), accuracy of C₁:

±25 % (including variation and temperature characteristic).

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

14/25

BD783xxEFJ-M Series (Including products under development)

Protection Functions

This IC has protection functions that detect several kinds of abnormal conditions and protect itself.

Protection

Functions

Detection and Release Condition

State of Output Pins

Signal Output stopped

and

Latched to High-Z

The OUTP pin or the OUTN pin is shorted to the

VDD pin / the GND pin.

Detection

Release

Detection

Release

Detection

Release

Over Current

Protection

Over Current Protection is released after setting

SDB to Low and waiting Turn Off Time.

After that, the IC becomes normal operation state

by setting the SDB pin to High.

Signal Output available

Signal Output stopped

and

Pulled down by 10 kΩ

(Typ)

Tj : 180 °C (Typ) or more

Thermal Shutdown

Tj : 160 °C (Typ) or less

(released automatically)

Signal Output available

Signal Output stopped

VDD : 3.43 V (Typ) / 3.80 V (Max) or less

Ta = -40 °C to +105 °C

and

Pulled down by 10 kΩ

(Typ)

Under Voltage

Lock Out

VDD : 3.58 V (Typ) / 3.95 V (Max) or more

Ta = -40 °C to +105 °C

Signal Output available

(released automatically)

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

15/25

BD783xxEFJ-M Series (Including products under development)

Protection Functions - continued

1. Over Current Protection

(1) Over Current Protection (Short to the VDD pin)

In case that the OUTP pin or the OUTN pin is shorted to the VDD pin, Over Current Protection starts to stop output

signal and latch output pins to High-Z.

Once Over Current Protection is started, the latch state is not released automatically even if the OUTP pin and the

OUTN pin are not shorted to the VDD pin. Over Current Protection is released by shutdown.

Detection

Release

The OUTP pin or the OUTN pin is shorted to the VDD pin.

Over Current Protection is released after setting the SDB pin to Low and waiting Turn Off Time

(660 ms Max).

After that, it is possible that the IC outputs signal by setting the SDB pin to High.

The OUTP pin and the OUTN pin are not

The OUTP pin or the OUTN pin

shorted to the VDD pin

The voltage of the OUTP pin and the OUTN pin returns to bias

is shorted to the VDD pin

V

voltage (VDD/2),but signal output is still stopped.

OUTP

VDD/2

t

Signal Output is stopped

Over Current Protection

is released

(Over Current Protection)

V

OUTN

VDD/2

t

Signal Output is stopped

(Over Current Protection)

Over Current Protection

is released

V

BTL

(OUTP-OUTN)

Signal Output is stopped

(Over Current Protection)

Set the SDB pin to Low

V

SDB

After Over Current Protection is

released, the IC becomes

active by setting the SDB pin to

High again.

V_IL=0.3 V (Max)

t

V

BIAS

VDD/2

VDD/2 × 10 %

t

660 ms (Max)

Figure 25. Over Current Protection (Short to the VDD pin)

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

16/25

BD783xxEFJ-M Series (Including products under development)

Protection Functions – continued

(2) Over Current Protection (Short to the GND pin)

In case that the OUTP pin or the OUTN pin is shorted to the GND pin, Over Current Protection starts to stop output

signal and latch output pins to High-Z.

Once Over Current Protection is started, the latch state is not released automatically even if the OUTP pin and the

OUTN pin are not shorted to the GND pin, Over Current Protection is released by shutdown.

Detection

Release

The OUTP pin or the OUTN pin is shorted to the GND pin

Over Current Protection is released after setting the SDB pin to Low and waiting Turn Off Time

(660 ms Max).

After that, it is possible that the IC outputs signal by setting the SDB pin to High.

The OUTP pin and the OUTN pin are not

shorted to the GND pin

The OUTP pin or the OUTN pin is

shorted to the GND pin

V

The voltage of the OUTP pin and the OUTN pin returns to bias

voltage (VDD/2),but signal output is still stopped.

OUTP

VDD/2

t

Signal Output is stopped

(Over Current Protection)

Over Current Protection

is released

V

OUTN

VDD/2

t

Signal Output is stopped

(Over Current Protection)

Over Current Protection

is released

V

BTL

(OUTP-OUTN)

t

Signal Output is stopped

(Over Current Protection)

Set the SDB pin to Low

V

SDB

After Over Current Protection is

released, the IC becomes

active by setting the SDB pin to

High again.

V_IL=0.3 V (Max)

t

V

BIAS

VDD/2

VDD/2 × 10 %

t

660 ms (Max)

Figure 26. Over Current Protection (Short to the GND pin)

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

17/25

BD783xxEFJ-M Series (Including products under development)

Protection Functions – continued

2. Thermal Shutdown

In case that Tj rises to 180 °C (Typ) or more, Thermal Shutdown starts to stop output signal and pulls down output pins

by 10 kΩ (Typ).

Detection

Release

Tj : 180 °C (Typ) or more

Tj : 160 °C (Typ) or less

(released automatically)

˚C

180 °C (Typ)

Tj

160 °C (Typ)

t

V

SDB

t

V

OUTP

VDD/2

Signal Output is stopped

t

V

OUTN

VDD/2

Signal Output is stopped

t

V

BTL

(OUTP-OUTN)

Signal Output is stopped

Figure 27. Thermal Shutdown

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

18/25

BD783xxEFJ-M Series (Including products under development)

Protection Functions – continued

3. Under Voltage Lock Out

In case that VDD drops to 3.43 V (Typ) or less, Under Voltage Lock Out starts to stop output signal and pulls down

output pins by 10 kΩ (Typ).

Detection

Release

VDD : 3.43 V (Typ) / 3.80 V (Max) or less

VDD : 3.58 V (Typ) / 3.95 V (Max) or more

(released automatically)

V

VDD

3.58 V (Typ)

3.43 V (Typ)

t

V

SDB

V

OUTP

VDD/2

Signal Output is stopped

V

OUTN

VDD/2

Signal Output is stopped

t

V

BTL

(OUTP-OUTN)

Signal Output is stopped

Figure 28. Under Voltage Lock Out

Caution:

In case that the voltage of VDD falls to 3.80 V (Max) or less by fluctuation of the power supply voltage, note that Under Voltage

Lock Out may start.

Under the condition that R_L= 6 Ω, depending on output signal level, back electromotive force may occur because of the fluctuation

of load current when Under Voltage Lock Out starts and parasitic inductance inside the IC.

Similarly, IR voltage drop may occur because of load current and parasitic resistance of the VDD pin.

These back electromotive force or IR voltage drop may cause intermittent action between “Detection” and “Release”.

This action may be heard as noise under the condition the voltage of the VDD pin is near the threshold voltage of detection.

www.rohm.com

TSZ02201-0C1C0EC00760-1-2

19/25

TSZ22111 • 15 • 001

19.Jul.2019 Rev.001

BD783xxEFJ-M Series (Including products under development)

I/O Equivalence Circuits

No.

Name

Voltage

Equivalent Circuit

Pin Description

VDD

Shutdown

High : Active

Low : Shutdown

SDB

GND

1

SDB

-

VDD

BIAS

2

BIAS

2.5 V

Bias

GND

VDD

3

4

INP

INN

Positive Differential Input

Negative Differential Input

INP

INN

2.5 V

GND

VDD

5

8

OUTP

OUTN

Positive Output

Negative Output

OUTP

OUTN

2.5 V

GND

6

7

VDD

GND

5 V

0 V

Power Supply

VDD

GND

Pin voltage is the value when VDD is 5.0 V and the operating mode is active (The SDB pin is High).

www.rohm.com

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

20/25

TSZ22111 • 15 • 001

BD783xxEFJ-M Series (Including products under development)

Operational Notes

1.

2.

Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply

pins.

Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at

all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic

capacitors.

3.

4.

Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.

Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5.

6.

Recommended Operating Conditions

The function and operation of the IC are guaranteed within the range specified by the recommended operating

conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical

characteristics.

Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow

instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.

Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing

of connections.

7.

Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject

the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should

always be turned off completely before connecting or removing it from the test setup during the inspection process. To

prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and

storage.

8.

9.

Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and

unintentional solder bridge deposited in between pins during assembly to name a few.

Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge

acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause

unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power

supply or ground line.

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

21/25

BD783xxEFJ-M Series (Including products under development)

Operational Notes – continued

10. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be

avoided.

Figure 29. Example of Monolithic IC Structure

11. Ceramic Capacitor

When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

12. Thermal Shutdown Circuit (TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always

be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the

junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj

falls below the TSD threshold, the circuits are automatically restored to normal operation.

Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no

circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat

damage.

13. Over Current Protection Circuit (OCP)

This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This

protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should

not be used in applications characterized by continuous operation or transitioning of the protection circuit.

www.rohm.com

TSZ02201-0C1C0EC00760-1-2

22/25

TSZ22111 • 15 • 001

19.Jul.2019 Rev.001

BD783xxEFJ-M Series (Including products under development)

Ordering Information

B D 7 8 3

x

E

F

J -

ME 2

Part Number

Voltage

Gain

Package

EFJ: HTSOP-J8

Product Rank

M: for Automotive

06: 6 dB

08: 8 dB

Packaging and forming specification

E2: Embossed tape and reel

10: 10 dB

12: 12 dB

14: 14 dB

16: 16 dB

18: 18 dB

20: 20 dB

22: 22 dB

24: 24 dB

26: 26 dB

Lineup

Part Number

Voltage Gain

Part Number Marking

78306

Production Status

Mass Production

Under Development

Mass Production

Under Development

Mass Production

BD78306EFJ-M

BD78308EFJ-M

BD78310EFJ-M

BD78312EFJ-M

BD78314EFJ-M

BD78316EFJ-M

BD78318EFJ-M

BD78320EFJ-M

BD78322EFJ-M

BD78324EFJ-M

BD78326EFJ-M

6 dB

8 dB

78308

78310

78312

78314

78316

78318

78320

78322

10 dB

12 dB

14 dB

16 dB

18 dB

20 dB

22 dB

24 dB

26 dB

78324

78326

Marking Diagram

HTSOP-J8(TOP VIEW)

Part Number Marking

LOT Number

Pin 1 Mark

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

23/25

BD783xxEFJ-M Series (Including products under development)

Physical Dimension and Packing Information

Package Name

HTSOP-J8

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

24/25

BD783xxEFJ-M Series (Including products under development)

Revision History

Date

Revision

001

Changes

19.Jul.2019

New Release

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0C1C0EC00760-1-2

19.Jul.2019 Rev.001

25/25

Notice

Precaution on using ROHM Products

(Note 1)

1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment

,

aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,

bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales

representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any

ROHM’s Products for Specific Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.

Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the

use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our

Products under any special or extraordinary environments or conditions (as exemplified below), your independent

verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.

However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble

cleaning agents for cleaning residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PAA-E

Rev.004

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl₂, H₂S, NH₃, SO₂, and NO₂

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PAA-E

Rev.004

电子百科

产品导航

产品型号BD78306EFJ-M的Datasheet PDF文件预览

BD7820FPE2相关产品

BD7820FPE2相关文章

IC37:专业IC行业平台