It is a hobby project. Please use it at your own risk.
| Functions | Chips |
|---|---|
| Processor | Intel i960 working at 16MHz (N80960SA16 w/o FPU or N80960SB16 with FPU) |
| Peripheral (UART, Timer, and GPIO) | Motorola MC68901P |
| Controller | Altera EPM7032SLC44-10 (or compatible Atmel ATF1502AS-7JX44) |
| 128 KiB RAM | Infineon CY7C1021BN-12ZXC (64K x 16) |
| 64 KiB ROM | 27C512 (64K x 8) with access time below 120ns |
The schematic is here. Though boards built as the schematic is are working correctly, there are issues related to voltage levels.
- 74HCT573 is better for U1, U4 and U11.
- Generation of RW̅ from WR̅ with a schmitt-trigger inverter 74HC14 might not work.
- The voltage level for clk2 pin is not the same for the other pins. Please care about clk2.
X1 for clk2 is 32MHz because clock signal for the processor is generated by dividing clk2.
Controller sources are here. It can be compiled with Quartus II 64-Bit Version 13.0.1 Build 232 Service Pack 1 Web Edition. Please use it at your own risk.
If Atmel ATF1502AS is planned to use instead of EPM7032S, please check Atmel application note 916. Atmel tool POF2JED converts a POF file generated for a corresponding Altera chip into an atmel JED file. The JED file can be converted into an SVF file with another Atmel tool named ATMISP. A JTAG software such as OpenOCD can program the chip with the SVF file. But, it is tough...
A docker container image of cross compiler is available.
- binutils 2.21.1
- gcc 2.95.3
- newlib 1.8.2
Install from the command line
$ docker pull ghcr.io/nkito/i960_sbc:latest
Try the command line
$ docker run -it --rm ghcr.io/nkito/i960_sbc:latest
or the following
$ docker run -it --rm -v /path_to_src_folder_in_host:/src -u (host uid):(host gid) ghcr.io/nkito/i960_sbc:latest
Compiler binaries are in /usr/local/cross/bin.
A sample code is here.