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413 Open 1,497 Closed
413 Open 1,497 Closed
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Issues list

Reduce log output
#4277 opened Nov 23, 2024 by hugolundin
Make all cocotb loggers private
#4275 opened Nov 21, 2024 by ktbarrett 2.0
subscriptable signals (LogicObject)
#4274 opened Nov 20, 2024 by psychogenic
1
GHDL: failed to access one bit of a SLV
#4273 opened Nov 20, 2024 by sebsky-dev
GHDL: fatal error on accessing value property of array of SLV signal constrained by generic category:simulators:ghdl GHDL
#4271 opened Nov 18, 2024 by JvWesterveld
2
Unable to build multiple toplevel hdl files using iverilog
#4269 opened Nov 14, 2024 by aamodini31
1
Split cocotb.SimPhase.Normal into BOTS and Value Change stages type:feature new or enhanced functionality
#4268 opened Nov 13, 2024 by ktbarrett 2.0
analog/mixed signal simulation using cocotb and vcs category:simulators:vcs Synopsys VCS
#4261 opened Nov 11, 2024 by HRET6288
1
Including Xilinx xpm_memory_tdpram in a module has side effects on sampled values of unrelated signals
#4260 opened Nov 11, 2024 by tristancmorgan
2
DLL not found when using Questa Visualizer and miniconda
#4250 opened Nov 7, 2024 by MAtten-Ametek
1
Xcelium's VHPI returns objects for case-misspellings category:simulators:xcelium Cadence Xcelium
#4248 opened Nov 6, 2024 by ktbarrett
NVC DLL missing on Windows builds
#4245 opened Oct 30, 2024 by Gophen
1
Questa VHPI vhpi_get(vhpiIsUpP, ...) does not return correct result category:simulators:questa Mentor Questa status:needs-upstream-report The issue is not yet reported upstream upstream An issue with an upstream simulator
#4236 opened Oct 22, 2024 by ktbarrett
Blank line gets added to log messages
#4223 opened Oct 16, 2024 by Gophen
Verilator: test_cases/test_plusargs fails verilation with compile error on MacOS category:simulators:verilator Verilator upstream An issue with an upstream simulator
#4202 opened Oct 7, 2024 by imphil
1
GHDL master fails to access signals? category:simulators:ghdl GHDL
#4201 opened Oct 7, 2024 by imphil
3
VCS: Make cocotb test suite pass with VCS VPI (Verilog toplevels) category:simulators:vcs Synopsys VCS type:feature new or enhanced functionality
#4194 opened Oct 5, 2024 by imphil
20 tasks
Verilog & VHDL based Mixed Design with UVM Testbench not Working in Synopsys VCS category:codebase:project-automation (makefiles and Python runner) relating to project automation code category:simulators:vcs Synopsys VCS type:bug a bug in existing functionality
#4187 opened Oct 3, 2024 by kashifminhas
1
JUnit output is not valid category:codebase:tests (regression_manager) regarding the code for automating test runs type:bug a bug in existing functionality
#4171 opened Sep 23, 2024 by ktbarrett
4
Python Runner with Xcelium sets value for all parameters in the design with the same name category:codebase:project-automation (makefiles and Python runner) relating to project automation code type:feature new or enhanced functionality
#4164 opened Sep 20, 2024 by Ustin 2.0
2
Allow bool casts of single-bit LogicArray instances type:feature new or enhanced functionality
#4159 opened Sep 18, 2024 by imphil 2.0
3
Enhance performance debugging category:performance performance topics type:feature new or enhanced functionality
#4156 opened Sep 15, 2024 by ktbarrett
The Python runner is not properly escaping string parameters when used with Verilator
#4153 opened Sep 11, 2024 by Ustin
1
1
Getting a orientation of a signal (if it's IN, OUT, or INOUT) type:feature new or enhanced functionality
#4138 opened Aug 27, 2024 by icecase532
1
Cleanup exception types type:cleanup cleanup or refactoring on code, documentation, or other areas
#4124 opened Aug 22, 2024 by ktbarrett
1 of 2 tasks
2.0
1
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