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UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina

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Name		Name	Last commit message	Last commit date
Latest commit History 19 Commits
design_src		design_src
img		img
sim_src		sim_src
Basys-3-Master.xdc		Basys-3-Master.xdc
README.md		README.md
serialPort_2.py		serialPort_2.py
serialPort_crc.py		serialPort_crc.py

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Tp2_UART

UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina

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UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina

verilog uart unc computerarchitecture arquitectura-de-computadores basys3-fpga fcefyn hardwaredescription

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