A FPGA friendly 32 bit RISC-V CPU implementation

The OpenPiton Platform

The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.

合肥工业大学2020年《系统硬件综合设计》（《计算机组成原理》课程设计，CPU）的代码与报告；使用Verilog实现全冒险处理机制的MIPS五段流水CPU，支持MIPS-C3的50条指令。

SUSTech's CS202 Computer_Organization in 2019Spring.

2020年北航计组课设代码 This is the BUAA Computer Orgnization code project files.

My solutions for Bilkent University CS224 Computer Organization Labs (Spring 2019). Includes assembly programming assignments together with various processor designs in System Verilog HDL

🖥️ A collection of SystemVerilog modules and Assembly programs. This repo includes examples of decoders, encoders, binary adders, and interactive games such as Guessing Game implemented in hardware description and assembly languages, illustrating practical applications in digital systems and microprocessor interfacing.

MIPS32 Assembly, Sorting Example in MIPS32 Assembly, CS-F342-Computer-Architecture-Lab

Arm Cortex-M0 based Customizable SoC for IoT Applications

SoC design targeted at the IceBreaker board

CBM 1551 paddle replacement / mass storage using an SD card interfacing with the Commodore C16/116/Plus4 simulating a TCBM bus 1551 disk drive

CS 552 term project : functional design of a microprocessor called the WISC-SP13

A completely self designed (game) computer, implemented in hardware using an FPGA. Basically every component is self designed, from the ISA up to the PCB and software. Project exists to learn more about the fundamentals of computers and to improve my Verilog skills

An experimental operating system project that runs at the BIOs level, but can be a functional operating system.

This is the repo for NTUEE Computer Architecture(EE4039)

ECLair Custom ECL CPU

rjsc5 a 16-bit RISC-V CPU

Innopolis University Computer Architecture course

Computer Organization Projects from Spring 2021 in Marmara University, Istanbul, Turkey