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verilog

Here are 261 public repositories matching this topic...

syntacore / scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

core riscv rtl ip verilog risc-v rv32i rv32e rv32imc rv32emc

Updated Nov 15, 2024
SystemVerilog

hughperkins / VeriGPU

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

machine-learning gpu verification verilog gpu-acceleration hardware-designs risc-v asic-design risc-v-assembly

Updated Nov 22, 2024
SystemVerilog

projf / projf-explore

Project F brings FPGAs to life with exciting open-source designs you can build on.

fpga verilog oshw graphics-hardware

Updated Oct 22, 2024
SystemVerilog

WangXuan95 / USTC-RVSoC

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

cpu fpga riscv rtl verilog systemverilog soc risc-v rv32i softcore

Updated Sep 14, 2023
SystemVerilog

sv-tests

chipsalliance / sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

rtl verilog systemverilog hdl compliance-testing symbiflow

Updated Nov 23, 2024
SystemVerilog

tymonx / logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl

Updated Nov 25, 2019
SystemVerilog

veripool / verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

emacs-lisp verilog systemverilog verilog-mode

Updated Nov 7, 2024
SystemVerilog

apfelaudio / eurorack-pmod

A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.

fpga hardware electronics synthesizer verilog modular-synthesizers kicad eurorack yosys pmod cocotb

Updated Nov 17, 2024
SystemVerilog

tilk / riscv-simple-sv

A simple RISC V core for teaching

riscv verilog risc-v

Updated Dec 30, 2021
SystemVerilog

loykylewong / FPGA-Application-Development-and-Simulation

《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Updated Oct 18, 2024
SystemVerilog

dpretet / axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

arm asic fpga processor riscv verilog soc fpga-soc interconnect amba crossbar riscv32 axi4 axi4-lite riscv64 monodraw axi4-protocol asic-design axi4-full

Updated Nov 21, 2024
SystemVerilog

Xilinx / open-nic-shell

AMD OpenNIC Shell includes the HDL source files

fpga verilog datacenter smartnic network-acceleration

Updated Jun 14, 2024
SystemVerilog

WangXuan95 / UH-JLS

An FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图像压缩。

fpga verilog image-compression image-encoder jpeg-ls

Updated Sep 18, 2024
SystemVerilog

WangXuan95 / FPGA-SATA-HBA

A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。

fpga verilog systemverilog sata sata-controller sata-hba sata-hba-controller sata-core sata-hba-core virtex-7

Updated Sep 14, 2023
SystemVerilog

unixb0y / SystemVerilogSHA256

SHA256 in (System-) Verilog / Open Source FPGA Miner

fpga bitcoin mining verilog sha256 systemverilog icarus-verilog

Updated Mar 10, 2018
SystemVerilog

Siddhi-95 / AHB-to-APB-Bridge-Verification

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

verilog systemverilog uvm

Updated Jul 2, 2023
SystemVerilog

BrianHGinc / BrianHG-DDR3-Controller

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

fpga intel verilog xilinx altera systemverilog lattice hdl testbenches ddr3

Updated Apr 8, 2024
SystemVerilog

cgra4ml

KastnerRG / cgra4ml

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

asic ai fpga neural-network cnn dnn verilog systemverilog axi-stream asic-design hls4ml

Updated Nov 22, 2024
SystemVerilog

mikeroyal / Verilog-SystemVerilog-Guide

Verilog/SystemVerilog Guide

awesome fpga hardware verilog awesome-list systemverilog awesome-readme

Updated Jan 4, 2024
SystemVerilog

Featherweight-IP / fwrisc

Featherweight RISC-V implementation

verilog risc-v zephyr

Updated Jan 17, 2022
SystemVerilog

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