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vlsi

Here are 291 public repositories matching this topic...

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Oct 20, 2024
Python

limbo018 / DREAMPlace

Deep learning toolkit-enabled VLSI placement

deep-learning pytorch gpu-acceleration vlsi vlsi-physical-design vlsi-placement

Updated Oct 29, 2024
C++

OpenTimer / OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

parallel-computing eda circuit-simulator cad verilog cpp17 circuit-simulation vlsi circuit-analysis computer-aided-design vlsi-physical-design sta electronic-design-automation vlsi-circuits static-timing-analysis

Updated May 26, 2023
Verilog

VLSI-EDA / PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Updated Nov 29, 2020
VHDL

Degate

DegateCommunity / Degate

A modern and open-source cross-platform software for chips reverse engineering.

security multi-platform gui cross-platform cpp vhdl reverse-engineering cybersecurity verilog chips vlsi security-tools

Updated Nov 25, 2024
C++

arm-university / VLSI-Fundamentals-Education-Kit

Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor

arm computer-engineering hardware-designs vlsi electrical-engineering cadence-virtuoso microprocessor-implementation synopsys-design devices-circuits-materials

Updated Jul 26, 2024
HTML

efabless / openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

flow asic eda verilog vlsi pnr silicon lvs flows sta gdsii drc pdk openroad openlane sky130 gf180mcu rtl-to-gds

Updated Nov 25, 2024
Python

nitram2342 / degate

Open source software for chip reverse engineering.

visualization gui library vhdl reverse-engineering image-processing verilog chip image-recognition vlsi

Updated Sep 22, 2020
C++

AUCOHL / DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design

Updated Jun 15, 2024
Verilog

phoeniX-Digital-Design / phoeniX

RISC-V Embedded Processor for Approximate Computing

cpu fpga embedded-systems riscv microprocessor computer-architecture vlsi risc-v approximate-computing cpu-design

Updated Nov 2, 2024
Verilog

purdue-onchip / gds2Para

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

parse eda vlsi integrated-circuits interconnect gdsii spef electronic-design-automation vlsi-circuits

Updated Apr 23, 2023
C++

antonblanchard / vlsiffra

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

verilog booth vlsi adder multiplier physical-design dadda amaranth-hdl

Updated Sep 20, 2023
Python

EEcircuit

eelab-dev / EEcircuit

A browser-based SPICE circuit simulator

simulation electronics webassembly wasm spice emscripten circuit vlsi cmos ngspice webgl-plot

Updated Nov 20, 2024
TypeScript

asyncvlsi / act

ACT hardware description language and core tools.

language eda circuit-simulator cad dataflow chp dataflow-programming prs hdl vlsi hardware-description-language production-rules design-automation asynchronous-circuits vlsi-cad asynchronous-vlsi communicating-hardware-processes

Updated Nov 20, 2024
C++

cuhk-eda / Xplace

Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization

gpu eda gpu-acceleration vlsi placement physical-design routability-driven

Updated Nov 23, 2024
C++

drec-fpga-intro

viktor-prutyanov / drec-fpga-intro

Материалы для курсов "Введение в проектирование на языке Verilog" (2024+), "Введение в FPGA и Verilog" (2018-2019)

education asic fpga verilog vlsi risc-v

Updated Nov 4, 2024
Verilog

NTU-LaDS-II / FAN_ATPG

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

cli cpp eda lex verilog yacc vlsi fan-out atpg electronic-design-automation fault-simulation sequential-circuits stuck-at combinational-circuits test-pattern vlsi-testing

Updated Nov 20, 2023
Verilog

hsluoyz / Atalanta

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

verilog vlsi atalanta atpg

Updated May 7, 2024
Verilog

luckyrantanplan / nthu-route

VLSI EDA Global Router

router eda vlsi vlsi-physical-design electronic-design-automation vlsi-circuits globalrouter ispd lattice-graph multi-maze-routing

Updated Jan 22, 2018
C++

ahmed-agiza / EDAViewer

EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!

Updated Jan 6, 2023
JavaScript

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