Digital logic design tool and simulator

A digital logic designer and circuit simulator.

CircuitVerse Primary Code Base

A free, open source, online digital circuit/logic designer.

API of homomorphic binary operations such as binary comparisons or binary divisions using the library HElib

Simulation of Ben Eater's 8 bit computer running in the logic simulator called Digital

Tydi: an open specification for complex data structures over hardware streams

Educational software for modelling and simulation of digital circuits.

Describing RTL circuit in Ruby

Fritzing parts for most common DIP ICs including 74LS Series and more, which is used in Digital Electronics or Logic Circuit and Design.

Generate ATPG for fault detection on Verilog circuits. C++/QT

A visual and constructive framework for teaching digital circuits.

Lectures on Digital Design

Slides for my talk at ACT 2022, 'Fully abstract categorical semantics for digital circuits'

MapBuf: Simultaneous Technology Mapping and Buffer Insertion for HLS Performance Optimization

Motorcycle LCD Digital Speedometer Odometer

Smorgasbord of HDL codes

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.

Generates the Latex Code for the Boolean Function

Extended abstract for my SYCO 8 talk, 'Normalisation by evaluation for digital circuits'